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126 lines
4.6 KiB
126 lines
4.6 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* mpc8610-pcm.h - ALSA PCM interface for the Freescale MPC8610 SoC |
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*/ |
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#ifndef _MPC8610_PCM_H |
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#define _MPC8610_PCM_H |
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struct ccsr_dma { |
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u8 res0[0x100]; |
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struct ccsr_dma_channel { |
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__be32 mr; /* Mode register */ |
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__be32 sr; /* Status register */ |
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__be32 eclndar; /* Current link descriptor extended addr reg */ |
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__be32 clndar; /* Current link descriptor address register */ |
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__be32 satr; /* Source attributes register */ |
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__be32 sar; /* Source address register */ |
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__be32 datr; /* Destination attributes register */ |
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__be32 dar; /* Destination address register */ |
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__be32 bcr; /* Byte count register */ |
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__be32 enlndar; /* Next link descriptor extended address reg */ |
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__be32 nlndar; /* Next link descriptor address register */ |
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u8 res1[4]; |
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__be32 eclsdar; /* Current list descriptor extended addr reg */ |
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__be32 clsdar; /* Current list descriptor address register */ |
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__be32 enlsdar; /* Next list descriptor extended address reg */ |
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__be32 nlsdar; /* Next list descriptor address register */ |
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__be32 ssr; /* Source stride register */ |
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__be32 dsr; /* Destination stride register */ |
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u8 res2[0x38]; |
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} channel[4]; |
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__be32 dgsr; |
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}; |
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#define CCSR_DMA_MR_BWC_DISABLED 0x0F000000 |
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#define CCSR_DMA_MR_BWC_SHIFT 24 |
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#define CCSR_DMA_MR_BWC_MASK 0x0F000000 |
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#define CCSR_DMA_MR_BWC(x) \ |
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((ilog2(x) << CCSR_DMA_MR_BWC_SHIFT) & CCSR_DMA_MR_BWC_MASK) |
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#define CCSR_DMA_MR_EMP_EN 0x00200000 |
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#define CCSR_DMA_MR_EMS_EN 0x00040000 |
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#define CCSR_DMA_MR_DAHTS_MASK 0x00030000 |
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#define CCSR_DMA_MR_DAHTS_1 0x00000000 |
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#define CCSR_DMA_MR_DAHTS_2 0x00010000 |
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#define CCSR_DMA_MR_DAHTS_4 0x00020000 |
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#define CCSR_DMA_MR_DAHTS_8 0x00030000 |
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#define CCSR_DMA_MR_SAHTS_MASK 0x0000C000 |
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#define CCSR_DMA_MR_SAHTS_1 0x00000000 |
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#define CCSR_DMA_MR_SAHTS_2 0x00004000 |
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#define CCSR_DMA_MR_SAHTS_4 0x00008000 |
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#define CCSR_DMA_MR_SAHTS_8 0x0000C000 |
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#define CCSR_DMA_MR_DAHE 0x00002000 |
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#define CCSR_DMA_MR_SAHE 0x00001000 |
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#define CCSR_DMA_MR_SRW 0x00000400 |
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#define CCSR_DMA_MR_EOSIE 0x00000200 |
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#define CCSR_DMA_MR_EOLNIE 0x00000100 |
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#define CCSR_DMA_MR_EOLSIE 0x00000080 |
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#define CCSR_DMA_MR_EIE 0x00000040 |
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#define CCSR_DMA_MR_XFE 0x00000020 |
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#define CCSR_DMA_MR_CDSM_SWSM 0x00000010 |
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#define CCSR_DMA_MR_CA 0x00000008 |
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#define CCSR_DMA_MR_CTM 0x00000004 |
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#define CCSR_DMA_MR_CC 0x00000002 |
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#define CCSR_DMA_MR_CS 0x00000001 |
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#define CCSR_DMA_SR_TE 0x00000080 |
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#define CCSR_DMA_SR_CH 0x00000020 |
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#define CCSR_DMA_SR_PE 0x00000010 |
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#define CCSR_DMA_SR_EOLNI 0x00000008 |
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#define CCSR_DMA_SR_CB 0x00000004 |
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#define CCSR_DMA_SR_EOSI 0x00000002 |
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#define CCSR_DMA_SR_EOLSI 0x00000001 |
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/* ECLNDAR takes bits 32-36 of the CLNDAR register */ |
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static inline u32 CCSR_DMA_ECLNDAR_ADDR(u64 x) |
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{ |
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return (x >> 32) & 0xf; |
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} |
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#define CCSR_DMA_CLNDAR_ADDR(x) ((x) & 0xFFFFFFFE) |
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#define CCSR_DMA_CLNDAR_EOSIE 0x00000008 |
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/* SATR and DATR, combined */ |
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#define CCSR_DMA_ATR_PBATMU 0x20000000 |
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#define CCSR_DMA_ATR_TFLOWLVL_0 0x00000000 |
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#define CCSR_DMA_ATR_TFLOWLVL_1 0x06000000 |
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#define CCSR_DMA_ATR_TFLOWLVL_2 0x08000000 |
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#define CCSR_DMA_ATR_TFLOWLVL_3 0x0C000000 |
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#define CCSR_DMA_ATR_PCIORDER 0x02000000 |
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#define CCSR_DMA_ATR_SME 0x01000000 |
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#define CCSR_DMA_ATR_NOSNOOP 0x00040000 |
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#define CCSR_DMA_ATR_SNOOP 0x00050000 |
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#define CCSR_DMA_ATR_ESAD_MASK 0x0000000F |
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/** |
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* List Descriptor for extended chaining mode DMA operations. |
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* |
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* The CLSDAR register points to the first (in a linked-list) List |
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* Descriptor. Each object must be aligned on a 32-byte boundary. Each |
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* list descriptor points to a linked-list of link Descriptors. |
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*/ |
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struct fsl_dma_list_descriptor { |
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__be64 next; /* Address of next list descriptor */ |
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__be64 first_link; /* Address of first link descriptor */ |
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__be32 source; /* Source stride */ |
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__be32 dest; /* Destination stride */ |
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u8 res[8]; /* Reserved */ |
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} __attribute__ ((aligned(32), packed)); |
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/** |
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* Link Descriptor for basic and extended chaining mode DMA operations. |
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* |
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* A Link Descriptor points to a single DMA buffer. Each link descriptor |
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* must be aligned on a 32-byte boundary. |
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*/ |
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struct fsl_dma_link_descriptor { |
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__be32 source_attr; /* Programmed into SATR register */ |
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__be32 source_addr; /* Programmed into SAR register */ |
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__be32 dest_attr; /* Programmed into DATR register */ |
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__be32 dest_addr; /* Programmed into DAR register */ |
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__be64 next; /* Address of next link descriptor */ |
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__be32 count; /* Byte count */ |
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u8 res[4]; /* Reserved */ |
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} __attribute__ ((aligned(32), packed)); |
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#endif
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