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1169 lines
27 KiB
1169 lines
27 KiB
// SPDX-License-Identifier: GPL-2.0 |
|
/* |
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* ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling |
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* |
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com |
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* |
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* Authors: Felipe Balbi <[email protected]>, |
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* Sebastian Andrzej Siewior <[email protected]> |
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*/ |
|
|
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#include <linux/kernel.h> |
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#include <linux/slab.h> |
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#include <linux/spinlock.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/list.h> |
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#include <linux/dma-mapping.h> |
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|
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#include <linux/usb/ch9.h> |
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#include <linux/usb/gadget.h> |
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#include <linux/usb/composite.h> |
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|
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#include "core.h" |
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#include "debug.h" |
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#include "gadget.h" |
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#include "io.h" |
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|
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static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep); |
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static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, |
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struct dwc3_ep *dep, struct dwc3_request *req); |
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|
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static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep, |
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dma_addr_t buf_dma, u32 len, u32 type, bool chain) |
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{ |
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struct dwc3_trb *trb; |
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struct dwc3 *dwc; |
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|
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dwc = dep->dwc; |
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trb = &dwc->ep0_trb[dep->trb_enqueue]; |
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|
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if (chain) |
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dep->trb_enqueue++; |
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|
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trb->bpl = lower_32_bits(buf_dma); |
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trb->bph = upper_32_bits(buf_dma); |
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trb->size = len; |
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trb->ctrl = type; |
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|
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trb->ctrl |= (DWC3_TRB_CTRL_HWO |
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| DWC3_TRB_CTRL_ISP_IMI); |
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|
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if (chain) |
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trb->ctrl |= DWC3_TRB_CTRL_CHN; |
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else |
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trb->ctrl |= (DWC3_TRB_CTRL_IOC |
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| DWC3_TRB_CTRL_LST); |
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|
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trace_dwc3_prepare_trb(dep, trb); |
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} |
|
|
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static int dwc3_ep0_start_trans(struct dwc3_ep *dep) |
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{ |
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struct dwc3_gadget_ep_cmd_params params; |
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struct dwc3 *dwc; |
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int ret; |
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|
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if (dep->flags & DWC3_EP_TRANSFER_STARTED) |
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return 0; |
|
|
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dwc = dep->dwc; |
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|
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memset(¶ms, 0, sizeof(params)); |
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params.param0 = upper_32_bits(dwc->ep0_trb_addr); |
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params.param1 = lower_32_bits(dwc->ep0_trb_addr); |
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|
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ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, ¶ms); |
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if (ret < 0) |
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return ret; |
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|
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dwc->ep0_next_event = DWC3_EP0_COMPLETE; |
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|
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return 0; |
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} |
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|
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static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, |
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struct dwc3_request *req) |
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{ |
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struct dwc3 *dwc = dep->dwc; |
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|
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req->request.actual = 0; |
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req->request.status = -EINPROGRESS; |
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req->epnum = dep->number; |
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|
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list_add_tail(&req->list, &dep->pending_list); |
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|
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/* |
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* Gadget driver might not be quick enough to queue a request |
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* before we get a Transfer Not Ready event on this endpoint. |
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* |
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* In that case, we will set DWC3_EP_PENDING_REQUEST. When that |
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* flag is set, it's telling us that as soon as Gadget queues the |
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* required request, we should kick the transfer here because the |
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* IRQ we were waiting for is long gone. |
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*/ |
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if (dep->flags & DWC3_EP_PENDING_REQUEST) { |
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unsigned int direction; |
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|
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direction = !!(dep->flags & DWC3_EP0_DIR_IN); |
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|
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if (dwc->ep0state != EP0_DATA_PHASE) { |
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dev_WARN(dwc->dev, "Unexpected pending request\n"); |
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return 0; |
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} |
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|
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__dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); |
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|
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dep->flags &= ~(DWC3_EP_PENDING_REQUEST | |
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DWC3_EP0_DIR_IN); |
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|
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return 0; |
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} |
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|
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/* |
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* In case gadget driver asked us to delay the STATUS phase, |
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* handle it here. |
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*/ |
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if (dwc->delayed_status) { |
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unsigned int direction; |
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|
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direction = !dwc->ep0_expect_in; |
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dwc->delayed_status = false; |
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usb_gadget_set_state(dwc->gadget, USB_STATE_CONFIGURED); |
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|
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if (dwc->ep0state == EP0_STATUS_PHASE) |
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__dwc3_ep0_do_control_status(dwc, dwc->eps[direction]); |
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|
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return 0; |
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} |
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|
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/* |
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* Unfortunately we have uncovered a limitation wrt the Data Phase. |
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* |
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* Section 9.4 says we can wait for the XferNotReady(DATA) event to |
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* come before issueing Start Transfer command, but if we do, we will |
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* miss situations where the host starts another SETUP phase instead of |
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* the DATA phase. Such cases happen at least on TD.7.6 of the Link |
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* Layer Compliance Suite. |
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* |
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* The problem surfaces due to the fact that in case of back-to-back |
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* SETUP packets there will be no XferNotReady(DATA) generated and we |
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* will be stuck waiting for XferNotReady(DATA) forever. |
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* |
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* By looking at tables 9-13 and 9-14 of the Databook, we can see that |
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* it tells us to start Data Phase right away. It also mentions that if |
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* we receive a SETUP phase instead of the DATA phase, core will issue |
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* XferComplete for the DATA phase, before actually initiating it in |
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* the wire, with the TRB's status set to "SETUP_PENDING". Such status |
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* can only be used to print some debugging logs, as the core expects |
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* us to go through to the STATUS phase and start a CONTROL_STATUS TRB, |
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* just so it completes right away, without transferring anything and, |
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* only then, we can go back to the SETUP phase. |
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* |
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* Because of this scenario, SNPS decided to change the programming |
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* model of control transfers and support on-demand transfers only for |
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* the STATUS phase. To fix the issue we have now, we will always wait |
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* for gadget driver to queue the DATA phase's struct usb_request, then |
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* start it right away. |
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* |
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* If we're actually in a 2-stage transfer, we will wait for |
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* XferNotReady(STATUS). |
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*/ |
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if (dwc->three_stage_setup) { |
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unsigned int direction; |
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|
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direction = dwc->ep0_expect_in; |
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dwc->ep0state = EP0_DATA_PHASE; |
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|
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__dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); |
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|
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dep->flags &= ~DWC3_EP0_DIR_IN; |
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} |
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|
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return 0; |
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} |
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|
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int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, |
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gfp_t gfp_flags) |
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{ |
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struct dwc3_request *req = to_dwc3_request(request); |
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struct dwc3_ep *dep = to_dwc3_ep(ep); |
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struct dwc3 *dwc = dep->dwc; |
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|
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unsigned long flags; |
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|
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int ret; |
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|
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spin_lock_irqsave(&dwc->lock, flags); |
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if (!dep->endpoint.desc || !dwc->pullups_connected) { |
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dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n", |
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dep->name); |
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ret = -ESHUTDOWN; |
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goto out; |
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} |
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|
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/* we share one TRB for ep0/1 */ |
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if (!list_empty(&dep->pending_list)) { |
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ret = -EBUSY; |
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goto out; |
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} |
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|
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ret = __dwc3_gadget_ep0_queue(dep, req); |
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|
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out: |
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spin_unlock_irqrestore(&dwc->lock, flags); |
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|
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return ret; |
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} |
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|
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static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) |
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{ |
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struct dwc3_ep *dep; |
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|
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/* reinitialize physical ep1 */ |
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dep = dwc->eps[1]; |
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dep->flags = DWC3_EP_ENABLED; |
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|
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/* stall is always issued on EP0 */ |
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dep = dwc->eps[0]; |
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__dwc3_gadget_ep_set_halt(dep, 1, false); |
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dep->flags = DWC3_EP_ENABLED; |
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dwc->delayed_status = false; |
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|
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if (!list_empty(&dep->pending_list)) { |
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struct dwc3_request *req; |
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|
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req = next_request(&dep->pending_list); |
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dwc3_gadget_giveback(dep, req, -ECONNRESET); |
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} |
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|
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dwc->ep0state = EP0_SETUP_PHASE; |
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dwc3_ep0_out_start(dwc); |
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} |
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|
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int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) |
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{ |
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struct dwc3_ep *dep = to_dwc3_ep(ep); |
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struct dwc3 *dwc = dep->dwc; |
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|
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dwc3_ep0_stall_and_restart(dwc); |
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|
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return 0; |
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} |
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|
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int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) |
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{ |
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struct dwc3_ep *dep = to_dwc3_ep(ep); |
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struct dwc3 *dwc = dep->dwc; |
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unsigned long flags; |
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int ret; |
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|
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spin_lock_irqsave(&dwc->lock, flags); |
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ret = __dwc3_gadget_ep0_set_halt(ep, value); |
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spin_unlock_irqrestore(&dwc->lock, flags); |
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|
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return ret; |
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} |
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|
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void dwc3_ep0_out_start(struct dwc3 *dwc) |
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{ |
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struct dwc3_ep *dep; |
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int ret; |
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|
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complete(&dwc->ep0_in_setup); |
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|
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dep = dwc->eps[0]; |
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dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8, |
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DWC3_TRBCTL_CONTROL_SETUP, false); |
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ret = dwc3_ep0_start_trans(dep); |
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WARN_ON(ret < 0); |
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} |
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|
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static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) |
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{ |
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struct dwc3_ep *dep; |
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u32 windex = le16_to_cpu(wIndex_le); |
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u32 epnum; |
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|
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epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1; |
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if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) |
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epnum |= 1; |
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|
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dep = dwc->eps[epnum]; |
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if (dep->flags & DWC3_EP_ENABLED) |
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return dep; |
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|
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return NULL; |
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} |
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|
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static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req) |
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{ |
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} |
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/* |
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* ch 9.4.5 |
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*/ |
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static int dwc3_ep0_handle_status(struct dwc3 *dwc, |
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struct usb_ctrlrequest *ctrl) |
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{ |
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struct dwc3_ep *dep; |
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u32 recip; |
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u32 value; |
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u32 reg; |
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u16 usb_status = 0; |
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__le16 *response_pkt; |
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|
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/* We don't support PTM_STATUS */ |
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value = le16_to_cpu(ctrl->wValue); |
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if (value != 0) |
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return -EINVAL; |
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|
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recip = ctrl->bRequestType & USB_RECIP_MASK; |
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switch (recip) { |
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case USB_RECIP_DEVICE: |
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/* |
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* LTM will be set once we know how to set this in HW. |
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*/ |
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usb_status |= dwc->gadget->is_selfpowered; |
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|
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if ((dwc->speed == DWC3_DSTS_SUPERSPEED) || |
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(dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) { |
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reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
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if (reg & DWC3_DCTL_INITU1ENA) |
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usb_status |= 1 << USB_DEV_STAT_U1_ENABLED; |
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if (reg & DWC3_DCTL_INITU2ENA) |
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usb_status |= 1 << USB_DEV_STAT_U2_ENABLED; |
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} |
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|
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break; |
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|
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case USB_RECIP_INTERFACE: |
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/* |
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* Function Remote Wake Capable D0 |
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* Function Remote Wakeup D1 |
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*/ |
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break; |
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|
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case USB_RECIP_ENDPOINT: |
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dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); |
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if (!dep) |
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return -EINVAL; |
|
|
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if (dep->flags & DWC3_EP_STALL) |
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usb_status = 1 << USB_ENDPOINT_HALT; |
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break; |
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default: |
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return -EINVAL; |
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} |
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|
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response_pkt = (__le16 *) dwc->setup_buf; |
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*response_pkt = cpu_to_le16(usb_status); |
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|
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dep = dwc->eps[0]; |
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dwc->ep0_usb_req.dep = dep; |
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dwc->ep0_usb_req.request.length = sizeof(*response_pkt); |
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dwc->ep0_usb_req.request.buf = dwc->setup_buf; |
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dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl; |
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|
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return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); |
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} |
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|
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static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state, |
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int set) |
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{ |
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u32 reg; |
|
|
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if (state != USB_STATE_CONFIGURED) |
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return -EINVAL; |
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if ((dwc->speed != DWC3_DSTS_SUPERSPEED) && |
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(dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS)) |
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return -EINVAL; |
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if (set && dwc->dis_u1_entry_quirk) |
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return -EINVAL; |
|
|
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reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
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if (set) |
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reg |= DWC3_DCTL_INITU1ENA; |
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else |
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reg &= ~DWC3_DCTL_INITU1ENA; |
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dwc3_writel(dwc->regs, DWC3_DCTL, reg); |
|
|
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return 0; |
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} |
|
|
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static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state, |
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int set) |
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{ |
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u32 reg; |
|
|
|
|
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if (state != USB_STATE_CONFIGURED) |
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return -EINVAL; |
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if ((dwc->speed != DWC3_DSTS_SUPERSPEED) && |
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(dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS)) |
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return -EINVAL; |
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if (set && dwc->dis_u2_entry_quirk) |
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return -EINVAL; |
|
|
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reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
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if (set) |
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reg |= DWC3_DCTL_INITU2ENA; |
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else |
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reg &= ~DWC3_DCTL_INITU2ENA; |
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dwc3_writel(dwc->regs, DWC3_DCTL, reg); |
|
|
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return 0; |
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} |
|
|
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static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state, |
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u32 wIndex, int set) |
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{ |
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if ((wIndex & 0xff) != 0) |
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return -EINVAL; |
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if (!set) |
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return -EINVAL; |
|
|
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switch (wIndex >> 8) { |
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case USB_TEST_J: |
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case USB_TEST_K: |
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case USB_TEST_SE0_NAK: |
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case USB_TEST_PACKET: |
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case USB_TEST_FORCE_ENABLE: |
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dwc->test_mode_nr = wIndex >> 8; |
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dwc->test_mode = true; |
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break; |
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default: |
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return -EINVAL; |
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} |
|
|
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return 0; |
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} |
|
|
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static int dwc3_ep0_handle_device(struct dwc3 *dwc, |
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struct usb_ctrlrequest *ctrl, int set) |
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{ |
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enum usb_device_state state; |
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u32 wValue; |
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u32 wIndex; |
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int ret = 0; |
|
|
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wValue = le16_to_cpu(ctrl->wValue); |
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wIndex = le16_to_cpu(ctrl->wIndex); |
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state = dwc->gadget->state; |
|
|
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switch (wValue) { |
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case USB_DEVICE_REMOTE_WAKEUP: |
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break; |
|
/* |
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* 9.4.1 says only only for SS, in AddressState only for |
|
* default control pipe |
|
*/ |
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case USB_DEVICE_U1_ENABLE: |
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ret = dwc3_ep0_handle_u1(dwc, state, set); |
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break; |
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case USB_DEVICE_U2_ENABLE: |
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ret = dwc3_ep0_handle_u2(dwc, state, set); |
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break; |
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case USB_DEVICE_LTM_ENABLE: |
|
ret = -EINVAL; |
|
break; |
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case USB_DEVICE_TEST_MODE: |
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ret = dwc3_ep0_handle_test(dwc, state, wIndex, set); |
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break; |
|
default: |
|
ret = -EINVAL; |
|
} |
|
|
|
return ret; |
|
} |
|
|
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static int dwc3_ep0_handle_intf(struct dwc3 *dwc, |
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struct usb_ctrlrequest *ctrl, int set) |
|
{ |
|
u32 wValue; |
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int ret = 0; |
|
|
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wValue = le16_to_cpu(ctrl->wValue); |
|
|
|
switch (wValue) { |
|
case USB_INTRF_FUNC_SUSPEND: |
|
/* |
|
* REVISIT: Ideally we would enable some low power mode here, |
|
* however it's unclear what we should be doing here. |
|
* |
|
* For now, we're not doing anything, just making sure we return |
|
* 0 so USB Command Verifier tests pass without any errors. |
|
*/ |
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break; |
|
default: |
|
ret = -EINVAL; |
|
} |
|
|
|
return ret; |
|
} |
|
|
|
static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc, |
|
struct usb_ctrlrequest *ctrl, int set) |
|
{ |
|
struct dwc3_ep *dep; |
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u32 wValue; |
|
int ret; |
|
|
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wValue = le16_to_cpu(ctrl->wValue); |
|
|
|
switch (wValue) { |
|
case USB_ENDPOINT_HALT: |
|
dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); |
|
if (!dep) |
|
return -EINVAL; |
|
|
|
if (set == 0 && (dep->flags & DWC3_EP_WEDGE)) |
|
break; |
|
|
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ret = __dwc3_gadget_ep_set_halt(dep, set, true); |
|
if (ret) |
|
return -EINVAL; |
|
|
|
/* ClearFeature(Halt) may need delayed status */ |
|
if (!set && (dep->flags & DWC3_EP_END_TRANSFER_PENDING)) |
|
return USB_GADGET_DELAYED_STATUS; |
|
|
|
break; |
|
default: |
|
return -EINVAL; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int dwc3_ep0_handle_feature(struct dwc3 *dwc, |
|
struct usb_ctrlrequest *ctrl, int set) |
|
{ |
|
u32 recip; |
|
int ret; |
|
|
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recip = ctrl->bRequestType & USB_RECIP_MASK; |
|
|
|
switch (recip) { |
|
case USB_RECIP_DEVICE: |
|
ret = dwc3_ep0_handle_device(dwc, ctrl, set); |
|
break; |
|
case USB_RECIP_INTERFACE: |
|
ret = dwc3_ep0_handle_intf(dwc, ctrl, set); |
|
break; |
|
case USB_RECIP_ENDPOINT: |
|
ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set); |
|
break; |
|
default: |
|
ret = -EINVAL; |
|
} |
|
|
|
return ret; |
|
} |
|
|
|
static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) |
|
{ |
|
enum usb_device_state state = dwc->gadget->state; |
|
u32 addr; |
|
u32 reg; |
|
|
|
addr = le16_to_cpu(ctrl->wValue); |
|
if (addr > 127) { |
|
dev_err(dwc->dev, "invalid device address %d\n", addr); |
|
return -EINVAL; |
|
} |
|
|
|
if (state == USB_STATE_CONFIGURED) { |
|
dev_err(dwc->dev, "can't SetAddress() from Configured State\n"); |
|
return -EINVAL; |
|
} |
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
|
reg &= ~(DWC3_DCFG_DEVADDR_MASK); |
|
reg |= DWC3_DCFG_DEVADDR(addr); |
|
dwc3_writel(dwc->regs, DWC3_DCFG, reg); |
|
|
|
if (addr) |
|
usb_gadget_set_state(dwc->gadget, USB_STATE_ADDRESS); |
|
else |
|
usb_gadget_set_state(dwc->gadget, USB_STATE_DEFAULT); |
|
|
|
return 0; |
|
} |
|
|
|
static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) |
|
{ |
|
int ret; |
|
|
|
spin_unlock(&dwc->lock); |
|
ret = dwc->gadget_driver->setup(dwc->gadget, ctrl); |
|
spin_lock(&dwc->lock); |
|
return ret; |
|
} |
|
|
|
static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) |
|
{ |
|
enum usb_device_state state = dwc->gadget->state; |
|
u32 cfg; |
|
int ret; |
|
u32 reg; |
|
|
|
cfg = le16_to_cpu(ctrl->wValue); |
|
|
|
switch (state) { |
|
case USB_STATE_DEFAULT: |
|
return -EINVAL; |
|
|
|
case USB_STATE_ADDRESS: |
|
ret = dwc3_ep0_delegate_req(dwc, ctrl); |
|
/* if the cfg matches and the cfg is non zero */ |
|
if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) { |
|
|
|
/* |
|
* only change state if set_config has already |
|
* been processed. If gadget driver returns |
|
* USB_GADGET_DELAYED_STATUS, we will wait |
|
* to change the state on the next usb_ep_queue() |
|
*/ |
|
if (ret == 0) |
|
usb_gadget_set_state(dwc->gadget, |
|
USB_STATE_CONFIGURED); |
|
|
|
/* |
|
* Enable transition to U1/U2 state when |
|
* nothing is pending from application. |
|
*/ |
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
|
if (!dwc->dis_u1_entry_quirk) |
|
reg |= DWC3_DCTL_ACCEPTU1ENA; |
|
if (!dwc->dis_u2_entry_quirk) |
|
reg |= DWC3_DCTL_ACCEPTU2ENA; |
|
dwc3_writel(dwc->regs, DWC3_DCTL, reg); |
|
} |
|
break; |
|
|
|
case USB_STATE_CONFIGURED: |
|
ret = dwc3_ep0_delegate_req(dwc, ctrl); |
|
if (!cfg && !ret) |
|
usb_gadget_set_state(dwc->gadget, |
|
USB_STATE_ADDRESS); |
|
break; |
|
default: |
|
ret = -EINVAL; |
|
} |
|
return ret; |
|
} |
|
|
|
static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req) |
|
{ |
|
struct dwc3_ep *dep = to_dwc3_ep(ep); |
|
struct dwc3 *dwc = dep->dwc; |
|
|
|
u32 param = 0; |
|
u32 reg; |
|
|
|
struct timing { |
|
u8 u1sel; |
|
u8 u1pel; |
|
__le16 u2sel; |
|
__le16 u2pel; |
|
} __packed timing; |
|
|
|
int ret; |
|
|
|
memcpy(&timing, req->buf, sizeof(timing)); |
|
|
|
dwc->u1sel = timing.u1sel; |
|
dwc->u1pel = timing.u1pel; |
|
dwc->u2sel = le16_to_cpu(timing.u2sel); |
|
dwc->u2pel = le16_to_cpu(timing.u2pel); |
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
|
if (reg & DWC3_DCTL_INITU2ENA) |
|
param = dwc->u2pel; |
|
if (reg & DWC3_DCTL_INITU1ENA) |
|
param = dwc->u1pel; |
|
|
|
/* |
|
* According to Synopsys Databook, if parameter is |
|
* greater than 125, a value of zero should be |
|
* programmed in the register. |
|
*/ |
|
if (param > 125) |
|
param = 0; |
|
|
|
/* now that we have the time, issue DGCMD Set Sel */ |
|
ret = dwc3_send_gadget_generic_command(dwc, |
|
DWC3_DGCMD_SET_PERIODIC_PAR, param); |
|
WARN_ON(ret < 0); |
|
} |
|
|
|
static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) |
|
{ |
|
struct dwc3_ep *dep; |
|
enum usb_device_state state = dwc->gadget->state; |
|
u16 wLength; |
|
|
|
if (state == USB_STATE_DEFAULT) |
|
return -EINVAL; |
|
|
|
wLength = le16_to_cpu(ctrl->wLength); |
|
|
|
if (wLength != 6) { |
|
dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n", |
|
wLength); |
|
return -EINVAL; |
|
} |
|
|
|
/* |
|
* To handle Set SEL we need to receive 6 bytes from Host. So let's |
|
* queue a usb_request for 6 bytes. |
|
* |
|
* Remember, though, this controller can't handle non-wMaxPacketSize |
|
* aligned transfers on the OUT direction, so we queue a request for |
|
* wMaxPacketSize instead. |
|
*/ |
|
dep = dwc->eps[0]; |
|
dwc->ep0_usb_req.dep = dep; |
|
dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket; |
|
dwc->ep0_usb_req.request.buf = dwc->setup_buf; |
|
dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl; |
|
|
|
return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); |
|
} |
|
|
|
static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) |
|
{ |
|
u16 wLength; |
|
u16 wValue; |
|
u16 wIndex; |
|
|
|
wValue = le16_to_cpu(ctrl->wValue); |
|
wLength = le16_to_cpu(ctrl->wLength); |
|
wIndex = le16_to_cpu(ctrl->wIndex); |
|
|
|
if (wIndex || wLength) |
|
return -EINVAL; |
|
|
|
dwc->gadget->isoch_delay = wValue; |
|
|
|
return 0; |
|
} |
|
|
|
static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) |
|
{ |
|
int ret; |
|
|
|
switch (ctrl->bRequest) { |
|
case USB_REQ_GET_STATUS: |
|
ret = dwc3_ep0_handle_status(dwc, ctrl); |
|
break; |
|
case USB_REQ_CLEAR_FEATURE: |
|
ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); |
|
break; |
|
case USB_REQ_SET_FEATURE: |
|
ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); |
|
break; |
|
case USB_REQ_SET_ADDRESS: |
|
ret = dwc3_ep0_set_address(dwc, ctrl); |
|
break; |
|
case USB_REQ_SET_CONFIGURATION: |
|
ret = dwc3_ep0_set_config(dwc, ctrl); |
|
break; |
|
case USB_REQ_SET_SEL: |
|
ret = dwc3_ep0_set_sel(dwc, ctrl); |
|
break; |
|
case USB_REQ_SET_ISOCH_DELAY: |
|
ret = dwc3_ep0_set_isoch_delay(dwc, ctrl); |
|
break; |
|
default: |
|
ret = dwc3_ep0_delegate_req(dwc, ctrl); |
|
break; |
|
} |
|
|
|
return ret; |
|
} |
|
|
|
static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, |
|
const struct dwc3_event_depevt *event) |
|
{ |
|
struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb; |
|
int ret = -EINVAL; |
|
u32 len; |
|
|
|
if (!dwc->gadget_driver) |
|
goto out; |
|
|
|
trace_dwc3_ctrl_req(ctrl); |
|
|
|
len = le16_to_cpu(ctrl->wLength); |
|
if (!len) { |
|
dwc->three_stage_setup = false; |
|
dwc->ep0_expect_in = false; |
|
dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; |
|
} else { |
|
dwc->three_stage_setup = true; |
|
dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN); |
|
dwc->ep0_next_event = DWC3_EP0_NRDY_DATA; |
|
} |
|
|
|
if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) |
|
ret = dwc3_ep0_std_request(dwc, ctrl); |
|
else |
|
ret = dwc3_ep0_delegate_req(dwc, ctrl); |
|
|
|
if (ret == USB_GADGET_DELAYED_STATUS) |
|
dwc->delayed_status = true; |
|
|
|
out: |
|
if (ret < 0) |
|
dwc3_ep0_stall_and_restart(dwc); |
|
} |
|
|
|
static void dwc3_ep0_complete_data(struct dwc3 *dwc, |
|
const struct dwc3_event_depevt *event) |
|
{ |
|
struct dwc3_request *r; |
|
struct usb_request *ur; |
|
struct dwc3_trb *trb; |
|
struct dwc3_ep *ep0; |
|
u32 transferred = 0; |
|
u32 status; |
|
u32 length; |
|
u8 epnum; |
|
|
|
epnum = event->endpoint_number; |
|
ep0 = dwc->eps[0]; |
|
|
|
dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; |
|
trb = dwc->ep0_trb; |
|
trace_dwc3_complete_trb(ep0, trb); |
|
|
|
r = next_request(&ep0->pending_list); |
|
if (!r) |
|
return; |
|
|
|
status = DWC3_TRB_SIZE_TRBSTS(trb->size); |
|
if (status == DWC3_TRBSTS_SETUP_PENDING) { |
|
dwc->setup_packet_pending = true; |
|
if (r) |
|
dwc3_gadget_giveback(ep0, r, -ECONNRESET); |
|
|
|
return; |
|
} |
|
|
|
ur = &r->request; |
|
|
|
length = trb->size & DWC3_TRB_SIZE_MASK; |
|
transferred = ur->length - length; |
|
ur->actual += transferred; |
|
|
|
if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) && |
|
ur->length && ur->zero) || dwc->ep0_bounced) { |
|
trb++; |
|
trb->ctrl &= ~DWC3_TRB_CTRL_HWO; |
|
trace_dwc3_complete_trb(ep0, trb); |
|
|
|
if (r->direction) |
|
dwc->eps[1]->trb_enqueue = 0; |
|
else |
|
dwc->eps[0]->trb_enqueue = 0; |
|
|
|
dwc->ep0_bounced = false; |
|
} |
|
|
|
if ((epnum & 1) && ur->actual < ur->length) |
|
dwc3_ep0_stall_and_restart(dwc); |
|
else |
|
dwc3_gadget_giveback(ep0, r, 0); |
|
} |
|
|
|
static void dwc3_ep0_complete_status(struct dwc3 *dwc, |
|
const struct dwc3_event_depevt *event) |
|
{ |
|
struct dwc3_request *r; |
|
struct dwc3_ep *dep; |
|
struct dwc3_trb *trb; |
|
u32 status; |
|
|
|
dep = dwc->eps[0]; |
|
trb = dwc->ep0_trb; |
|
|
|
trace_dwc3_complete_trb(dep, trb); |
|
|
|
if (!list_empty(&dep->pending_list)) { |
|
r = next_request(&dep->pending_list); |
|
|
|
dwc3_gadget_giveback(dep, r, 0); |
|
} |
|
|
|
if (dwc->test_mode) { |
|
int ret; |
|
|
|
ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr); |
|
if (ret < 0) { |
|
dev_err(dwc->dev, "invalid test #%d\n", |
|
dwc->test_mode_nr); |
|
dwc3_ep0_stall_and_restart(dwc); |
|
return; |
|
} |
|
} |
|
|
|
status = DWC3_TRB_SIZE_TRBSTS(trb->size); |
|
if (status == DWC3_TRBSTS_SETUP_PENDING) |
|
dwc->setup_packet_pending = true; |
|
|
|
dwc->ep0state = EP0_SETUP_PHASE; |
|
dwc3_ep0_out_start(dwc); |
|
} |
|
|
|
static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, |
|
const struct dwc3_event_depevt *event) |
|
{ |
|
struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; |
|
|
|
dep->flags &= ~DWC3_EP_TRANSFER_STARTED; |
|
dep->resource_index = 0; |
|
dwc->setup_packet_pending = false; |
|
|
|
switch (dwc->ep0state) { |
|
case EP0_SETUP_PHASE: |
|
dwc3_ep0_inspect_setup(dwc, event); |
|
break; |
|
|
|
case EP0_DATA_PHASE: |
|
dwc3_ep0_complete_data(dwc, event); |
|
break; |
|
|
|
case EP0_STATUS_PHASE: |
|
dwc3_ep0_complete_status(dwc, event); |
|
break; |
|
default: |
|
WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); |
|
} |
|
} |
|
|
|
static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, |
|
struct dwc3_ep *dep, struct dwc3_request *req) |
|
{ |
|
unsigned int trb_length = 0; |
|
int ret; |
|
|
|
req->direction = !!dep->number; |
|
|
|
if (req->request.length == 0) { |
|
if (!req->direction) |
|
trb_length = dep->endpoint.maxpacket; |
|
|
|
dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, trb_length, |
|
DWC3_TRBCTL_CONTROL_DATA, false); |
|
ret = dwc3_ep0_start_trans(dep); |
|
} else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) |
|
&& (dep->number == 0)) { |
|
u32 maxpacket; |
|
u32 rem; |
|
|
|
ret = usb_gadget_map_request_by_dev(dwc->sysdev, |
|
&req->request, dep->number); |
|
if (ret) |
|
return; |
|
|
|
maxpacket = dep->endpoint.maxpacket; |
|
rem = req->request.length % maxpacket; |
|
dwc->ep0_bounced = true; |
|
|
|
/* prepare normal TRB */ |
|
dwc3_ep0_prepare_one_trb(dep, req->request.dma, |
|
req->request.length, |
|
DWC3_TRBCTL_CONTROL_DATA, |
|
true); |
|
|
|
req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1]; |
|
|
|
/* Now prepare one extra TRB to align transfer size */ |
|
dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, |
|
maxpacket - rem, |
|
DWC3_TRBCTL_CONTROL_DATA, |
|
false); |
|
ret = dwc3_ep0_start_trans(dep); |
|
} else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) && |
|
req->request.length && req->request.zero) { |
|
|
|
ret = usb_gadget_map_request_by_dev(dwc->sysdev, |
|
&req->request, dep->number); |
|
if (ret) |
|
return; |
|
|
|
/* prepare normal TRB */ |
|
dwc3_ep0_prepare_one_trb(dep, req->request.dma, |
|
req->request.length, |
|
DWC3_TRBCTL_CONTROL_DATA, |
|
true); |
|
|
|
req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1]; |
|
|
|
if (!req->direction) |
|
trb_length = dep->endpoint.maxpacket; |
|
|
|
/* Now prepare one extra TRB to align transfer size */ |
|
dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, |
|
trb_length, DWC3_TRBCTL_CONTROL_DATA, |
|
false); |
|
ret = dwc3_ep0_start_trans(dep); |
|
} else { |
|
ret = usb_gadget_map_request_by_dev(dwc->sysdev, |
|
&req->request, dep->number); |
|
if (ret) |
|
return; |
|
|
|
dwc3_ep0_prepare_one_trb(dep, req->request.dma, |
|
req->request.length, DWC3_TRBCTL_CONTROL_DATA, |
|
false); |
|
|
|
req->trb = &dwc->ep0_trb[dep->trb_enqueue]; |
|
|
|
ret = dwc3_ep0_start_trans(dep); |
|
} |
|
|
|
WARN_ON(ret < 0); |
|
} |
|
|
|
static int dwc3_ep0_start_control_status(struct dwc3_ep *dep) |
|
{ |
|
struct dwc3 *dwc = dep->dwc; |
|
u32 type; |
|
|
|
type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3 |
|
: DWC3_TRBCTL_CONTROL_STATUS2; |
|
|
|
dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false); |
|
return dwc3_ep0_start_trans(dep); |
|
} |
|
|
|
static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep) |
|
{ |
|
WARN_ON(dwc3_ep0_start_control_status(dep)); |
|
} |
|
|
|
static void dwc3_ep0_do_control_status(struct dwc3 *dwc, |
|
const struct dwc3_event_depevt *event) |
|
{ |
|
struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; |
|
|
|
__dwc3_ep0_do_control_status(dwc, dep); |
|
} |
|
|
|
void dwc3_ep0_send_delayed_status(struct dwc3 *dwc) |
|
{ |
|
unsigned int direction = !dwc->ep0_expect_in; |
|
|
|
dwc->delayed_status = false; |
|
|
|
if (dwc->ep0state != EP0_STATUS_PHASE) |
|
return; |
|
|
|
__dwc3_ep0_do_control_status(dwc, dwc->eps[direction]); |
|
} |
|
|
|
static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep) |
|
{ |
|
struct dwc3_gadget_ep_cmd_params params; |
|
u32 cmd; |
|
int ret; |
|
|
|
if (!dep->resource_index) |
|
return; |
|
|
|
cmd = DWC3_DEPCMD_ENDTRANSFER; |
|
cmd |= DWC3_DEPCMD_CMDIOC; |
|
cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); |
|
memset(¶ms, 0, sizeof(params)); |
|
ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); |
|
WARN_ON_ONCE(ret); |
|
dep->resource_index = 0; |
|
} |
|
|
|
static void dwc3_ep0_xfernotready(struct dwc3 *dwc, |
|
const struct dwc3_event_depevt *event) |
|
{ |
|
switch (event->status) { |
|
case DEPEVT_STATUS_CONTROL_DATA: |
|
/* |
|
* We already have a DATA transfer in the controller's cache, |
|
* if we receive a XferNotReady(DATA) we will ignore it, unless |
|
* it's for the wrong direction. |
|
* |
|
* In that case, we must issue END_TRANSFER command to the Data |
|
* Phase we already have started and issue SetStall on the |
|
* control endpoint. |
|
*/ |
|
if (dwc->ep0_expect_in != event->endpoint_number) { |
|
struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in]; |
|
|
|
dev_err(dwc->dev, "unexpected direction for Data Phase\n"); |
|
dwc3_ep0_end_control_data(dwc, dep); |
|
dwc3_ep0_stall_and_restart(dwc); |
|
return; |
|
} |
|
|
|
break; |
|
|
|
case DEPEVT_STATUS_CONTROL_STATUS: |
|
if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) |
|
return; |
|
|
|
dwc->ep0state = EP0_STATUS_PHASE; |
|
|
|
if (dwc->delayed_status) { |
|
struct dwc3_ep *dep = dwc->eps[0]; |
|
|
|
WARN_ON_ONCE(event->endpoint_number != 1); |
|
/* |
|
* We should handle the delay STATUS phase here if the |
|
* request for handling delay STATUS has been queued |
|
* into the list. |
|
*/ |
|
if (!list_empty(&dep->pending_list)) { |
|
dwc->delayed_status = false; |
|
usb_gadget_set_state(dwc->gadget, |
|
USB_STATE_CONFIGURED); |
|
dwc3_ep0_do_control_status(dwc, event); |
|
} |
|
|
|
return; |
|
} |
|
|
|
dwc3_ep0_do_control_status(dwc, event); |
|
} |
|
} |
|
|
|
void dwc3_ep0_interrupt(struct dwc3 *dwc, |
|
const struct dwc3_event_depevt *event) |
|
{ |
|
struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; |
|
u8 cmd; |
|
|
|
switch (event->endpoint_event) { |
|
case DWC3_DEPEVT_XFERCOMPLETE: |
|
dwc3_ep0_xfer_complete(dwc, event); |
|
break; |
|
|
|
case DWC3_DEPEVT_XFERNOTREADY: |
|
dwc3_ep0_xfernotready(dwc, event); |
|
break; |
|
|
|
case DWC3_DEPEVT_XFERINPROGRESS: |
|
case DWC3_DEPEVT_RXTXFIFOEVT: |
|
case DWC3_DEPEVT_STREAMEVT: |
|
break; |
|
case DWC3_DEPEVT_EPCMDCMPLT: |
|
cmd = DEPEVT_PARAMETER_CMD(event->parameters); |
|
|
|
if (cmd == DWC3_DEPCMD_ENDTRANSFER) { |
|
dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING; |
|
dep->flags &= ~DWC3_EP_TRANSFER_STARTED; |
|
} |
|
break; |
|
} |
|
}
|
|
|