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971 lines
23 KiB
971 lines
23 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* Copyright (c) 2018, The Linux Foundation. All rights reserved. |
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* |
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* Inspired by dwc3-of-simple.c |
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*/ |
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#include <linux/acpi.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/clk.h> |
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#include <linux/irq.h> |
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#include <linux/of_clk.h> |
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/extcon.h> |
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#include <linux/interconnect.h> |
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#include <linux/of_platform.h> |
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#include <linux/platform_device.h> |
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#include <linux/phy/phy.h> |
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#include <linux/usb/of.h> |
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#include <linux/reset.h> |
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#include <linux/iopoll.h> |
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#include "core.h" |
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/* USB QSCRATCH Hardware registers */ |
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#define QSCRATCH_HS_PHY_CTRL 0x10 |
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#define UTMI_OTG_VBUS_VALID BIT(20) |
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#define SW_SESSVLD_SEL BIT(28) |
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#define QSCRATCH_SS_PHY_CTRL 0x30 |
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#define LANE0_PWR_PRESENT BIT(24) |
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#define QSCRATCH_GENERAL_CFG 0x08 |
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#define PIPE_UTMI_CLK_SEL BIT(0) |
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#define PIPE3_PHYSTATUS_SW BIT(3) |
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#define PIPE_UTMI_CLK_DIS BIT(8) |
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#define PWR_EVNT_IRQ_STAT_REG 0x58 |
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#define PWR_EVNT_LPM_IN_L2_MASK BIT(4) |
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#define PWR_EVNT_LPM_OUT_L2_MASK BIT(5) |
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#define SDM845_QSCRATCH_BASE_OFFSET 0xf8800 |
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#define SDM845_QSCRATCH_SIZE 0x400 |
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#define SDM845_DWC3_CORE_SIZE 0xcd00 |
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/* Interconnect path bandwidths in MBps */ |
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#define USB_MEMORY_AVG_HS_BW MBps_to_icc(240) |
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#define USB_MEMORY_PEAK_HS_BW MBps_to_icc(700) |
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#define USB_MEMORY_AVG_SS_BW MBps_to_icc(1000) |
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#define USB_MEMORY_PEAK_SS_BW MBps_to_icc(2500) |
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#define APPS_USB_AVG_BW 0 |
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#define APPS_USB_PEAK_BW MBps_to_icc(40) |
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struct dwc3_acpi_pdata { |
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u32 qscratch_base_offset; |
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u32 qscratch_base_size; |
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u32 dwc3_core_base_size; |
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int hs_phy_irq_index; |
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int dp_hs_phy_irq_index; |
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int dm_hs_phy_irq_index; |
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int ss_phy_irq_index; |
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bool is_urs; |
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}; |
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struct dwc3_qcom { |
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struct device *dev; |
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void __iomem *qscratch_base; |
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struct platform_device *dwc3; |
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struct platform_device *urs_usb; |
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struct clk **clks; |
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int num_clocks; |
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struct reset_control *resets; |
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int hs_phy_irq; |
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int dp_hs_phy_irq; |
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int dm_hs_phy_irq; |
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int ss_phy_irq; |
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struct extcon_dev *edev; |
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struct extcon_dev *host_edev; |
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struct notifier_block vbus_nb; |
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struct notifier_block host_nb; |
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const struct dwc3_acpi_pdata *acpi_pdata; |
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enum usb_dr_mode mode; |
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bool is_suspended; |
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bool pm_suspended; |
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struct icc_path *icc_path_ddr; |
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struct icc_path *icc_path_apps; |
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}; |
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static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val) |
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{ |
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u32 reg; |
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reg = readl(base + offset); |
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reg |= val; |
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writel(reg, base + offset); |
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/* ensure that above write is through */ |
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readl(base + offset); |
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} |
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static inline void dwc3_qcom_clrbits(void __iomem *base, u32 offset, u32 val) |
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{ |
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u32 reg; |
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reg = readl(base + offset); |
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reg &= ~val; |
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writel(reg, base + offset); |
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/* ensure that above write is through */ |
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readl(base + offset); |
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} |
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static void dwc3_qcom_vbus_overrride_enable(struct dwc3_qcom *qcom, bool enable) |
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{ |
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if (enable) { |
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dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL, |
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LANE0_PWR_PRESENT); |
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dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL, |
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UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL); |
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} else { |
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dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL, |
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LANE0_PWR_PRESENT); |
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dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL, |
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UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL); |
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} |
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} |
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static int dwc3_qcom_vbus_notifier(struct notifier_block *nb, |
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unsigned long event, void *ptr) |
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{ |
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struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, vbus_nb); |
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/* enable vbus override for device mode */ |
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dwc3_qcom_vbus_overrride_enable(qcom, event); |
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qcom->mode = event ? USB_DR_MODE_PERIPHERAL : USB_DR_MODE_HOST; |
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return NOTIFY_DONE; |
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} |
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static int dwc3_qcom_host_notifier(struct notifier_block *nb, |
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unsigned long event, void *ptr) |
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{ |
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struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, host_nb); |
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/* disable vbus override in host mode */ |
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dwc3_qcom_vbus_overrride_enable(qcom, !event); |
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qcom->mode = event ? USB_DR_MODE_HOST : USB_DR_MODE_PERIPHERAL; |
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return NOTIFY_DONE; |
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} |
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static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom) |
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{ |
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struct device *dev = qcom->dev; |
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struct extcon_dev *host_edev; |
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int ret; |
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if (!of_property_read_bool(dev->of_node, "extcon")) |
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return 0; |
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qcom->edev = extcon_get_edev_by_phandle(dev, 0); |
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if (IS_ERR(qcom->edev)) |
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return PTR_ERR(qcom->edev); |
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qcom->vbus_nb.notifier_call = dwc3_qcom_vbus_notifier; |
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qcom->host_edev = extcon_get_edev_by_phandle(dev, 1); |
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if (IS_ERR(qcom->host_edev)) |
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qcom->host_edev = NULL; |
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ret = devm_extcon_register_notifier(dev, qcom->edev, EXTCON_USB, |
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&qcom->vbus_nb); |
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if (ret < 0) { |
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dev_err(dev, "VBUS notifier register failed\n"); |
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return ret; |
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} |
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if (qcom->host_edev) |
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host_edev = qcom->host_edev; |
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else |
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host_edev = qcom->edev; |
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qcom->host_nb.notifier_call = dwc3_qcom_host_notifier; |
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ret = devm_extcon_register_notifier(dev, host_edev, EXTCON_USB_HOST, |
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&qcom->host_nb); |
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if (ret < 0) { |
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dev_err(dev, "Host notifier register failed\n"); |
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return ret; |
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} |
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/* Update initial VBUS override based on extcon state */ |
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if (extcon_get_state(qcom->edev, EXTCON_USB) || |
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!extcon_get_state(host_edev, EXTCON_USB_HOST)) |
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dwc3_qcom_vbus_notifier(&qcom->vbus_nb, true, qcom->edev); |
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else |
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dwc3_qcom_vbus_notifier(&qcom->vbus_nb, false, qcom->edev); |
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return 0; |
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} |
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static int dwc3_qcom_interconnect_enable(struct dwc3_qcom *qcom) |
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{ |
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int ret; |
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ret = icc_enable(qcom->icc_path_ddr); |
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if (ret) |
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return ret; |
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ret = icc_enable(qcom->icc_path_apps); |
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if (ret) |
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icc_disable(qcom->icc_path_ddr); |
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return ret; |
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} |
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static int dwc3_qcom_interconnect_disable(struct dwc3_qcom *qcom) |
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{ |
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int ret; |
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ret = icc_disable(qcom->icc_path_ddr); |
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if (ret) |
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return ret; |
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ret = icc_disable(qcom->icc_path_apps); |
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if (ret) |
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icc_enable(qcom->icc_path_ddr); |
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return ret; |
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} |
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/** |
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* dwc3_qcom_interconnect_init() - Get interconnect path handles |
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* and set bandwidhth. |
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* @qcom: Pointer to the concerned usb core. |
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* |
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*/ |
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static int dwc3_qcom_interconnect_init(struct dwc3_qcom *qcom) |
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{ |
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struct device *dev = qcom->dev; |
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int ret; |
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if (has_acpi_companion(dev)) |
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return 0; |
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qcom->icc_path_ddr = of_icc_get(dev, "usb-ddr"); |
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if (IS_ERR(qcom->icc_path_ddr)) { |
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dev_err(dev, "failed to get usb-ddr path: %ld\n", |
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PTR_ERR(qcom->icc_path_ddr)); |
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return PTR_ERR(qcom->icc_path_ddr); |
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} |
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qcom->icc_path_apps = of_icc_get(dev, "apps-usb"); |
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if (IS_ERR(qcom->icc_path_apps)) { |
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dev_err(dev, "failed to get apps-usb path: %ld\n", |
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PTR_ERR(qcom->icc_path_apps)); |
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return PTR_ERR(qcom->icc_path_apps); |
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} |
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if (usb_get_maximum_speed(&qcom->dwc3->dev) >= USB_SPEED_SUPER || |
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usb_get_maximum_speed(&qcom->dwc3->dev) == USB_SPEED_UNKNOWN) |
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ret = icc_set_bw(qcom->icc_path_ddr, |
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USB_MEMORY_AVG_SS_BW, USB_MEMORY_PEAK_SS_BW); |
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else |
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ret = icc_set_bw(qcom->icc_path_ddr, |
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USB_MEMORY_AVG_HS_BW, USB_MEMORY_PEAK_HS_BW); |
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if (ret) { |
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dev_err(dev, "failed to set bandwidth for usb-ddr path: %d\n", ret); |
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return ret; |
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} |
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ret = icc_set_bw(qcom->icc_path_apps, |
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APPS_USB_AVG_BW, APPS_USB_PEAK_BW); |
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if (ret) { |
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dev_err(dev, "failed to set bandwidth for apps-usb path: %d\n", ret); |
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return ret; |
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} |
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return 0; |
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} |
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/** |
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* dwc3_qcom_interconnect_exit() - Release interconnect path handles |
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* @qcom: Pointer to the concerned usb core. |
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* |
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* This function is used to release interconnect path handle. |
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*/ |
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static void dwc3_qcom_interconnect_exit(struct dwc3_qcom *qcom) |
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{ |
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icc_put(qcom->icc_path_ddr); |
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icc_put(qcom->icc_path_apps); |
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} |
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static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom) |
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{ |
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if (qcom->hs_phy_irq) { |
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disable_irq_wake(qcom->hs_phy_irq); |
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disable_irq_nosync(qcom->hs_phy_irq); |
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} |
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if (qcom->dp_hs_phy_irq) { |
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disable_irq_wake(qcom->dp_hs_phy_irq); |
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disable_irq_nosync(qcom->dp_hs_phy_irq); |
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} |
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if (qcom->dm_hs_phy_irq) { |
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disable_irq_wake(qcom->dm_hs_phy_irq); |
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disable_irq_nosync(qcom->dm_hs_phy_irq); |
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} |
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if (qcom->ss_phy_irq) { |
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disable_irq_wake(qcom->ss_phy_irq); |
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disable_irq_nosync(qcom->ss_phy_irq); |
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} |
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} |
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static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom) |
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{ |
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if (qcom->hs_phy_irq) { |
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enable_irq(qcom->hs_phy_irq); |
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enable_irq_wake(qcom->hs_phy_irq); |
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} |
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if (qcom->dp_hs_phy_irq) { |
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enable_irq(qcom->dp_hs_phy_irq); |
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enable_irq_wake(qcom->dp_hs_phy_irq); |
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} |
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if (qcom->dm_hs_phy_irq) { |
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enable_irq(qcom->dm_hs_phy_irq); |
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enable_irq_wake(qcom->dm_hs_phy_irq); |
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} |
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if (qcom->ss_phy_irq) { |
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enable_irq(qcom->ss_phy_irq); |
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enable_irq_wake(qcom->ss_phy_irq); |
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} |
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} |
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static int dwc3_qcom_suspend(struct dwc3_qcom *qcom) |
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{ |
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u32 val; |
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int i, ret; |
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if (qcom->is_suspended) |
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return 0; |
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val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG); |
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if (!(val & PWR_EVNT_LPM_IN_L2_MASK)) |
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dev_err(qcom->dev, "HS-PHY not in L2\n"); |
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for (i = qcom->num_clocks - 1; i >= 0; i--) |
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clk_disable_unprepare(qcom->clks[i]); |
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ret = dwc3_qcom_interconnect_disable(qcom); |
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if (ret) |
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dev_warn(qcom->dev, "failed to disable interconnect: %d\n", ret); |
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if (device_may_wakeup(qcom->dev)) |
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dwc3_qcom_enable_interrupts(qcom); |
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qcom->is_suspended = true; |
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return 0; |
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} |
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static int dwc3_qcom_resume(struct dwc3_qcom *qcom) |
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{ |
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int ret; |
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int i; |
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if (!qcom->is_suspended) |
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return 0; |
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if (device_may_wakeup(qcom->dev)) |
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dwc3_qcom_disable_interrupts(qcom); |
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for (i = 0; i < qcom->num_clocks; i++) { |
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ret = clk_prepare_enable(qcom->clks[i]); |
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if (ret < 0) { |
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while (--i >= 0) |
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clk_disable_unprepare(qcom->clks[i]); |
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return ret; |
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} |
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} |
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ret = dwc3_qcom_interconnect_enable(qcom); |
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if (ret) |
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dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret); |
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/* Clear existing events from PHY related to L2 in/out */ |
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dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG, |
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PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK); |
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qcom->is_suspended = false; |
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return 0; |
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} |
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static irqreturn_t qcom_dwc3_resume_irq(int irq, void *data) |
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{ |
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struct dwc3_qcom *qcom = data; |
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struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); |
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/* If pm_suspended then let pm_resume take care of resuming h/w */ |
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if (qcom->pm_suspended) |
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return IRQ_HANDLED; |
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if (dwc->xhci) |
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pm_runtime_resume(&dwc->xhci->dev); |
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return IRQ_HANDLED; |
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} |
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static void dwc3_qcom_select_utmi_clk(struct dwc3_qcom *qcom) |
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{ |
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/* Configure dwc3 to use UTMI clock as PIPE clock not present */ |
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dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG, |
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PIPE_UTMI_CLK_DIS); |
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usleep_range(100, 1000); |
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dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG, |
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PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW); |
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usleep_range(100, 1000); |
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dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG, |
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PIPE_UTMI_CLK_DIS); |
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} |
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static int dwc3_qcom_get_irq(struct platform_device *pdev, |
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const char *name, int num) |
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{ |
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struct dwc3_qcom *qcom = platform_get_drvdata(pdev); |
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struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb : pdev; |
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struct device_node *np = pdev->dev.of_node; |
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int ret; |
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if (np) |
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ret = platform_get_irq_byname(pdev_irq, name); |
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else |
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ret = platform_get_irq(pdev_irq, num); |
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return ret; |
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} |
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static int dwc3_qcom_setup_irq(struct platform_device *pdev) |
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{ |
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struct dwc3_qcom *qcom = platform_get_drvdata(pdev); |
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const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata; |
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int irq; |
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int ret; |
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irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq", |
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pdata ? pdata->hs_phy_irq_index : -1); |
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if (irq > 0) { |
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/* Keep wakeup interrupts disabled until suspend */ |
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irq_set_status_flags(irq, IRQ_NOAUTOEN); |
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ret = devm_request_threaded_irq(qcom->dev, irq, NULL, |
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qcom_dwc3_resume_irq, |
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IRQF_TRIGGER_HIGH | IRQF_ONESHOT, |
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"qcom_dwc3 HS", qcom); |
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if (ret) { |
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dev_err(qcom->dev, "hs_phy_irq failed: %d\n", ret); |
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return ret; |
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} |
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qcom->hs_phy_irq = irq; |
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} |
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irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq", |
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pdata ? pdata->dp_hs_phy_irq_index : -1); |
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if (irq > 0) { |
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irq_set_status_flags(irq, IRQ_NOAUTOEN); |
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ret = devm_request_threaded_irq(qcom->dev, irq, NULL, |
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qcom_dwc3_resume_irq, |
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IRQF_TRIGGER_HIGH | IRQF_ONESHOT, |
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"qcom_dwc3 DP_HS", qcom); |
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if (ret) { |
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dev_err(qcom->dev, "dp_hs_phy_irq failed: %d\n", ret); |
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return ret; |
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} |
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qcom->dp_hs_phy_irq = irq; |
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} |
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irq = dwc3_qcom_get_irq(pdev, "dm_hs_phy_irq", |
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pdata ? pdata->dm_hs_phy_irq_index : -1); |
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if (irq > 0) { |
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irq_set_status_flags(irq, IRQ_NOAUTOEN); |
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ret = devm_request_threaded_irq(qcom->dev, irq, NULL, |
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qcom_dwc3_resume_irq, |
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IRQF_TRIGGER_HIGH | IRQF_ONESHOT, |
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"qcom_dwc3 DM_HS", qcom); |
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if (ret) { |
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dev_err(qcom->dev, "dm_hs_phy_irq failed: %d\n", ret); |
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return ret; |
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} |
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qcom->dm_hs_phy_irq = irq; |
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} |
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irq = dwc3_qcom_get_irq(pdev, "ss_phy_irq", |
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pdata ? pdata->ss_phy_irq_index : -1); |
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if (irq > 0) { |
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irq_set_status_flags(irq, IRQ_NOAUTOEN); |
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ret = devm_request_threaded_irq(qcom->dev, irq, NULL, |
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qcom_dwc3_resume_irq, |
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IRQF_TRIGGER_HIGH | IRQF_ONESHOT, |
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"qcom_dwc3 SS", qcom); |
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if (ret) { |
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dev_err(qcom->dev, "ss_phy_irq failed: %d\n", ret); |
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return ret; |
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} |
|
qcom->ss_phy_irq = irq; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int dwc3_qcom_clk_init(struct dwc3_qcom *qcom, int count) |
|
{ |
|
struct device *dev = qcom->dev; |
|
struct device_node *np = dev->of_node; |
|
int i; |
|
|
|
if (!np || !count) |
|
return 0; |
|
|
|
if (count < 0) |
|
return count; |
|
|
|
qcom->num_clocks = count; |
|
|
|
qcom->clks = devm_kcalloc(dev, qcom->num_clocks, |
|
sizeof(struct clk *), GFP_KERNEL); |
|
if (!qcom->clks) |
|
return -ENOMEM; |
|
|
|
for (i = 0; i < qcom->num_clocks; i++) { |
|
struct clk *clk; |
|
int ret; |
|
|
|
clk = of_clk_get(np, i); |
|
if (IS_ERR(clk)) { |
|
while (--i >= 0) |
|
clk_put(qcom->clks[i]); |
|
return PTR_ERR(clk); |
|
} |
|
|
|
ret = clk_prepare_enable(clk); |
|
if (ret < 0) { |
|
while (--i >= 0) { |
|
clk_disable_unprepare(qcom->clks[i]); |
|
clk_put(qcom->clks[i]); |
|
} |
|
clk_put(clk); |
|
|
|
return ret; |
|
} |
|
|
|
qcom->clks[i] = clk; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static const struct property_entry dwc3_qcom_acpi_properties[] = { |
|
PROPERTY_ENTRY_STRING("dr_mode", "host"), |
|
{} |
|
}; |
|
|
|
static const struct software_node dwc3_qcom_swnode = { |
|
.properties = dwc3_qcom_acpi_properties, |
|
}; |
|
|
|
static int dwc3_qcom_acpi_register_core(struct platform_device *pdev) |
|
{ |
|
struct dwc3_qcom *qcom = platform_get_drvdata(pdev); |
|
struct device *dev = &pdev->dev; |
|
struct resource *res, *child_res = NULL; |
|
struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb : |
|
pdev; |
|
int irq; |
|
int ret; |
|
|
|
qcom->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); |
|
if (!qcom->dwc3) |
|
return -ENOMEM; |
|
|
|
qcom->dwc3->dev.parent = dev; |
|
qcom->dwc3->dev.type = dev->type; |
|
qcom->dwc3->dev.dma_mask = dev->dma_mask; |
|
qcom->dwc3->dev.dma_parms = dev->dma_parms; |
|
qcom->dwc3->dev.coherent_dma_mask = dev->coherent_dma_mask; |
|
|
|
child_res = kcalloc(2, sizeof(*child_res), GFP_KERNEL); |
|
if (!child_res) |
|
return -ENOMEM; |
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
if (!res) { |
|
dev_err(&pdev->dev, "failed to get memory resource\n"); |
|
ret = -ENODEV; |
|
goto out; |
|
} |
|
|
|
child_res[0].flags = res->flags; |
|
child_res[0].start = res->start; |
|
child_res[0].end = child_res[0].start + |
|
qcom->acpi_pdata->dwc3_core_base_size; |
|
|
|
irq = platform_get_irq(pdev_irq, 0); |
|
child_res[1].flags = IORESOURCE_IRQ; |
|
child_res[1].start = child_res[1].end = irq; |
|
|
|
ret = platform_device_add_resources(qcom->dwc3, child_res, 2); |
|
if (ret) { |
|
dev_err(&pdev->dev, "failed to add resources\n"); |
|
goto out; |
|
} |
|
|
|
ret = device_add_software_node(&qcom->dwc3->dev, &dwc3_qcom_swnode); |
|
if (ret < 0) { |
|
dev_err(&pdev->dev, "failed to add properties\n"); |
|
goto out; |
|
} |
|
|
|
ret = platform_device_add(qcom->dwc3); |
|
if (ret) { |
|
dev_err(&pdev->dev, "failed to add device\n"); |
|
device_remove_software_node(&qcom->dwc3->dev); |
|
} |
|
|
|
out: |
|
kfree(child_res); |
|
return ret; |
|
} |
|
|
|
static int dwc3_qcom_of_register_core(struct platform_device *pdev) |
|
{ |
|
struct dwc3_qcom *qcom = platform_get_drvdata(pdev); |
|
struct device_node *np = pdev->dev.of_node, *dwc3_np; |
|
struct device *dev = &pdev->dev; |
|
int ret; |
|
|
|
dwc3_np = of_get_child_by_name(np, "dwc3"); |
|
if (!dwc3_np) { |
|
dev_err(dev, "failed to find dwc3 core child\n"); |
|
return -ENODEV; |
|
} |
|
|
|
ret = of_platform_populate(np, NULL, NULL, dev); |
|
if (ret) { |
|
dev_err(dev, "failed to register dwc3 core - %d\n", ret); |
|
goto node_put; |
|
} |
|
|
|
qcom->dwc3 = of_find_device_by_node(dwc3_np); |
|
if (!qcom->dwc3) { |
|
ret = -ENODEV; |
|
dev_err(dev, "failed to get dwc3 platform device\n"); |
|
} |
|
|
|
node_put: |
|
of_node_put(dwc3_np); |
|
|
|
return ret; |
|
} |
|
|
|
static struct platform_device * |
|
dwc3_qcom_create_urs_usb_platdev(struct device *dev) |
|
{ |
|
struct fwnode_handle *fwh; |
|
struct acpi_device *adev; |
|
char name[8]; |
|
int ret; |
|
int id; |
|
|
|
/* Figure out device id */ |
|
ret = sscanf(fwnode_get_name(dev->fwnode), "URS%d", &id); |
|
if (!ret) |
|
return NULL; |
|
|
|
/* Find the child using name */ |
|
snprintf(name, sizeof(name), "USB%d", id); |
|
fwh = fwnode_get_named_child_node(dev->fwnode, name); |
|
if (!fwh) |
|
return NULL; |
|
|
|
adev = to_acpi_device_node(fwh); |
|
if (!adev) |
|
return NULL; |
|
|
|
return acpi_create_platform_device(adev, NULL); |
|
} |
|
|
|
static int dwc3_qcom_probe(struct platform_device *pdev) |
|
{ |
|
struct device_node *np = pdev->dev.of_node; |
|
struct device *dev = &pdev->dev; |
|
struct dwc3_qcom *qcom; |
|
struct resource *res, *parent_res = NULL; |
|
int ret, i; |
|
bool ignore_pipe_clk; |
|
|
|
qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL); |
|
if (!qcom) |
|
return -ENOMEM; |
|
|
|
platform_set_drvdata(pdev, qcom); |
|
qcom->dev = &pdev->dev; |
|
|
|
if (has_acpi_companion(dev)) { |
|
qcom->acpi_pdata = acpi_device_get_match_data(dev); |
|
if (!qcom->acpi_pdata) { |
|
dev_err(&pdev->dev, "no supporting ACPI device data\n"); |
|
return -EINVAL; |
|
} |
|
} |
|
|
|
qcom->resets = devm_reset_control_array_get_optional_exclusive(dev); |
|
if (IS_ERR(qcom->resets)) { |
|
ret = PTR_ERR(qcom->resets); |
|
dev_err(&pdev->dev, "failed to get resets, err=%d\n", ret); |
|
return ret; |
|
} |
|
|
|
ret = reset_control_assert(qcom->resets); |
|
if (ret) { |
|
dev_err(&pdev->dev, "failed to assert resets, err=%d\n", ret); |
|
return ret; |
|
} |
|
|
|
usleep_range(10, 1000); |
|
|
|
ret = reset_control_deassert(qcom->resets); |
|
if (ret) { |
|
dev_err(&pdev->dev, "failed to deassert resets, err=%d\n", ret); |
|
goto reset_assert; |
|
} |
|
|
|
ret = dwc3_qcom_clk_init(qcom, of_clk_get_parent_count(np)); |
|
if (ret) { |
|
dev_err(dev, "failed to get clocks\n"); |
|
goto reset_assert; |
|
} |
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
|
|
if (np) { |
|
parent_res = res; |
|
} else { |
|
parent_res = kmemdup(res, sizeof(struct resource), GFP_KERNEL); |
|
if (!parent_res) |
|
return -ENOMEM; |
|
|
|
parent_res->start = res->start + |
|
qcom->acpi_pdata->qscratch_base_offset; |
|
parent_res->end = parent_res->start + |
|
qcom->acpi_pdata->qscratch_base_size; |
|
|
|
if (qcom->acpi_pdata->is_urs) { |
|
qcom->urs_usb = dwc3_qcom_create_urs_usb_platdev(dev); |
|
if (!qcom->urs_usb) { |
|
dev_err(dev, "failed to create URS USB platdev\n"); |
|
return -ENODEV; |
|
} |
|
} |
|
} |
|
|
|
qcom->qscratch_base = devm_ioremap_resource(dev, parent_res); |
|
if (IS_ERR(qcom->qscratch_base)) { |
|
dev_err(dev, "failed to map qscratch, err=%d\n", ret); |
|
ret = PTR_ERR(qcom->qscratch_base); |
|
goto clk_disable; |
|
} |
|
|
|
ret = dwc3_qcom_setup_irq(pdev); |
|
if (ret) { |
|
dev_err(dev, "failed to setup IRQs, err=%d\n", ret); |
|
goto clk_disable; |
|
} |
|
|
|
/* |
|
* Disable pipe_clk requirement if specified. Used when dwc3 |
|
* operates without SSPHY and only HS/FS/LS modes are supported. |
|
*/ |
|
ignore_pipe_clk = device_property_read_bool(dev, |
|
"qcom,select-utmi-as-pipe-clk"); |
|
if (ignore_pipe_clk) |
|
dwc3_qcom_select_utmi_clk(qcom); |
|
|
|
if (np) |
|
ret = dwc3_qcom_of_register_core(pdev); |
|
else |
|
ret = dwc3_qcom_acpi_register_core(pdev); |
|
|
|
if (ret) { |
|
dev_err(dev, "failed to register DWC3 Core, err=%d\n", ret); |
|
goto depopulate; |
|
} |
|
|
|
ret = dwc3_qcom_interconnect_init(qcom); |
|
if (ret) |
|
goto depopulate; |
|
|
|
qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev); |
|
|
|
/* enable vbus override for device mode */ |
|
if (qcom->mode == USB_DR_MODE_PERIPHERAL) |
|
dwc3_qcom_vbus_overrride_enable(qcom, true); |
|
|
|
/* register extcon to override sw_vbus on Vbus change later */ |
|
ret = dwc3_qcom_register_extcon(qcom); |
|
if (ret) |
|
goto interconnect_exit; |
|
|
|
device_init_wakeup(&pdev->dev, 1); |
|
qcom->is_suspended = false; |
|
pm_runtime_set_active(dev); |
|
pm_runtime_enable(dev); |
|
pm_runtime_forbid(dev); |
|
|
|
return 0; |
|
|
|
interconnect_exit: |
|
dwc3_qcom_interconnect_exit(qcom); |
|
depopulate: |
|
if (np) |
|
of_platform_depopulate(&pdev->dev); |
|
else |
|
platform_device_put(pdev); |
|
clk_disable: |
|
for (i = qcom->num_clocks - 1; i >= 0; i--) { |
|
clk_disable_unprepare(qcom->clks[i]); |
|
clk_put(qcom->clks[i]); |
|
} |
|
reset_assert: |
|
reset_control_assert(qcom->resets); |
|
|
|
return ret; |
|
} |
|
|
|
static int dwc3_qcom_remove(struct platform_device *pdev) |
|
{ |
|
struct dwc3_qcom *qcom = platform_get_drvdata(pdev); |
|
struct device *dev = &pdev->dev; |
|
int i; |
|
|
|
device_remove_software_node(&qcom->dwc3->dev); |
|
of_platform_depopulate(dev); |
|
|
|
for (i = qcom->num_clocks - 1; i >= 0; i--) { |
|
clk_disable_unprepare(qcom->clks[i]); |
|
clk_put(qcom->clks[i]); |
|
} |
|
qcom->num_clocks = 0; |
|
|
|
dwc3_qcom_interconnect_exit(qcom); |
|
reset_control_assert(qcom->resets); |
|
|
|
pm_runtime_allow(dev); |
|
pm_runtime_disable(dev); |
|
|
|
return 0; |
|
} |
|
|
|
static int __maybe_unused dwc3_qcom_pm_suspend(struct device *dev) |
|
{ |
|
struct dwc3_qcom *qcom = dev_get_drvdata(dev); |
|
int ret = 0; |
|
|
|
ret = dwc3_qcom_suspend(qcom); |
|
if (!ret) |
|
qcom->pm_suspended = true; |
|
|
|
return ret; |
|
} |
|
|
|
static int __maybe_unused dwc3_qcom_pm_resume(struct device *dev) |
|
{ |
|
struct dwc3_qcom *qcom = dev_get_drvdata(dev); |
|
int ret; |
|
|
|
ret = dwc3_qcom_resume(qcom); |
|
if (!ret) |
|
qcom->pm_suspended = false; |
|
|
|
return ret; |
|
} |
|
|
|
static int __maybe_unused dwc3_qcom_runtime_suspend(struct device *dev) |
|
{ |
|
struct dwc3_qcom *qcom = dev_get_drvdata(dev); |
|
|
|
return dwc3_qcom_suspend(qcom); |
|
} |
|
|
|
static int __maybe_unused dwc3_qcom_runtime_resume(struct device *dev) |
|
{ |
|
struct dwc3_qcom *qcom = dev_get_drvdata(dev); |
|
|
|
return dwc3_qcom_resume(qcom); |
|
} |
|
|
|
static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = { |
|
SET_SYSTEM_SLEEP_PM_OPS(dwc3_qcom_pm_suspend, dwc3_qcom_pm_resume) |
|
SET_RUNTIME_PM_OPS(dwc3_qcom_runtime_suspend, dwc3_qcom_runtime_resume, |
|
NULL) |
|
}; |
|
|
|
static const struct of_device_id dwc3_qcom_of_match[] = { |
|
{ .compatible = "qcom,dwc3" }, |
|
{ .compatible = "qcom,msm8996-dwc3" }, |
|
{ .compatible = "qcom,msm8998-dwc3" }, |
|
{ .compatible = "qcom,sdm845-dwc3" }, |
|
{ } |
|
}; |
|
MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match); |
|
|
|
#ifdef CONFIG_ACPI |
|
static const struct dwc3_acpi_pdata sdm845_acpi_pdata = { |
|
.qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET, |
|
.qscratch_base_size = SDM845_QSCRATCH_SIZE, |
|
.dwc3_core_base_size = SDM845_DWC3_CORE_SIZE, |
|
.hs_phy_irq_index = 1, |
|
.dp_hs_phy_irq_index = 4, |
|
.dm_hs_phy_irq_index = 3, |
|
.ss_phy_irq_index = 2 |
|
}; |
|
|
|
static const struct dwc3_acpi_pdata sdm845_acpi_urs_pdata = { |
|
.qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET, |
|
.qscratch_base_size = SDM845_QSCRATCH_SIZE, |
|
.dwc3_core_base_size = SDM845_DWC3_CORE_SIZE, |
|
.hs_phy_irq_index = 1, |
|
.dp_hs_phy_irq_index = 4, |
|
.dm_hs_phy_irq_index = 3, |
|
.ss_phy_irq_index = 2, |
|
.is_urs = true, |
|
}; |
|
|
|
static const struct acpi_device_id dwc3_qcom_acpi_match[] = { |
|
{ "QCOM2430", (unsigned long)&sdm845_acpi_pdata }, |
|
{ "QCOM0304", (unsigned long)&sdm845_acpi_urs_pdata }, |
|
{ "QCOM0497", (unsigned long)&sdm845_acpi_urs_pdata }, |
|
{ "QCOM04A6", (unsigned long)&sdm845_acpi_pdata }, |
|
{ }, |
|
}; |
|
MODULE_DEVICE_TABLE(acpi, dwc3_qcom_acpi_match); |
|
#endif |
|
|
|
static struct platform_driver dwc3_qcom_driver = { |
|
.probe = dwc3_qcom_probe, |
|
.remove = dwc3_qcom_remove, |
|
.driver = { |
|
.name = "dwc3-qcom", |
|
.pm = &dwc3_qcom_dev_pm_ops, |
|
.of_match_table = dwc3_qcom_of_match, |
|
.acpi_match_table = ACPI_PTR(dwc3_qcom_acpi_match), |
|
}, |
|
}; |
|
|
|
module_platform_driver(dwc3_qcom_driver); |
|
|
|
MODULE_LICENSE("GPL v2"); |
|
MODULE_DESCRIPTION("DesignWare DWC3 QCOM Glue Driver");
|
|
|