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855 lines
20 KiB
855 lines
20 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Based on meson_uart.c, by AMLOGIC, INC. |
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* |
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* Copyright (C) 2014 Carlo Caione <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/console.h> |
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#include <linux/delay.h> |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/iopoll.h> |
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/serial.h> |
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#include <linux/serial_core.h> |
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#include <linux/tty.h> |
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#include <linux/tty_flip.h> |
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/* Register offsets */ |
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#define AML_UART_WFIFO 0x00 |
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#define AML_UART_RFIFO 0x04 |
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#define AML_UART_CONTROL 0x08 |
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#define AML_UART_STATUS 0x0c |
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#define AML_UART_MISC 0x10 |
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#define AML_UART_REG5 0x14 |
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/* AML_UART_CONTROL bits */ |
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#define AML_UART_TX_EN BIT(12) |
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#define AML_UART_RX_EN BIT(13) |
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#define AML_UART_TWO_WIRE_EN BIT(15) |
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#define AML_UART_STOP_BIT_LEN_MASK (0x03 << 16) |
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#define AML_UART_STOP_BIT_1SB (0x00 << 16) |
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#define AML_UART_STOP_BIT_2SB (0x01 << 16) |
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#define AML_UART_PARITY_TYPE BIT(18) |
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#define AML_UART_PARITY_EN BIT(19) |
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#define AML_UART_TX_RST BIT(22) |
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#define AML_UART_RX_RST BIT(23) |
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#define AML_UART_CLEAR_ERR BIT(24) |
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#define AML_UART_RX_INT_EN BIT(27) |
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#define AML_UART_TX_INT_EN BIT(28) |
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#define AML_UART_DATA_LEN_MASK (0x03 << 20) |
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#define AML_UART_DATA_LEN_8BIT (0x00 << 20) |
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#define AML_UART_DATA_LEN_7BIT (0x01 << 20) |
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#define AML_UART_DATA_LEN_6BIT (0x02 << 20) |
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#define AML_UART_DATA_LEN_5BIT (0x03 << 20) |
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/* AML_UART_STATUS bits */ |
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#define AML_UART_PARITY_ERR BIT(16) |
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#define AML_UART_FRAME_ERR BIT(17) |
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#define AML_UART_TX_FIFO_WERR BIT(18) |
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#define AML_UART_RX_EMPTY BIT(20) |
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#define AML_UART_TX_FULL BIT(21) |
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#define AML_UART_TX_EMPTY BIT(22) |
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#define AML_UART_XMIT_BUSY BIT(25) |
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#define AML_UART_ERR (AML_UART_PARITY_ERR | \ |
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AML_UART_FRAME_ERR | \ |
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AML_UART_TX_FIFO_WERR) |
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/* AML_UART_MISC bits */ |
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#define AML_UART_XMIT_IRQ(c) (((c) & 0xff) << 8) |
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#define AML_UART_RECV_IRQ(c) ((c) & 0xff) |
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/* AML_UART_REG5 bits */ |
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#define AML_UART_BAUD_MASK 0x7fffff |
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#define AML_UART_BAUD_USE BIT(23) |
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#define AML_UART_BAUD_XTAL BIT(24) |
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#define AML_UART_PORT_NUM 12 |
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#define AML_UART_PORT_OFFSET 6 |
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#define AML_UART_DEV_NAME "ttyAML" |
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#define AML_UART_POLL_USEC 5 |
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#define AML_UART_TIMEOUT_USEC 10000 |
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static struct uart_driver meson_uart_driver; |
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static struct uart_port *meson_ports[AML_UART_PORT_NUM]; |
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static void meson_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
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{ |
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} |
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static unsigned int meson_uart_get_mctrl(struct uart_port *port) |
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{ |
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return TIOCM_CTS; |
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} |
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static unsigned int meson_uart_tx_empty(struct uart_port *port) |
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{ |
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u32 val; |
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val = readl(port->membase + AML_UART_STATUS); |
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val &= (AML_UART_TX_EMPTY | AML_UART_XMIT_BUSY); |
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return (val == AML_UART_TX_EMPTY) ? TIOCSER_TEMT : 0; |
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} |
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static void meson_uart_stop_tx(struct uart_port *port) |
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{ |
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u32 val; |
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val = readl(port->membase + AML_UART_CONTROL); |
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val &= ~AML_UART_TX_INT_EN; |
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writel(val, port->membase + AML_UART_CONTROL); |
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} |
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static void meson_uart_stop_rx(struct uart_port *port) |
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{ |
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u32 val; |
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val = readl(port->membase + AML_UART_CONTROL); |
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val &= ~AML_UART_RX_EN; |
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writel(val, port->membase + AML_UART_CONTROL); |
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} |
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static void meson_uart_shutdown(struct uart_port *port) |
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{ |
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unsigned long flags; |
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u32 val; |
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free_irq(port->irq, port); |
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spin_lock_irqsave(&port->lock, flags); |
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val = readl(port->membase + AML_UART_CONTROL); |
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val &= ~AML_UART_RX_EN; |
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val &= ~(AML_UART_RX_INT_EN | AML_UART_TX_INT_EN); |
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writel(val, port->membase + AML_UART_CONTROL); |
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spin_unlock_irqrestore(&port->lock, flags); |
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} |
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static void meson_uart_start_tx(struct uart_port *port) |
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{ |
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struct circ_buf *xmit = &port->state->xmit; |
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unsigned int ch; |
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u32 val; |
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if (uart_tx_stopped(port)) { |
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meson_uart_stop_tx(port); |
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return; |
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} |
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while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) { |
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if (port->x_char) { |
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writel(port->x_char, port->membase + AML_UART_WFIFO); |
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port->icount.tx++; |
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port->x_char = 0; |
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continue; |
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} |
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if (uart_circ_empty(xmit)) |
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break; |
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ch = xmit->buf[xmit->tail]; |
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writel(ch, port->membase + AML_UART_WFIFO); |
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xmit->tail = (xmit->tail+1) & (SERIAL_XMIT_SIZE - 1); |
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port->icount.tx++; |
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} |
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if (!uart_circ_empty(xmit)) { |
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val = readl(port->membase + AML_UART_CONTROL); |
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val |= AML_UART_TX_INT_EN; |
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writel(val, port->membase + AML_UART_CONTROL); |
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} |
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
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uart_write_wakeup(port); |
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} |
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static void meson_receive_chars(struct uart_port *port) |
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{ |
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struct tty_port *tport = &port->state->port; |
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char flag; |
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u32 ostatus, status, ch, mode; |
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do { |
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flag = TTY_NORMAL; |
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port->icount.rx++; |
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ostatus = status = readl(port->membase + AML_UART_STATUS); |
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if (status & AML_UART_ERR) { |
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if (status & AML_UART_TX_FIFO_WERR) |
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port->icount.overrun++; |
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else if (status & AML_UART_FRAME_ERR) |
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port->icount.frame++; |
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else if (status & AML_UART_PARITY_ERR) |
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port->icount.frame++; |
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mode = readl(port->membase + AML_UART_CONTROL); |
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mode |= AML_UART_CLEAR_ERR; |
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writel(mode, port->membase + AML_UART_CONTROL); |
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/* It doesn't clear to 0 automatically */ |
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mode &= ~AML_UART_CLEAR_ERR; |
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writel(mode, port->membase + AML_UART_CONTROL); |
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status &= port->read_status_mask; |
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if (status & AML_UART_FRAME_ERR) |
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flag = TTY_FRAME; |
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else if (status & AML_UART_PARITY_ERR) |
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flag = TTY_PARITY; |
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} |
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ch = readl(port->membase + AML_UART_RFIFO); |
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ch &= 0xff; |
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if ((ostatus & AML_UART_FRAME_ERR) && (ch == 0)) { |
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port->icount.brk++; |
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flag = TTY_BREAK; |
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if (uart_handle_break(port)) |
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continue; |
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} |
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if (uart_handle_sysrq_char(port, ch)) |
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continue; |
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if ((status & port->ignore_status_mask) == 0) |
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tty_insert_flip_char(tport, ch, flag); |
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if (status & AML_UART_TX_FIFO_WERR) |
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tty_insert_flip_char(tport, 0, TTY_OVERRUN); |
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} while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY)); |
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spin_unlock(&port->lock); |
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tty_flip_buffer_push(tport); |
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spin_lock(&port->lock); |
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} |
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static irqreturn_t meson_uart_interrupt(int irq, void *dev_id) |
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{ |
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struct uart_port *port = (struct uart_port *)dev_id; |
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spin_lock(&port->lock); |
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if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY)) |
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meson_receive_chars(port); |
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if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) { |
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if (readl(port->membase + AML_UART_CONTROL) & AML_UART_TX_INT_EN) |
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meson_uart_start_tx(port); |
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} |
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spin_unlock(&port->lock); |
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return IRQ_HANDLED; |
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} |
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static const char *meson_uart_type(struct uart_port *port) |
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{ |
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return (port->type == PORT_MESON) ? "meson_uart" : NULL; |
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} |
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static void meson_uart_reset(struct uart_port *port) |
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{ |
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u32 val; |
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val = readl(port->membase + AML_UART_CONTROL); |
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val |= (AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLEAR_ERR); |
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writel(val, port->membase + AML_UART_CONTROL); |
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val &= ~(AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLEAR_ERR); |
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writel(val, port->membase + AML_UART_CONTROL); |
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} |
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static int meson_uart_startup(struct uart_port *port) |
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{ |
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u32 val; |
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int ret = 0; |
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val = readl(port->membase + AML_UART_CONTROL); |
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val |= AML_UART_CLEAR_ERR; |
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writel(val, port->membase + AML_UART_CONTROL); |
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val &= ~AML_UART_CLEAR_ERR; |
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writel(val, port->membase + AML_UART_CONTROL); |
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val |= (AML_UART_RX_EN | AML_UART_TX_EN); |
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writel(val, port->membase + AML_UART_CONTROL); |
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val |= (AML_UART_RX_INT_EN | AML_UART_TX_INT_EN); |
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writel(val, port->membase + AML_UART_CONTROL); |
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val = (AML_UART_RECV_IRQ(1) | AML_UART_XMIT_IRQ(port->fifosize / 2)); |
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writel(val, port->membase + AML_UART_MISC); |
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ret = request_irq(port->irq, meson_uart_interrupt, 0, |
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port->name, port); |
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return ret; |
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} |
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static void meson_uart_change_speed(struct uart_port *port, unsigned long baud) |
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{ |
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u32 val; |
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while (!meson_uart_tx_empty(port)) |
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cpu_relax(); |
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if (port->uartclk == 24000000) { |
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val = ((port->uartclk / 3) / baud) - 1; |
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val |= AML_UART_BAUD_XTAL; |
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} else { |
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val = ((port->uartclk * 10 / (baud * 4) + 5) / 10) - 1; |
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} |
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val |= AML_UART_BAUD_USE; |
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writel(val, port->membase + AML_UART_REG5); |
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} |
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static void meson_uart_set_termios(struct uart_port *port, |
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struct ktermios *termios, |
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struct ktermios *old) |
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{ |
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unsigned int cflags, iflags, baud; |
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unsigned long flags; |
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u32 val; |
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spin_lock_irqsave(&port->lock, flags); |
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cflags = termios->c_cflag; |
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iflags = termios->c_iflag; |
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val = readl(port->membase + AML_UART_CONTROL); |
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val &= ~AML_UART_DATA_LEN_MASK; |
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switch (cflags & CSIZE) { |
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case CS8: |
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val |= AML_UART_DATA_LEN_8BIT; |
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break; |
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case CS7: |
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val |= AML_UART_DATA_LEN_7BIT; |
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break; |
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case CS6: |
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val |= AML_UART_DATA_LEN_6BIT; |
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break; |
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case CS5: |
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val |= AML_UART_DATA_LEN_5BIT; |
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break; |
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} |
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if (cflags & PARENB) |
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val |= AML_UART_PARITY_EN; |
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else |
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val &= ~AML_UART_PARITY_EN; |
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if (cflags & PARODD) |
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val |= AML_UART_PARITY_TYPE; |
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else |
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val &= ~AML_UART_PARITY_TYPE; |
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val &= ~AML_UART_STOP_BIT_LEN_MASK; |
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if (cflags & CSTOPB) |
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val |= AML_UART_STOP_BIT_2SB; |
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else |
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val |= AML_UART_STOP_BIT_1SB; |
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if (cflags & CRTSCTS) |
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val &= ~AML_UART_TWO_WIRE_EN; |
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else |
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val |= AML_UART_TWO_WIRE_EN; |
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writel(val, port->membase + AML_UART_CONTROL); |
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baud = uart_get_baud_rate(port, termios, old, 50, 4000000); |
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meson_uart_change_speed(port, baud); |
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port->read_status_mask = AML_UART_TX_FIFO_WERR; |
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if (iflags & INPCK) |
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port->read_status_mask |= AML_UART_PARITY_ERR | |
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AML_UART_FRAME_ERR; |
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port->ignore_status_mask = 0; |
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if (iflags & IGNPAR) |
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port->ignore_status_mask |= AML_UART_PARITY_ERR | |
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AML_UART_FRAME_ERR; |
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uart_update_timeout(port, termios->c_cflag, baud); |
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spin_unlock_irqrestore(&port->lock, flags); |
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} |
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static int meson_uart_verify_port(struct uart_port *port, |
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struct serial_struct *ser) |
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{ |
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int ret = 0; |
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if (port->type != PORT_MESON) |
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ret = -EINVAL; |
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if (port->irq != ser->irq) |
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ret = -EINVAL; |
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if (ser->baud_base < 9600) |
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ret = -EINVAL; |
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return ret; |
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} |
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static void meson_uart_release_port(struct uart_port *port) |
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{ |
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devm_iounmap(port->dev, port->membase); |
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port->membase = NULL; |
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devm_release_mem_region(port->dev, port->mapbase, port->mapsize); |
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} |
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static int meson_uart_request_port(struct uart_port *port) |
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{ |
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if (!devm_request_mem_region(port->dev, port->mapbase, port->mapsize, |
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dev_name(port->dev))) { |
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dev_err(port->dev, "Memory region busy\n"); |
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return -EBUSY; |
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} |
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port->membase = devm_ioremap(port->dev, port->mapbase, |
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port->mapsize); |
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if (!port->membase) |
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return -ENOMEM; |
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return 0; |
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} |
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static void meson_uart_config_port(struct uart_port *port, int flags) |
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{ |
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if (flags & UART_CONFIG_TYPE) { |
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port->type = PORT_MESON; |
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meson_uart_request_port(port); |
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} |
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} |
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#ifdef CONFIG_CONSOLE_POLL |
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/* |
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* Console polling routines for writing and reading from the uart while |
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* in an interrupt or debug context (i.e. kgdb). |
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*/ |
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static int meson_uart_poll_get_char(struct uart_port *port) |
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{ |
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u32 c; |
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unsigned long flags; |
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spin_lock_irqsave(&port->lock, flags); |
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if (readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY) |
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c = NO_POLL_CHAR; |
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else |
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c = readl(port->membase + AML_UART_RFIFO); |
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spin_unlock_irqrestore(&port->lock, flags); |
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return c; |
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} |
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static void meson_uart_poll_put_char(struct uart_port *port, unsigned char c) |
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{ |
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unsigned long flags; |
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u32 reg; |
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int ret; |
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spin_lock_irqsave(&port->lock, flags); |
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/* Wait until FIFO is empty or timeout */ |
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ret = readl_poll_timeout_atomic(port->membase + AML_UART_STATUS, reg, |
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reg & AML_UART_TX_EMPTY, |
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AML_UART_POLL_USEC, |
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AML_UART_TIMEOUT_USEC); |
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if (ret == -ETIMEDOUT) { |
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dev_err(port->dev, "Timeout waiting for UART TX EMPTY\n"); |
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goto out; |
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} |
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/* Write the character */ |
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writel(c, port->membase + AML_UART_WFIFO); |
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/* Wait until FIFO is empty or timeout */ |
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ret = readl_poll_timeout_atomic(port->membase + AML_UART_STATUS, reg, |
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reg & AML_UART_TX_EMPTY, |
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AML_UART_POLL_USEC, |
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AML_UART_TIMEOUT_USEC); |
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if (ret == -ETIMEDOUT) |
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dev_err(port->dev, "Timeout waiting for UART TX EMPTY\n"); |
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out: |
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spin_unlock_irqrestore(&port->lock, flags); |
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} |
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#endif /* CONFIG_CONSOLE_POLL */ |
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static const struct uart_ops meson_uart_ops = { |
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.set_mctrl = meson_uart_set_mctrl, |
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.get_mctrl = meson_uart_get_mctrl, |
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.tx_empty = meson_uart_tx_empty, |
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.start_tx = meson_uart_start_tx, |
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.stop_tx = meson_uart_stop_tx, |
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.stop_rx = meson_uart_stop_rx, |
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.startup = meson_uart_startup, |
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.shutdown = meson_uart_shutdown, |
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.set_termios = meson_uart_set_termios, |
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.type = meson_uart_type, |
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.config_port = meson_uart_config_port, |
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.request_port = meson_uart_request_port, |
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.release_port = meson_uart_release_port, |
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.verify_port = meson_uart_verify_port, |
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#ifdef CONFIG_CONSOLE_POLL |
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.poll_get_char = meson_uart_poll_get_char, |
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.poll_put_char = meson_uart_poll_put_char, |
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#endif |
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}; |
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#ifdef CONFIG_SERIAL_MESON_CONSOLE |
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static void meson_uart_enable_tx_engine(struct uart_port *port) |
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{ |
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u32 val; |
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val = readl(port->membase + AML_UART_CONTROL); |
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val |= AML_UART_TX_EN; |
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writel(val, port->membase + AML_UART_CONTROL); |
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} |
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static void meson_console_putchar(struct uart_port *port, int ch) |
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{ |
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if (!port->membase) |
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return; |
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while (readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL) |
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cpu_relax(); |
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writel(ch, port->membase + AML_UART_WFIFO); |
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} |
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static void meson_serial_port_write(struct uart_port *port, const char *s, |
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u_int count) |
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{ |
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unsigned long flags; |
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int locked; |
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u32 val, tmp; |
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local_irq_save(flags); |
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if (port->sysrq) { |
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locked = 0; |
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} else if (oops_in_progress) { |
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locked = spin_trylock(&port->lock); |
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} else { |
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spin_lock(&port->lock); |
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locked = 1; |
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} |
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val = readl(port->membase + AML_UART_CONTROL); |
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tmp = val & ~(AML_UART_TX_INT_EN | AML_UART_RX_INT_EN); |
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writel(tmp, port->membase + AML_UART_CONTROL); |
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uart_console_write(port, s, count, meson_console_putchar); |
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writel(val, port->membase + AML_UART_CONTROL); |
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if (locked) |
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spin_unlock(&port->lock); |
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local_irq_restore(flags); |
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} |
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static void meson_serial_console_write(struct console *co, const char *s, |
|
u_int count) |
|
{ |
|
struct uart_port *port; |
|
|
|
port = meson_ports[co->index]; |
|
if (!port) |
|
return; |
|
|
|
meson_serial_port_write(port, s, count); |
|
} |
|
|
|
static int meson_serial_console_setup(struct console *co, char *options) |
|
{ |
|
struct uart_port *port; |
|
int baud = 115200; |
|
int bits = 8; |
|
int parity = 'n'; |
|
int flow = 'n'; |
|
|
|
if (co->index < 0 || co->index >= AML_UART_PORT_NUM) |
|
return -EINVAL; |
|
|
|
port = meson_ports[co->index]; |
|
if (!port || !port->membase) |
|
return -ENODEV; |
|
|
|
meson_uart_enable_tx_engine(port); |
|
|
|
if (options) |
|
uart_parse_options(options, &baud, &parity, &bits, &flow); |
|
|
|
return uart_set_options(port, co, baud, parity, bits, flow); |
|
} |
|
|
|
static struct console meson_serial_console = { |
|
.name = AML_UART_DEV_NAME, |
|
.write = meson_serial_console_write, |
|
.device = uart_console_device, |
|
.setup = meson_serial_console_setup, |
|
.flags = CON_PRINTBUFFER, |
|
.index = -1, |
|
.data = &meson_uart_driver, |
|
}; |
|
|
|
static int __init meson_serial_console_init(void) |
|
{ |
|
register_console(&meson_serial_console); |
|
return 0; |
|
} |
|
|
|
static void meson_serial_early_console_write(struct console *co, |
|
const char *s, |
|
u_int count) |
|
{ |
|
struct earlycon_device *dev = co->data; |
|
|
|
meson_serial_port_write(&dev->port, s, count); |
|
} |
|
|
|
static int __init |
|
meson_serial_early_console_setup(struct earlycon_device *device, const char *opt) |
|
{ |
|
if (!device->port.membase) |
|
return -ENODEV; |
|
|
|
meson_uart_enable_tx_engine(&device->port); |
|
device->con->write = meson_serial_early_console_write; |
|
return 0; |
|
} |
|
/* Legacy bindings, should be removed when no more used */ |
|
OF_EARLYCON_DECLARE(meson, "amlogic,meson-uart", |
|
meson_serial_early_console_setup); |
|
/* Stable bindings */ |
|
OF_EARLYCON_DECLARE(meson, "amlogic,meson-ao-uart", |
|
meson_serial_early_console_setup); |
|
|
|
#define MESON_SERIAL_CONSOLE (&meson_serial_console) |
|
#else |
|
static int __init meson_serial_console_init(void) { |
|
return 0; |
|
} |
|
#define MESON_SERIAL_CONSOLE NULL |
|
#endif |
|
|
|
static struct uart_driver meson_uart_driver = { |
|
.owner = THIS_MODULE, |
|
.driver_name = "meson_uart", |
|
.dev_name = AML_UART_DEV_NAME, |
|
.nr = AML_UART_PORT_NUM, |
|
.cons = MESON_SERIAL_CONSOLE, |
|
}; |
|
|
|
static inline struct clk *meson_uart_probe_clock(struct device *dev, |
|
const char *id) |
|
{ |
|
struct clk *clk = NULL; |
|
int ret; |
|
|
|
clk = devm_clk_get(dev, id); |
|
if (IS_ERR(clk)) |
|
return clk; |
|
|
|
ret = clk_prepare_enable(clk); |
|
if (ret) { |
|
dev_err(dev, "couldn't enable clk\n"); |
|
return ERR_PTR(ret); |
|
} |
|
|
|
devm_add_action_or_reset(dev, |
|
(void(*)(void *))clk_disable_unprepare, |
|
clk); |
|
|
|
return clk; |
|
} |
|
|
|
/* |
|
* This function gets clocks in the legacy non-stable DT bindings. |
|
* This code will be remove once all the platforms switch to the |
|
* new DT bindings. |
|
*/ |
|
static int meson_uart_probe_clocks_legacy(struct platform_device *pdev, |
|
struct uart_port *port) |
|
{ |
|
struct clk *clk = NULL; |
|
|
|
clk = meson_uart_probe_clock(&pdev->dev, NULL); |
|
if (IS_ERR(clk)) |
|
return PTR_ERR(clk); |
|
|
|
port->uartclk = clk_get_rate(clk); |
|
|
|
return 0; |
|
} |
|
|
|
static int meson_uart_probe_clocks(struct platform_device *pdev, |
|
struct uart_port *port) |
|
{ |
|
struct clk *clk_xtal = NULL; |
|
struct clk *clk_pclk = NULL; |
|
struct clk *clk_baud = NULL; |
|
|
|
clk_pclk = meson_uart_probe_clock(&pdev->dev, "pclk"); |
|
if (IS_ERR(clk_pclk)) |
|
return PTR_ERR(clk_pclk); |
|
|
|
clk_xtal = meson_uart_probe_clock(&pdev->dev, "xtal"); |
|
if (IS_ERR(clk_xtal)) |
|
return PTR_ERR(clk_xtal); |
|
|
|
clk_baud = meson_uart_probe_clock(&pdev->dev, "baud"); |
|
if (IS_ERR(clk_baud)) |
|
return PTR_ERR(clk_baud); |
|
|
|
port->uartclk = clk_get_rate(clk_baud); |
|
|
|
return 0; |
|
} |
|
|
|
static int meson_uart_probe(struct platform_device *pdev) |
|
{ |
|
struct resource *res_mem, *res_irq; |
|
struct uart_port *port; |
|
int ret = 0; |
|
int id = -1; |
|
|
|
if (pdev->dev.of_node) |
|
pdev->id = of_alias_get_id(pdev->dev.of_node, "serial"); |
|
|
|
if (pdev->id < 0) { |
|
for (id = AML_UART_PORT_OFFSET; id < AML_UART_PORT_NUM; id++) { |
|
if (!meson_ports[id]) { |
|
pdev->id = id; |
|
break; |
|
} |
|
} |
|
} |
|
|
|
if (pdev->id < 0 || pdev->id >= AML_UART_PORT_NUM) |
|
return -EINVAL; |
|
|
|
res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
if (!res_mem) |
|
return -ENODEV; |
|
|
|
res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
|
if (!res_irq) |
|
return -ENODEV; |
|
|
|
if (meson_ports[pdev->id]) { |
|
dev_err(&pdev->dev, "port %d already allocated\n", pdev->id); |
|
return -EBUSY; |
|
} |
|
|
|
port = devm_kzalloc(&pdev->dev, sizeof(struct uart_port), GFP_KERNEL); |
|
if (!port) |
|
return -ENOMEM; |
|
|
|
/* Use legacy way until all platforms switch to new bindings */ |
|
if (of_device_is_compatible(pdev->dev.of_node, "amlogic,meson-uart")) |
|
ret = meson_uart_probe_clocks_legacy(pdev, port); |
|
else |
|
ret = meson_uart_probe_clocks(pdev, port); |
|
|
|
if (ret) |
|
return ret; |
|
|
|
port->iotype = UPIO_MEM; |
|
port->mapbase = res_mem->start; |
|
port->mapsize = resource_size(res_mem); |
|
port->irq = res_irq->start; |
|
port->flags = UPF_BOOT_AUTOCONF | UPF_LOW_LATENCY; |
|
port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MESON_CONSOLE); |
|
port->dev = &pdev->dev; |
|
port->line = pdev->id; |
|
port->type = PORT_MESON; |
|
port->x_char = 0; |
|
port->ops = &meson_uart_ops; |
|
port->fifosize = 64; |
|
|
|
meson_ports[pdev->id] = port; |
|
platform_set_drvdata(pdev, port); |
|
|
|
/* reset port before registering (and possibly registering console) */ |
|
if (meson_uart_request_port(port) >= 0) { |
|
meson_uart_reset(port); |
|
meson_uart_release_port(port); |
|
} |
|
|
|
ret = uart_add_one_port(&meson_uart_driver, port); |
|
if (ret) |
|
meson_ports[pdev->id] = NULL; |
|
|
|
return ret; |
|
} |
|
|
|
static int meson_uart_remove(struct platform_device *pdev) |
|
{ |
|
struct uart_port *port; |
|
|
|
port = platform_get_drvdata(pdev); |
|
uart_remove_one_port(&meson_uart_driver, port); |
|
meson_ports[pdev->id] = NULL; |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id meson_uart_dt_match[] = { |
|
/* Legacy bindings, should be removed when no more used */ |
|
{ .compatible = "amlogic,meson-uart" }, |
|
/* Stable bindings */ |
|
{ .compatible = "amlogic,meson6-uart" }, |
|
{ .compatible = "amlogic,meson8-uart" }, |
|
{ .compatible = "amlogic,meson8b-uart" }, |
|
{ .compatible = "amlogic,meson-gx-uart" }, |
|
{ /* sentinel */ }, |
|
}; |
|
MODULE_DEVICE_TABLE(of, meson_uart_dt_match); |
|
|
|
static struct platform_driver meson_uart_platform_driver = { |
|
.probe = meson_uart_probe, |
|
.remove = meson_uart_remove, |
|
.driver = { |
|
.name = "meson_uart", |
|
.of_match_table = meson_uart_dt_match, |
|
}, |
|
}; |
|
|
|
static int __init meson_uart_init(void) |
|
{ |
|
int ret; |
|
|
|
ret = meson_serial_console_init(); |
|
if (ret) |
|
return ret; |
|
|
|
ret = uart_register_driver(&meson_uart_driver); |
|
if (ret) |
|
return ret; |
|
|
|
ret = platform_driver_register(&meson_uart_platform_driver); |
|
if (ret) |
|
uart_unregister_driver(&meson_uart_driver); |
|
|
|
return ret; |
|
} |
|
|
|
static void __exit meson_uart_exit(void) |
|
{ |
|
platform_driver_unregister(&meson_uart_platform_driver); |
|
uart_unregister_driver(&meson_uart_driver); |
|
} |
|
|
|
module_init(meson_uart_init); |
|
module_exit(meson_uart_exit); |
|
|
|
MODULE_AUTHOR("Carlo Caione <[email protected]>"); |
|
MODULE_DESCRIPTION("Amlogic Meson serial port driver"); |
|
MODULE_LICENSE("GPL v2");
|
|
|