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971 lines
24 KiB
971 lines
24 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright 2003 Digi International (www.digi.com) |
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* Scott H Kilau <Scott_Kilau at digi dot com> |
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* |
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* NOTE TO LINUX KERNEL HACKERS: DO NOT REFORMAT THIS CODE! |
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* |
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* This is shared code between Digi's CVS archive and the |
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* Linux Kernel sources. |
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* Changing the source just for reformatting needlessly breaks |
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* our CVS diff history. |
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* |
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* Send any bug fixes/changes to: Eng.Linux at digi dot com. |
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* Thank you. |
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* |
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*/ |
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#include <linux/delay.h> /* For udelay */ |
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#include <linux/io.h> /* For read[bwl]/write[bwl] */ |
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#include <linux/serial.h> /* For struct async_serial */ |
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#include <linux/serial_reg.h> /* For the various UART offsets */ |
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#include <linux/pci.h> |
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#include <linux/tty.h> |
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#include "jsm.h" /* Driver main header file */ |
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static struct { |
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unsigned int rate; |
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unsigned int cflag; |
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} baud_rates[] = { |
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{ 921600, B921600 }, |
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{ 460800, B460800 }, |
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{ 230400, B230400 }, |
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{ 115200, B115200 }, |
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{ 57600, B57600 }, |
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{ 38400, B38400 }, |
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{ 19200, B19200 }, |
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{ 9600, B9600 }, |
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{ 4800, B4800 }, |
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{ 2400, B2400 }, |
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{ 1200, B1200 }, |
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{ 600, B600 }, |
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{ 300, B300 }, |
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{ 200, B200 }, |
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{ 150, B150 }, |
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{ 134, B134 }, |
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{ 110, B110 }, |
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{ 75, B75 }, |
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{ 50, B50 }, |
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}; |
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static void cls_set_cts_flow_control(struct jsm_channel *ch) |
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{ |
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u8 lcrb = readb(&ch->ch_cls_uart->lcr); |
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u8 ier = readb(&ch->ch_cls_uart->ier); |
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u8 isr_fcr = 0; |
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|
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/* |
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* The Enhanced Register Set may only be accessed when |
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* the Line Control Register is set to 0xBFh. |
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*/ |
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writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); |
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isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); |
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|
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/* Turn on CTS flow control, turn off IXON flow control */ |
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isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_CTSDSR); |
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isr_fcr &= ~(UART_EXAR654_EFR_IXON); |
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writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); |
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|
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/* Write old LCR value back out, which turns enhanced access off */ |
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writeb(lcrb, &ch->ch_cls_uart->lcr); |
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|
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/* |
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* Enable interrupts for CTS flow, turn off interrupts for |
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* received XOFF chars |
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*/ |
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ier |= (UART_EXAR654_IER_CTSDSR); |
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ier &= ~(UART_EXAR654_IER_XOFF); |
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writeb(ier, &ch->ch_cls_uart->ier); |
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|
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/* Set the usual FIFO values */ |
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writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); |
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writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 | |
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UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR), |
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&ch->ch_cls_uart->isr_fcr); |
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ch->ch_t_tlevel = 16; |
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} |
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static void cls_set_ixon_flow_control(struct jsm_channel *ch) |
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{ |
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u8 lcrb = readb(&ch->ch_cls_uart->lcr); |
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u8 ier = readb(&ch->ch_cls_uart->ier); |
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u8 isr_fcr = 0; |
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/* |
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* The Enhanced Register Set may only be accessed when |
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* the Line Control Register is set to 0xBFh. |
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*/ |
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writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); |
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isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); |
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|
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/* Turn on IXON flow control, turn off CTS flow control */ |
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isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXON); |
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isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR); |
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writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); |
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/* Now set our current start/stop chars while in enhanced mode */ |
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writeb(ch->ch_startc, &ch->ch_cls_uart->mcr); |
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writeb(0, &ch->ch_cls_uart->lsr); |
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writeb(ch->ch_stopc, &ch->ch_cls_uart->msr); |
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writeb(0, &ch->ch_cls_uart->spr); |
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|
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/* Write old LCR value back out, which turns enhanced access off */ |
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writeb(lcrb, &ch->ch_cls_uart->lcr); |
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/* |
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* Disable interrupts for CTS flow, turn on interrupts for |
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* received XOFF chars |
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*/ |
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ier &= ~(UART_EXAR654_IER_CTSDSR); |
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ier |= (UART_EXAR654_IER_XOFF); |
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writeb(ier, &ch->ch_cls_uart->ier); |
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|
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/* Set the usual FIFO values */ |
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writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); |
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writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 | |
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UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR), |
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&ch->ch_cls_uart->isr_fcr); |
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} |
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static void cls_set_no_output_flow_control(struct jsm_channel *ch) |
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{ |
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u8 lcrb = readb(&ch->ch_cls_uart->lcr); |
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u8 ier = readb(&ch->ch_cls_uart->ier); |
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u8 isr_fcr = 0; |
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/* |
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* The Enhanced Register Set may only be accessed when |
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* the Line Control Register is set to 0xBFh. |
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*/ |
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writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); |
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isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); |
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|
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/* Turn off IXON flow control, turn off CTS flow control */ |
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isr_fcr |= (UART_EXAR654_EFR_ECB); |
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isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR | UART_EXAR654_EFR_IXON); |
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writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); |
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|
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/* Write old LCR value back out, which turns enhanced access off */ |
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writeb(lcrb, &ch->ch_cls_uart->lcr); |
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|
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/* |
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* Disable interrupts for CTS flow, turn off interrupts for |
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* received XOFF chars |
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*/ |
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ier &= ~(UART_EXAR654_IER_CTSDSR); |
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ier &= ~(UART_EXAR654_IER_XOFF); |
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writeb(ier, &ch->ch_cls_uart->ier); |
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|
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/* Set the usual FIFO values */ |
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writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); |
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writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 | |
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UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR), |
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&ch->ch_cls_uart->isr_fcr); |
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ch->ch_r_watermark = 0; |
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ch->ch_t_tlevel = 16; |
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ch->ch_r_tlevel = 16; |
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} |
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static void cls_set_rts_flow_control(struct jsm_channel *ch) |
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{ |
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u8 lcrb = readb(&ch->ch_cls_uart->lcr); |
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u8 ier = readb(&ch->ch_cls_uart->ier); |
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u8 isr_fcr = 0; |
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|
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/* |
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* The Enhanced Register Set may only be accessed when |
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* the Line Control Register is set to 0xBFh. |
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*/ |
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writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); |
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isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); |
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/* Turn on RTS flow control, turn off IXOFF flow control */ |
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isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_RTSDTR); |
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isr_fcr &= ~(UART_EXAR654_EFR_IXOFF); |
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writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); |
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|
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/* Write old LCR value back out, which turns enhanced access off */ |
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writeb(lcrb, &ch->ch_cls_uart->lcr); |
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/* Enable interrupts for RTS flow */ |
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ier |= (UART_EXAR654_IER_RTSDTR); |
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writeb(ier, &ch->ch_cls_uart->ier); |
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/* Set the usual FIFO values */ |
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writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); |
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writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 | |
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UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR), |
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&ch->ch_cls_uart->isr_fcr); |
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ch->ch_r_watermark = 4; |
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ch->ch_r_tlevel = 8; |
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} |
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static void cls_set_ixoff_flow_control(struct jsm_channel *ch) |
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{ |
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u8 lcrb = readb(&ch->ch_cls_uart->lcr); |
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u8 ier = readb(&ch->ch_cls_uart->ier); |
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u8 isr_fcr = 0; |
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/* |
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* The Enhanced Register Set may only be accessed when |
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* the Line Control Register is set to 0xBFh. |
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*/ |
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writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); |
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isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); |
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/* Turn on IXOFF flow control, turn off RTS flow control */ |
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isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXOFF); |
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isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR); |
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writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); |
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/* Now set our current start/stop chars while in enhanced mode */ |
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writeb(ch->ch_startc, &ch->ch_cls_uart->mcr); |
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writeb(0, &ch->ch_cls_uart->lsr); |
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writeb(ch->ch_stopc, &ch->ch_cls_uart->msr); |
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writeb(0, &ch->ch_cls_uart->spr); |
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|
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/* Write old LCR value back out, which turns enhanced access off */ |
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writeb(lcrb, &ch->ch_cls_uart->lcr); |
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|
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/* Disable interrupts for RTS flow */ |
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ier &= ~(UART_EXAR654_IER_RTSDTR); |
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writeb(ier, &ch->ch_cls_uart->ier); |
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/* Set the usual FIFO values */ |
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writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); |
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writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 | |
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UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR), |
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&ch->ch_cls_uart->isr_fcr); |
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} |
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static void cls_set_no_input_flow_control(struct jsm_channel *ch) |
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{ |
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u8 lcrb = readb(&ch->ch_cls_uart->lcr); |
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u8 ier = readb(&ch->ch_cls_uart->ier); |
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u8 isr_fcr = 0; |
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/* |
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* The Enhanced Register Set may only be accessed when |
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* the Line Control Register is set to 0xBFh. |
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*/ |
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writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); |
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isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); |
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/* Turn off IXOFF flow control, turn off RTS flow control */ |
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isr_fcr |= (UART_EXAR654_EFR_ECB); |
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isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR | UART_EXAR654_EFR_IXOFF); |
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writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); |
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/* Write old LCR value back out, which turns enhanced access off */ |
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writeb(lcrb, &ch->ch_cls_uart->lcr); |
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|
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/* Disable interrupts for RTS flow */ |
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ier &= ~(UART_EXAR654_IER_RTSDTR); |
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writeb(ier, &ch->ch_cls_uart->ier); |
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/* Set the usual FIFO values */ |
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writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr); |
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writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 | |
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UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR), |
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&ch->ch_cls_uart->isr_fcr); |
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ch->ch_t_tlevel = 16; |
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ch->ch_r_tlevel = 16; |
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} |
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/* |
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* cls_clear_break. |
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* Determines whether its time to shut off break condition. |
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* |
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* No locks are assumed to be held when calling this function. |
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* channel lock is held and released in this function. |
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*/ |
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static void cls_clear_break(struct jsm_channel *ch) |
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{ |
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unsigned long lock_flags; |
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spin_lock_irqsave(&ch->ch_lock, lock_flags); |
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/* Turn break off, and unset some variables */ |
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if (ch->ch_flags & CH_BREAK_SENDING) { |
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u8 temp = readb(&ch->ch_cls_uart->lcr); |
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writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr); |
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ch->ch_flags &= ~(CH_BREAK_SENDING); |
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jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, |
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"clear break Finishing UART_LCR_SBC! finished: %lx\n", |
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jiffies); |
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} |
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spin_unlock_irqrestore(&ch->ch_lock, lock_flags); |
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} |
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static void cls_disable_receiver(struct jsm_channel *ch) |
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{ |
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u8 tmp = readb(&ch->ch_cls_uart->ier); |
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tmp &= ~(UART_IER_RDI); |
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writeb(tmp, &ch->ch_cls_uart->ier); |
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} |
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static void cls_enable_receiver(struct jsm_channel *ch) |
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{ |
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u8 tmp = readb(&ch->ch_cls_uart->ier); |
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tmp |= (UART_IER_RDI); |
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writeb(tmp, &ch->ch_cls_uart->ier); |
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} |
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/* Make the UART raise any of the output signals we want up */ |
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static void cls_assert_modem_signals(struct jsm_channel *ch) |
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{ |
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if (!ch) |
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return; |
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writeb(ch->ch_mostat, &ch->ch_cls_uart->mcr); |
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} |
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static void cls_copy_data_from_uart_to_queue(struct jsm_channel *ch) |
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{ |
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int qleft = 0; |
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u8 linestatus = 0; |
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u8 error_mask = 0; |
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u16 head; |
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u16 tail; |
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unsigned long flags; |
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if (!ch) |
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return; |
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spin_lock_irqsave(&ch->ch_lock, flags); |
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/* cache head and tail of queue */ |
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head = ch->ch_r_head & RQUEUEMASK; |
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tail = ch->ch_r_tail & RQUEUEMASK; |
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|
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/* Get our cached LSR */ |
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linestatus = ch->ch_cached_lsr; |
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ch->ch_cached_lsr = 0; |
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|
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/* Store how much space we have left in the queue */ |
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qleft = tail - head - 1; |
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if (qleft < 0) |
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qleft += RQUEUEMASK + 1; |
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|
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/* |
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* Create a mask to determine whether we should |
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* insert the character (if any) into our queue. |
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*/ |
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if (ch->ch_c_iflag & IGNBRK) |
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error_mask |= UART_LSR_BI; |
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|
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while (1) { |
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/* |
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* Grab the linestatus register, we need to |
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* check to see if there is any data to read |
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*/ |
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linestatus = readb(&ch->ch_cls_uart->lsr); |
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|
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/* Break out if there is no data to fetch */ |
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if (!(linestatus & UART_LSR_DR)) |
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break; |
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/* |
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* Discard character if we are ignoring the error mask |
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* which in this case is the break signal. |
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*/ |
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if (linestatus & error_mask) { |
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linestatus = 0; |
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readb(&ch->ch_cls_uart->txrx); |
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continue; |
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} |
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/* |
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* If our queue is full, we have no choice but to drop some |
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* data. The assumption is that HWFLOW or SWFLOW should have |
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* stopped things way way before we got to this point. |
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* |
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* I decided that I wanted to ditch the oldest data first, |
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* I hope thats okay with everyone? Yes? Good. |
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*/ |
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while (qleft < 1) { |
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tail = (tail + 1) & RQUEUEMASK; |
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ch->ch_r_tail = tail; |
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ch->ch_err_overrun++; |
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qleft++; |
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} |
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|
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ch->ch_equeue[head] = linestatus & (UART_LSR_BI | UART_LSR_PE |
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| UART_LSR_FE); |
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ch->ch_rqueue[head] = readb(&ch->ch_cls_uart->txrx); |
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|
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qleft--; |
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|
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if (ch->ch_equeue[head] & UART_LSR_PE) |
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ch->ch_err_parity++; |
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if (ch->ch_equeue[head] & UART_LSR_BI) |
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ch->ch_err_break++; |
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if (ch->ch_equeue[head] & UART_LSR_FE) |
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ch->ch_err_frame++; |
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|
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/* Add to, and flip head if needed */ |
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head = (head + 1) & RQUEUEMASK; |
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ch->ch_rxcount++; |
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} |
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|
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/* |
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* Write new final heads to channel structure. |
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*/ |
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ch->ch_r_head = head & RQUEUEMASK; |
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ch->ch_e_head = head & EQUEUEMASK; |
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|
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spin_unlock_irqrestore(&ch->ch_lock, flags); |
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} |
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|
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static void cls_copy_data_from_queue_to_uart(struct jsm_channel *ch) |
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{ |
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u16 tail; |
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int n; |
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int qlen; |
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u32 len_written = 0; |
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struct circ_buf *circ; |
|
|
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if (!ch) |
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return; |
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|
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circ = &ch->uart_port.state->xmit; |
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|
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/* No data to write to the UART */ |
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if (uart_circ_empty(circ)) |
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return; |
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|
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/* If port is "stopped", don't send any data to the UART */ |
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if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING)) |
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return; |
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|
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/* We have to do it this way, because of the EXAR TXFIFO count bug. */ |
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if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) |
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return; |
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|
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n = 32; |
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|
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/* cache tail of queue */ |
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tail = circ->tail & (UART_XMIT_SIZE - 1); |
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qlen = uart_circ_chars_pending(circ); |
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|
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/* Find minimum of the FIFO space, versus queue length */ |
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n = min(n, qlen); |
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|
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while (n > 0) { |
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writeb(circ->buf[tail], &ch->ch_cls_uart->txrx); |
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tail = (tail + 1) & (UART_XMIT_SIZE - 1); |
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n--; |
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ch->ch_txcount++; |
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len_written++; |
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} |
|
|
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/* Update the final tail */ |
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circ->tail = tail & (UART_XMIT_SIZE - 1); |
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|
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if (len_written > ch->ch_t_tlevel) |
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ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); |
|
|
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if (uart_circ_empty(circ)) |
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uart_write_wakeup(&ch->uart_port); |
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} |
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|
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static void cls_parse_modem(struct jsm_channel *ch, u8 signals) |
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{ |
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u8 msignals = signals; |
|
|
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jsm_dbg(MSIGS, &ch->ch_bd->pci_dev, |
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"neo_parse_modem: port: %d msignals: %x\n", |
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ch->ch_portnum, msignals); |
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|
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/* |
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* Scrub off lower bits. |
|
* They signify delta's, which I don't care about |
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* Keep DDCD and DDSR though |
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*/ |
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msignals &= 0xf8; |
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|
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if (msignals & UART_MSR_DDCD) |
|
uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD); |
|
if (msignals & UART_MSR_DDSR) |
|
uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_CTS); |
|
|
|
if (msignals & UART_MSR_DCD) |
|
ch->ch_mistat |= UART_MSR_DCD; |
|
else |
|
ch->ch_mistat &= ~UART_MSR_DCD; |
|
|
|
if (msignals & UART_MSR_DSR) |
|
ch->ch_mistat |= UART_MSR_DSR; |
|
else |
|
ch->ch_mistat &= ~UART_MSR_DSR; |
|
|
|
if (msignals & UART_MSR_RI) |
|
ch->ch_mistat |= UART_MSR_RI; |
|
else |
|
ch->ch_mistat &= ~UART_MSR_RI; |
|
|
|
if (msignals & UART_MSR_CTS) |
|
ch->ch_mistat |= UART_MSR_CTS; |
|
else |
|
ch->ch_mistat &= ~UART_MSR_CTS; |
|
|
|
jsm_dbg(MSIGS, &ch->ch_bd->pci_dev, |
|
"Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n", |
|
ch->ch_portnum, |
|
!!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR), |
|
!!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS), |
|
!!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS), |
|
!!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR), |
|
!!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI), |
|
!!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD)); |
|
} |
|
|
|
/* Parse the ISR register for the specific port */ |
|
static inline void cls_parse_isr(struct jsm_board *brd, uint port) |
|
{ |
|
struct jsm_channel *ch; |
|
u8 isr = 0; |
|
unsigned long flags; |
|
|
|
/* |
|
* No need to verify board pointer, it was already |
|
* verified in the interrupt routine. |
|
*/ |
|
|
|
if (port >= brd->nasync) |
|
return; |
|
|
|
ch = brd->channels[port]; |
|
if (!ch) |
|
return; |
|
|
|
/* Here we try to figure out what caused the interrupt to happen */ |
|
while (1) { |
|
isr = readb(&ch->ch_cls_uart->isr_fcr); |
|
|
|
/* Bail if no pending interrupt on port */ |
|
if (isr & UART_IIR_NO_INT) |
|
break; |
|
|
|
/* Receive Interrupt pending */ |
|
if (isr & (UART_IIR_RDI | UART_IIR_RDI_TIMEOUT)) { |
|
/* Read data from uart -> queue */ |
|
cls_copy_data_from_uart_to_queue(ch); |
|
jsm_check_queue_flow_control(ch); |
|
} |
|
|
|
/* Transmit Hold register empty pending */ |
|
if (isr & UART_IIR_THRI) { |
|
/* Transfer data (if any) from Write Queue -> UART. */ |
|
spin_lock_irqsave(&ch->ch_lock, flags); |
|
ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); |
|
spin_unlock_irqrestore(&ch->ch_lock, flags); |
|
cls_copy_data_from_queue_to_uart(ch); |
|
} |
|
|
|
/* |
|
* CTS/RTS change of state: |
|
* Don't need to do anything, the cls_parse_modem |
|
* below will grab the updated modem signals. |
|
*/ |
|
|
|
/* Parse any modem signal changes */ |
|
cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr)); |
|
} |
|
} |
|
|
|
/* Channel lock MUST be held before calling this function! */ |
|
static void cls_flush_uart_write(struct jsm_channel *ch) |
|
{ |
|
u8 tmp = 0; |
|
u8 i = 0; |
|
|
|
if (!ch) |
|
return; |
|
|
|
writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), |
|
&ch->ch_cls_uart->isr_fcr); |
|
|
|
for (i = 0; i < 10; i++) { |
|
/* Check to see if the UART feels it completely flushed FIFO */ |
|
tmp = readb(&ch->ch_cls_uart->isr_fcr); |
|
if (tmp & UART_FCR_CLEAR_XMIT) { |
|
jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, |
|
"Still flushing TX UART... i: %d\n", i); |
|
udelay(10); |
|
} else |
|
break; |
|
} |
|
|
|
ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); |
|
} |
|
|
|
/* Channel lock MUST be held before calling this function! */ |
|
static void cls_flush_uart_read(struct jsm_channel *ch) |
|
{ |
|
if (!ch) |
|
return; |
|
|
|
/* |
|
* For complete POSIX compatibility, we should be purging the |
|
* read FIFO in the UART here. |
|
* |
|
* However, clearing the read FIFO (UART_FCR_CLEAR_RCVR) also |
|
* incorrectly flushes write data as well as just basically trashing the |
|
* FIFO. |
|
* |
|
* Presumably, this is a bug in this UART. |
|
*/ |
|
|
|
udelay(10); |
|
} |
|
|
|
static void cls_send_start_character(struct jsm_channel *ch) |
|
{ |
|
if (!ch) |
|
return; |
|
|
|
if (ch->ch_startc != __DISABLED_CHAR) { |
|
ch->ch_xon_sends++; |
|
writeb(ch->ch_startc, &ch->ch_cls_uart->txrx); |
|
} |
|
} |
|
|
|
static void cls_send_stop_character(struct jsm_channel *ch) |
|
{ |
|
if (!ch) |
|
return; |
|
|
|
if (ch->ch_stopc != __DISABLED_CHAR) { |
|
ch->ch_xoff_sends++; |
|
writeb(ch->ch_stopc, &ch->ch_cls_uart->txrx); |
|
} |
|
} |
|
|
|
/* |
|
* cls_param() |
|
* Send any/all changes to the line to the UART. |
|
*/ |
|
static void cls_param(struct jsm_channel *ch) |
|
{ |
|
u8 lcr = 0; |
|
u8 uart_lcr = 0; |
|
u8 ier = 0; |
|
u32 baud = 9600; |
|
int quot = 0; |
|
struct jsm_board *bd; |
|
int i; |
|
unsigned int cflag; |
|
|
|
bd = ch->ch_bd; |
|
if (!bd) |
|
return; |
|
|
|
/* |
|
* If baud rate is zero, flush queues, and set mval to drop DTR. |
|
*/ |
|
if ((ch->ch_c_cflag & (CBAUD)) == 0) { |
|
ch->ch_r_head = 0; |
|
ch->ch_r_tail = 0; |
|
ch->ch_e_head = 0; |
|
ch->ch_e_tail = 0; |
|
|
|
cls_flush_uart_write(ch); |
|
cls_flush_uart_read(ch); |
|
|
|
/* The baudrate is B0 so all modem lines are to be dropped. */ |
|
ch->ch_flags |= (CH_BAUD0); |
|
ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR); |
|
cls_assert_modem_signals(ch); |
|
return; |
|
} |
|
|
|
cflag = C_BAUD(ch->uart_port.state->port.tty); |
|
baud = 9600; |
|
for (i = 0; i < ARRAY_SIZE(baud_rates); i++) { |
|
if (baud_rates[i].cflag == cflag) { |
|
baud = baud_rates[i].rate; |
|
break; |
|
} |
|
} |
|
|
|
if (ch->ch_flags & CH_BAUD0) |
|
ch->ch_flags &= ~(CH_BAUD0); |
|
|
|
if (ch->ch_c_cflag & PARENB) |
|
lcr |= UART_LCR_PARITY; |
|
|
|
if (!(ch->ch_c_cflag & PARODD)) |
|
lcr |= UART_LCR_EPAR; |
|
|
|
/* |
|
* Not all platforms support mark/space parity, |
|
* so this will hide behind an ifdef. |
|
*/ |
|
#ifdef CMSPAR |
|
if (ch->ch_c_cflag & CMSPAR) |
|
lcr |= UART_LCR_SPAR; |
|
#endif |
|
|
|
if (ch->ch_c_cflag & CSTOPB) |
|
lcr |= UART_LCR_STOP; |
|
|
|
switch (ch->ch_c_cflag & CSIZE) { |
|
case CS5: |
|
lcr |= UART_LCR_WLEN5; |
|
break; |
|
case CS6: |
|
lcr |= UART_LCR_WLEN6; |
|
break; |
|
case CS7: |
|
lcr |= UART_LCR_WLEN7; |
|
break; |
|
case CS8: |
|
default: |
|
lcr |= UART_LCR_WLEN8; |
|
break; |
|
} |
|
|
|
ier = readb(&ch->ch_cls_uart->ier); |
|
uart_lcr = readb(&ch->ch_cls_uart->lcr); |
|
|
|
quot = ch->ch_bd->bd_dividend / baud; |
|
|
|
if (quot != 0) { |
|
writeb(UART_LCR_DLAB, &ch->ch_cls_uart->lcr); |
|
writeb((quot & 0xff), &ch->ch_cls_uart->txrx); |
|
writeb((quot >> 8), &ch->ch_cls_uart->ier); |
|
writeb(lcr, &ch->ch_cls_uart->lcr); |
|
} |
|
|
|
if (uart_lcr != lcr) |
|
writeb(lcr, &ch->ch_cls_uart->lcr); |
|
|
|
if (ch->ch_c_cflag & CREAD) |
|
ier |= (UART_IER_RDI | UART_IER_RLSI); |
|
|
|
ier |= (UART_IER_THRI | UART_IER_MSI); |
|
|
|
writeb(ier, &ch->ch_cls_uart->ier); |
|
|
|
if (ch->ch_c_cflag & CRTSCTS) |
|
cls_set_cts_flow_control(ch); |
|
else if (ch->ch_c_iflag & IXON) { |
|
/* |
|
* If start/stop is set to disable, |
|
* then we should disable flow control. |
|
*/ |
|
if ((ch->ch_startc == __DISABLED_CHAR) || |
|
(ch->ch_stopc == __DISABLED_CHAR)) |
|
cls_set_no_output_flow_control(ch); |
|
else |
|
cls_set_ixon_flow_control(ch); |
|
} else |
|
cls_set_no_output_flow_control(ch); |
|
|
|
if (ch->ch_c_cflag & CRTSCTS) |
|
cls_set_rts_flow_control(ch); |
|
else if (ch->ch_c_iflag & IXOFF) { |
|
/* |
|
* If start/stop is set to disable, |
|
* then we should disable flow control. |
|
*/ |
|
if ((ch->ch_startc == __DISABLED_CHAR) || |
|
(ch->ch_stopc == __DISABLED_CHAR)) |
|
cls_set_no_input_flow_control(ch); |
|
else |
|
cls_set_ixoff_flow_control(ch); |
|
} else |
|
cls_set_no_input_flow_control(ch); |
|
|
|
cls_assert_modem_signals(ch); |
|
|
|
/* get current status of the modem signals now */ |
|
cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr)); |
|
} |
|
|
|
/* |
|
* cls_intr() |
|
* |
|
* Classic specific interrupt handler. |
|
*/ |
|
static irqreturn_t cls_intr(int irq, void *voidbrd) |
|
{ |
|
struct jsm_board *brd = voidbrd; |
|
unsigned long lock_flags; |
|
unsigned char uart_poll; |
|
uint i = 0; |
|
|
|
/* Lock out the slow poller from running on this board. */ |
|
spin_lock_irqsave(&brd->bd_intr_lock, lock_flags); |
|
|
|
/* |
|
* Check the board's global interrupt offset to see if we |
|
* acctually do have an interrupt pending on us. |
|
*/ |
|
uart_poll = readb(brd->re_map_membase + UART_CLASSIC_POLL_ADDR_OFFSET); |
|
|
|
jsm_dbg(INTR, &brd->pci_dev, "%s:%d uart_poll: %x\n", |
|
__FILE__, __LINE__, uart_poll); |
|
|
|
if (!uart_poll) { |
|
jsm_dbg(INTR, &brd->pci_dev, |
|
"Kernel interrupted to me, but no pending interrupts...\n"); |
|
spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags); |
|
return IRQ_NONE; |
|
} |
|
|
|
/* At this point, we have at least SOMETHING to service, dig further. */ |
|
|
|
/* Parse each port to find out what caused the interrupt */ |
|
for (i = 0; i < brd->nasync; i++) |
|
cls_parse_isr(brd, i); |
|
|
|
spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags); |
|
|
|
return IRQ_HANDLED; |
|
} |
|
|
|
/* Inits UART */ |
|
static void cls_uart_init(struct jsm_channel *ch) |
|
{ |
|
unsigned char lcrb = readb(&ch->ch_cls_uart->lcr); |
|
unsigned char isr_fcr = 0; |
|
|
|
writeb(0, &ch->ch_cls_uart->ier); |
|
|
|
/* |
|
* The Enhanced Register Set may only be accessed when |
|
* the Line Control Register is set to 0xBFh. |
|
*/ |
|
writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr); |
|
|
|
isr_fcr = readb(&ch->ch_cls_uart->isr_fcr); |
|
|
|
/* Turn on Enhanced/Extended controls */ |
|
isr_fcr |= (UART_EXAR654_EFR_ECB); |
|
|
|
writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr); |
|
|
|
/* Write old LCR value back out, which turns enhanced access off */ |
|
writeb(lcrb, &ch->ch_cls_uart->lcr); |
|
|
|
/* Clear out UART and FIFO */ |
|
readb(&ch->ch_cls_uart->txrx); |
|
|
|
writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), |
|
&ch->ch_cls_uart->isr_fcr); |
|
udelay(10); |
|
|
|
ch->ch_flags |= (CH_FIFO_ENABLED | CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); |
|
|
|
readb(&ch->ch_cls_uart->lsr); |
|
readb(&ch->ch_cls_uart->msr); |
|
} |
|
|
|
/* |
|
* Turns off UART. |
|
*/ |
|
static void cls_uart_off(struct jsm_channel *ch) |
|
{ |
|
/* Stop all interrupts from accurring. */ |
|
writeb(0, &ch->ch_cls_uart->ier); |
|
} |
|
|
|
/* |
|
* cls_get_uarts_bytes_left. |
|
* Returns 0 is nothing left in the FIFO, returns 1 otherwise. |
|
* |
|
* The channel lock MUST be held by the calling function. |
|
*/ |
|
static u32 cls_get_uart_bytes_left(struct jsm_channel *ch) |
|
{ |
|
u8 left = 0; |
|
u8 lsr = readb(&ch->ch_cls_uart->lsr); |
|
|
|
/* Determine whether the Transmitter is empty or not */ |
|
if (!(lsr & UART_LSR_TEMT)) |
|
left = 1; |
|
else { |
|
ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); |
|
left = 0; |
|
} |
|
|
|
return left; |
|
} |
|
|
|
/* |
|
* cls_send_break. |
|
* Starts sending a break thru the UART. |
|
* |
|
* The channel lock MUST be held by the calling function. |
|
*/ |
|
static void cls_send_break(struct jsm_channel *ch) |
|
{ |
|
/* Tell the UART to start sending the break */ |
|
if (!(ch->ch_flags & CH_BREAK_SENDING)) { |
|
u8 temp = readb(&ch->ch_cls_uart->lcr); |
|
|
|
writeb((temp | UART_LCR_SBC), &ch->ch_cls_uart->lcr); |
|
ch->ch_flags |= (CH_BREAK_SENDING); |
|
} |
|
} |
|
|
|
/* |
|
* cls_send_immediate_char. |
|
* Sends a specific character as soon as possible to the UART, |
|
* jumping over any bytes that might be in the write queue. |
|
* |
|
* The channel lock MUST be held by the calling function. |
|
*/ |
|
static void cls_send_immediate_char(struct jsm_channel *ch, unsigned char c) |
|
{ |
|
writeb(c, &ch->ch_cls_uart->txrx); |
|
} |
|
|
|
struct board_ops jsm_cls_ops = { |
|
.intr = cls_intr, |
|
.uart_init = cls_uart_init, |
|
.uart_off = cls_uart_off, |
|
.param = cls_param, |
|
.assert_modem_signals = cls_assert_modem_signals, |
|
.flush_uart_write = cls_flush_uart_write, |
|
.flush_uart_read = cls_flush_uart_read, |
|
.disable_receiver = cls_disable_receiver, |
|
.enable_receiver = cls_enable_receiver, |
|
.send_break = cls_send_break, |
|
.clear_break = cls_clear_break, |
|
.send_start_character = cls_send_start_character, |
|
.send_stop_character = cls_send_stop_character, |
|
.copy_data_from_queue_to_uart = cls_copy_data_from_queue_to_uart, |
|
.get_uart_bytes_left = cls_get_uart_bytes_left, |
|
.send_immediate_char = cls_send_immediate_char |
|
}; |
|
|
|
|