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297 lines
7.1 KiB
297 lines
7.1 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Marvell Berlin SATA PHY driver |
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* |
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* Copyright (C) 2014 Marvell Technology Group Ltd. |
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* |
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* Antoine Ténart <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/module.h> |
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#include <linux/phy/phy.h> |
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#include <linux/io.h> |
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#include <linux/platform_device.h> |
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#define HOST_VSA_ADDR 0x0 |
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#define HOST_VSA_DATA 0x4 |
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#define PORT_SCR_CTL 0x2c |
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#define PORT_VSR_ADDR 0x78 |
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#define PORT_VSR_DATA 0x7c |
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#define CONTROL_REGISTER 0x0 |
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#define MBUS_SIZE_CONTROL 0x4 |
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#define POWER_DOWN_PHY0 BIT(6) |
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#define POWER_DOWN_PHY1 BIT(14) |
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#define MBUS_WRITE_REQUEST_SIZE_128 (BIT(2) << 16) |
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#define MBUS_READ_REQUEST_SIZE_128 (BIT(2) << 19) |
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#define BG2_PHY_BASE 0x080 |
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#define BG2Q_PHY_BASE 0x200 |
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/* register 0x01 */ |
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#define REF_FREF_SEL_25 BIT(0) |
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#define PHY_BERLIN_MODE_SATA (0x0 << 5) |
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/* register 0x02 */ |
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#define USE_MAX_PLL_RATE BIT(12) |
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/* register 0x23 */ |
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#define DATA_BIT_WIDTH_10 (0x0 << 10) |
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#define DATA_BIT_WIDTH_20 (0x1 << 10) |
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#define DATA_BIT_WIDTH_40 (0x2 << 10) |
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/* register 0x25 */ |
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#define PHY_GEN_MAX_1_5 (0x0 << 10) |
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#define PHY_GEN_MAX_3_0 (0x1 << 10) |
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#define PHY_GEN_MAX_6_0 (0x2 << 10) |
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struct phy_berlin_desc { |
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struct phy *phy; |
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u32 power_bit; |
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unsigned index; |
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}; |
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struct phy_berlin_priv { |
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void __iomem *base; |
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spinlock_t lock; |
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struct clk *clk; |
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struct phy_berlin_desc **phys; |
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unsigned nphys; |
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u32 phy_base; |
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}; |
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static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg, |
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u32 phy_base, u32 reg, u32 mask, u32 val) |
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{ |
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u32 regval; |
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/* select register */ |
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writel(phy_base + reg, ctrl_reg + PORT_VSR_ADDR); |
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/* set bits */ |
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regval = readl(ctrl_reg + PORT_VSR_DATA); |
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regval &= ~mask; |
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regval |= val; |
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writel(regval, ctrl_reg + PORT_VSR_DATA); |
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} |
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static int phy_berlin_sata_power_on(struct phy *phy) |
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{ |
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struct phy_berlin_desc *desc = phy_get_drvdata(phy); |
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struct phy_berlin_priv *priv = dev_get_drvdata(phy->dev.parent); |
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void __iomem *ctrl_reg = priv->base + 0x60 + (desc->index * 0x80); |
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u32 regval; |
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clk_prepare_enable(priv->clk); |
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spin_lock(&priv->lock); |
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/* Power on PHY */ |
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writel(CONTROL_REGISTER, priv->base + HOST_VSA_ADDR); |
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regval = readl(priv->base + HOST_VSA_DATA); |
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regval &= ~desc->power_bit; |
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writel(regval, priv->base + HOST_VSA_DATA); |
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/* Configure MBus */ |
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writel(MBUS_SIZE_CONTROL, priv->base + HOST_VSA_ADDR); |
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regval = readl(priv->base + HOST_VSA_DATA); |
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regval |= MBUS_WRITE_REQUEST_SIZE_128 | MBUS_READ_REQUEST_SIZE_128; |
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writel(regval, priv->base + HOST_VSA_DATA); |
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/* set PHY mode and ref freq to 25 MHz */ |
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phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01, |
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0x00ff, |
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REF_FREF_SEL_25 | PHY_BERLIN_MODE_SATA); |
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/* set PHY up to 6 Gbps */ |
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phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25, |
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0x0c00, PHY_GEN_MAX_6_0); |
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/* set 40 bits width */ |
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phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x23, |
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0x0c00, DATA_BIT_WIDTH_40); |
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/* use max pll rate */ |
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phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x02, |
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0x0000, USE_MAX_PLL_RATE); |
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/* set Gen3 controller speed */ |
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regval = readl(ctrl_reg + PORT_SCR_CTL); |
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regval &= ~GENMASK(7, 4); |
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regval |= 0x30; |
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writel(regval, ctrl_reg + PORT_SCR_CTL); |
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spin_unlock(&priv->lock); |
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clk_disable_unprepare(priv->clk); |
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return 0; |
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} |
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static int phy_berlin_sata_power_off(struct phy *phy) |
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{ |
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struct phy_berlin_desc *desc = phy_get_drvdata(phy); |
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struct phy_berlin_priv *priv = dev_get_drvdata(phy->dev.parent); |
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u32 regval; |
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clk_prepare_enable(priv->clk); |
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spin_lock(&priv->lock); |
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/* Power down PHY */ |
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writel(CONTROL_REGISTER, priv->base + HOST_VSA_ADDR); |
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regval = readl(priv->base + HOST_VSA_DATA); |
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regval |= desc->power_bit; |
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writel(regval, priv->base + HOST_VSA_DATA); |
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spin_unlock(&priv->lock); |
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clk_disable_unprepare(priv->clk); |
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return 0; |
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} |
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static struct phy *phy_berlin_sata_phy_xlate(struct device *dev, |
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struct of_phandle_args *args) |
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{ |
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struct phy_berlin_priv *priv = dev_get_drvdata(dev); |
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int i; |
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if (WARN_ON(args->args[0] >= priv->nphys)) |
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return ERR_PTR(-ENODEV); |
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for (i = 0; i < priv->nphys; i++) { |
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if (priv->phys[i]->index == args->args[0]) |
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break; |
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} |
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if (i == priv->nphys) |
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return ERR_PTR(-ENODEV); |
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return priv->phys[i]->phy; |
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} |
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static const struct phy_ops phy_berlin_sata_ops = { |
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.power_on = phy_berlin_sata_power_on, |
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.power_off = phy_berlin_sata_power_off, |
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.owner = THIS_MODULE, |
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}; |
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static u32 phy_berlin_power_down_bits[] = { |
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POWER_DOWN_PHY0, |
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POWER_DOWN_PHY1, |
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}; |
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static int phy_berlin_sata_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct device_node *child; |
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struct phy *phy; |
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struct phy_provider *phy_provider; |
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struct phy_berlin_priv *priv; |
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struct resource *res; |
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int ret, i = 0; |
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u32 phy_id; |
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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if (!res) |
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return -EINVAL; |
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priv->base = devm_ioremap(dev, res->start, resource_size(res)); |
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if (!priv->base) |
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return -ENOMEM; |
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priv->clk = devm_clk_get(dev, NULL); |
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if (IS_ERR(priv->clk)) |
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return PTR_ERR(priv->clk); |
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priv->nphys = of_get_child_count(dev->of_node); |
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if (priv->nphys == 0) |
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return -ENODEV; |
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priv->phys = devm_kcalloc(dev, priv->nphys, sizeof(*priv->phys), |
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GFP_KERNEL); |
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if (!priv->phys) |
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return -ENOMEM; |
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if (of_device_is_compatible(dev->of_node, "marvell,berlin2-sata-phy")) |
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priv->phy_base = BG2_PHY_BASE; |
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else |
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priv->phy_base = BG2Q_PHY_BASE; |
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dev_set_drvdata(dev, priv); |
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spin_lock_init(&priv->lock); |
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for_each_available_child_of_node(dev->of_node, child) { |
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struct phy_berlin_desc *phy_desc; |
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if (of_property_read_u32(child, "reg", &phy_id)) { |
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dev_err(dev, "missing reg property in node %pOFn\n", |
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child); |
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ret = -EINVAL; |
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goto put_child; |
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} |
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if (phy_id >= ARRAY_SIZE(phy_berlin_power_down_bits)) { |
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dev_err(dev, "invalid reg in node %pOFn\n", child); |
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ret = -EINVAL; |
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goto put_child; |
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} |
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phy_desc = devm_kzalloc(dev, sizeof(*phy_desc), GFP_KERNEL); |
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if (!phy_desc) { |
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ret = -ENOMEM; |
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goto put_child; |
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} |
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phy = devm_phy_create(dev, NULL, &phy_berlin_sata_ops); |
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if (IS_ERR(phy)) { |
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dev_err(dev, "failed to create PHY %d\n", phy_id); |
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ret = PTR_ERR(phy); |
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goto put_child; |
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} |
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phy_desc->phy = phy; |
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phy_desc->power_bit = phy_berlin_power_down_bits[phy_id]; |
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phy_desc->index = phy_id; |
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phy_set_drvdata(phy, phy_desc); |
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priv->phys[i++] = phy_desc; |
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/* Make sure the PHY is off */ |
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phy_berlin_sata_power_off(phy); |
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} |
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phy_provider = |
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devm_of_phy_provider_register(dev, phy_berlin_sata_phy_xlate); |
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return PTR_ERR_OR_ZERO(phy_provider); |
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put_child: |
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of_node_put(child); |
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return ret; |
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} |
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static const struct of_device_id phy_berlin_sata_of_match[] = { |
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{ .compatible = "marvell,berlin2-sata-phy" }, |
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{ .compatible = "marvell,berlin2q-sata-phy" }, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(of, phy_berlin_sata_of_match); |
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static struct platform_driver phy_berlin_sata_driver = { |
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.probe = phy_berlin_sata_probe, |
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.driver = { |
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.name = "phy-berlin-sata", |
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.of_match_table = phy_berlin_sata_of_match, |
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}, |
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}; |
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module_platform_driver(phy_berlin_sata_driver); |
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MODULE_DESCRIPTION("Marvell Berlin SATA PHY driver"); |
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MODULE_AUTHOR("Antoine Ténart <[email protected]>"); |
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MODULE_LICENSE("GPL v2");
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