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187 lines
5.1 KiB
187 lines
5.1 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (c) 2014 Linaro Ltd. |
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* Copyright (c) 2014 Hisilicon Limited. |
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*/ |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/module.h> |
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#include <linux/phy/phy.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#define SATA_PHY0_CTLL 0xa0 |
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#define MPLL_MULTIPLIER_SHIFT 1 |
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#define MPLL_MULTIPLIER_MASK 0xfe |
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#define MPLL_MULTIPLIER_50M 0x3c |
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#define MPLL_MULTIPLIER_100M 0x1e |
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#define PHY_RESET BIT(0) |
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#define REF_SSP_EN BIT(9) |
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#define SSC_EN BIT(10) |
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#define REF_USE_PAD BIT(23) |
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#define SATA_PORT_PHYCTL 0x174 |
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#define SPEED_MODE_MASK 0x6f0000 |
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#define HALF_RATE_SHIFT 16 |
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#define PHY_CONFIG_SHIFT 18 |
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#define GEN2_EN_SHIFT 21 |
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#define SPEED_CTRL BIT(20) |
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#define SATA_PORT_PHYCTL1 0x148 |
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#define AMPLITUDE_MASK 0x3ffffe |
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#define AMPLITUDE_GEN3 0x68 |
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#define AMPLITUDE_GEN3_SHIFT 15 |
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#define AMPLITUDE_GEN2 0x56 |
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#define AMPLITUDE_GEN2_SHIFT 8 |
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#define AMPLITUDE_GEN1 0x56 |
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#define AMPLITUDE_GEN1_SHIFT 1 |
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#define SATA_PORT_PHYCTL2 0x14c |
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#define PREEMPH_MASK 0x3ffff |
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#define PREEMPH_GEN3 0x20 |
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#define PREEMPH_GEN3_SHIFT 12 |
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#define PREEMPH_GEN2 0x15 |
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#define PREEMPH_GEN2_SHIFT 6 |
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#define PREEMPH_GEN1 0x5 |
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#define PREEMPH_GEN1_SHIFT 0 |
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struct hix5hd2_priv { |
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void __iomem *base; |
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struct regmap *peri_ctrl; |
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}; |
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enum phy_speed_mode { |
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SPEED_MODE_GEN1 = 0, |
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SPEED_MODE_GEN2 = 1, |
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SPEED_MODE_GEN3 = 2, |
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}; |
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static int hix5hd2_sata_phy_init(struct phy *phy) |
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{ |
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struct hix5hd2_priv *priv = phy_get_drvdata(phy); |
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u32 val, data[2]; |
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int ret; |
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if (priv->peri_ctrl) { |
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ret = of_property_read_u32_array(phy->dev.of_node, |
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"hisilicon,power-reg", |
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&data[0], 2); |
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if (ret) { |
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dev_err(&phy->dev, "Fail read hisilicon,power-reg\n"); |
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return ret; |
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} |
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regmap_update_bits(priv->peri_ctrl, data[0], |
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BIT(data[1]), BIT(data[1])); |
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} |
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/* reset phy */ |
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val = readl_relaxed(priv->base + SATA_PHY0_CTLL); |
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val &= ~(MPLL_MULTIPLIER_MASK | REF_USE_PAD); |
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val |= MPLL_MULTIPLIER_50M << MPLL_MULTIPLIER_SHIFT | |
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REF_SSP_EN | PHY_RESET; |
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writel_relaxed(val, priv->base + SATA_PHY0_CTLL); |
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msleep(20); |
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val &= ~PHY_RESET; |
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writel_relaxed(val, priv->base + SATA_PHY0_CTLL); |
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val = readl_relaxed(priv->base + SATA_PORT_PHYCTL1); |
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val &= ~AMPLITUDE_MASK; |
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val |= AMPLITUDE_GEN3 << AMPLITUDE_GEN3_SHIFT | |
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AMPLITUDE_GEN2 << AMPLITUDE_GEN2_SHIFT | |
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AMPLITUDE_GEN1 << AMPLITUDE_GEN1_SHIFT; |
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writel_relaxed(val, priv->base + SATA_PORT_PHYCTL1); |
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val = readl_relaxed(priv->base + SATA_PORT_PHYCTL2); |
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val &= ~PREEMPH_MASK; |
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val |= PREEMPH_GEN3 << PREEMPH_GEN3_SHIFT | |
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PREEMPH_GEN2 << PREEMPH_GEN2_SHIFT | |
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PREEMPH_GEN1 << PREEMPH_GEN1_SHIFT; |
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writel_relaxed(val, priv->base + SATA_PORT_PHYCTL2); |
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/* ensure PHYCTRL setting takes effect */ |
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val = readl_relaxed(priv->base + SATA_PORT_PHYCTL); |
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val &= ~SPEED_MODE_MASK; |
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val |= SPEED_MODE_GEN1 << HALF_RATE_SHIFT | |
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SPEED_MODE_GEN1 << PHY_CONFIG_SHIFT | |
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SPEED_MODE_GEN1 << GEN2_EN_SHIFT | SPEED_CTRL; |
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writel_relaxed(val, priv->base + SATA_PORT_PHYCTL); |
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msleep(20); |
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val &= ~SPEED_MODE_MASK; |
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val |= SPEED_MODE_GEN3 << HALF_RATE_SHIFT | |
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SPEED_MODE_GEN3 << PHY_CONFIG_SHIFT | |
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SPEED_MODE_GEN3 << GEN2_EN_SHIFT | SPEED_CTRL; |
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writel_relaxed(val, priv->base + SATA_PORT_PHYCTL); |
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val &= ~(SPEED_MODE_MASK | SPEED_CTRL); |
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val |= SPEED_MODE_GEN2 << HALF_RATE_SHIFT | |
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SPEED_MODE_GEN2 << PHY_CONFIG_SHIFT | |
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SPEED_MODE_GEN2 << GEN2_EN_SHIFT; |
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writel_relaxed(val, priv->base + SATA_PORT_PHYCTL); |
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return 0; |
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} |
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static const struct phy_ops hix5hd2_sata_phy_ops = { |
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.init = hix5hd2_sata_phy_init, |
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.owner = THIS_MODULE, |
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}; |
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static int hix5hd2_sata_phy_probe(struct platform_device *pdev) |
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{ |
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struct phy_provider *phy_provider; |
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struct device *dev = &pdev->dev; |
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struct resource *res; |
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struct phy *phy; |
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struct hix5hd2_priv *priv; |
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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if (!res) |
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return -EINVAL; |
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priv->base = devm_ioremap(dev, res->start, resource_size(res)); |
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if (!priv->base) |
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return -ENOMEM; |
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priv->peri_ctrl = syscon_regmap_lookup_by_phandle(dev->of_node, |
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"hisilicon,peripheral-syscon"); |
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if (IS_ERR(priv->peri_ctrl)) |
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priv->peri_ctrl = NULL; |
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phy = devm_phy_create(dev, NULL, &hix5hd2_sata_phy_ops); |
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if (IS_ERR(phy)) { |
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dev_err(dev, "failed to create PHY\n"); |
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return PTR_ERR(phy); |
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} |
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phy_set_drvdata(phy, priv); |
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
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return PTR_ERR_OR_ZERO(phy_provider); |
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} |
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static const struct of_device_id hix5hd2_sata_phy_of_match[] = { |
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{.compatible = "hisilicon,hix5hd2-sata-phy",}, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(of, hix5hd2_sata_phy_of_match); |
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static struct platform_driver hix5hd2_sata_phy_driver = { |
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.probe = hix5hd2_sata_phy_probe, |
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.driver = { |
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.name = "hix5hd2-sata-phy", |
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.of_match_table = hix5hd2_sata_phy_of_match, |
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} |
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}; |
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module_platform_driver(hix5hd2_sata_phy_driver); |
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MODULE_AUTHOR("Jiancheng Xue <[email protected]>"); |
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MODULE_DESCRIPTION("HISILICON HIX5HD2 SATA PHY driver"); |
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MODULE_ALIAS("platform:hix5hd2-sata-phy"); |
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MODULE_LICENSE("GPL v2");
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