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509 lines
15 KiB
509 lines
15 KiB
/* |
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* ths8200 - Texas Instruments THS8200 video encoder driver |
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* |
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* Copyright 2013 Cisco Systems, Inc. and/or its affiliates. |
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* |
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* This program is free software; you may redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; version 2 of the License. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation version 2. |
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* |
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* This program is distributed .as is. WITHOUT ANY WARRANTY of any |
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* kind, whether express or implied; without even the implied warranty |
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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#include <linux/i2c.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/v4l2-dv-timings.h> |
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#include <media/v4l2-dv-timings.h> |
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#include <media/v4l2-async.h> |
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#include <media/v4l2-device.h> |
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#include "ths8200_regs.h" |
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static int debug; |
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module_param(debug, int, 0644); |
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MODULE_PARM_DESC(debug, "debug level (0-2)"); |
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MODULE_DESCRIPTION("Texas Instruments THS8200 video encoder driver"); |
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MODULE_AUTHOR("Mats Randgaard <[email protected]>"); |
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MODULE_AUTHOR("Martin Bugge <[email protected]>"); |
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MODULE_LICENSE("GPL v2"); |
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struct ths8200_state { |
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struct v4l2_subdev sd; |
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uint8_t chip_version; |
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/* Is the ths8200 powered on? */ |
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bool power_on; |
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struct v4l2_dv_timings dv_timings; |
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}; |
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static const struct v4l2_dv_timings_cap ths8200_timings_cap = { |
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.type = V4L2_DV_BT_656_1120, |
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/* keep this initialization for compatibility with GCC < 4.4.6 */ |
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.reserved = { 0 }, |
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V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1080, 25000000, 148500000, |
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V4L2_DV_BT_STD_CEA861, V4L2_DV_BT_CAP_PROGRESSIVE) |
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}; |
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static inline struct ths8200_state *to_state(struct v4l2_subdev *sd) |
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{ |
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return container_of(sd, struct ths8200_state, sd); |
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} |
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static inline unsigned htotal(const struct v4l2_bt_timings *t) |
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{ |
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return V4L2_DV_BT_FRAME_WIDTH(t); |
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} |
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static inline unsigned vtotal(const struct v4l2_bt_timings *t) |
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{ |
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return V4L2_DV_BT_FRAME_HEIGHT(t); |
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} |
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static int ths8200_read(struct v4l2_subdev *sd, u8 reg) |
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{ |
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struct i2c_client *client = v4l2_get_subdevdata(sd); |
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return i2c_smbus_read_byte_data(client, reg); |
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} |
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static int ths8200_write(struct v4l2_subdev *sd, u8 reg, u8 val) |
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{ |
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struct i2c_client *client = v4l2_get_subdevdata(sd); |
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int ret; |
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int i; |
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for (i = 0; i < 3; i++) { |
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ret = i2c_smbus_write_byte_data(client, reg, val); |
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if (ret == 0) |
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return 0; |
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} |
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v4l2_err(sd, "I2C Write Problem\n"); |
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return ret; |
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} |
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/* To set specific bits in the register, a clear-mask is given (to be AND-ed), |
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* and then the value-mask (to be OR-ed). |
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*/ |
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static inline void |
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ths8200_write_and_or(struct v4l2_subdev *sd, u8 reg, |
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uint8_t clr_mask, uint8_t val_mask) |
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{ |
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ths8200_write(sd, reg, (ths8200_read(sd, reg) & clr_mask) | val_mask); |
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} |
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#ifdef CONFIG_VIDEO_ADV_DEBUG |
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static int ths8200_g_register(struct v4l2_subdev *sd, |
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struct v4l2_dbg_register *reg) |
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{ |
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reg->val = ths8200_read(sd, reg->reg & 0xff); |
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reg->size = 1; |
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return 0; |
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} |
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static int ths8200_s_register(struct v4l2_subdev *sd, |
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const struct v4l2_dbg_register *reg) |
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{ |
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ths8200_write(sd, reg->reg & 0xff, reg->val & 0xff); |
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return 0; |
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} |
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#endif |
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static int ths8200_log_status(struct v4l2_subdev *sd) |
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{ |
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struct ths8200_state *state = to_state(sd); |
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uint8_t reg_03 = ths8200_read(sd, THS8200_CHIP_CTL); |
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v4l2_info(sd, "----- Chip status -----\n"); |
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v4l2_info(sd, "version: %u\n", state->chip_version); |
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v4l2_info(sd, "power: %s\n", (reg_03 & 0x0c) ? "off" : "on"); |
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v4l2_info(sd, "reset: %s\n", (reg_03 & 0x01) ? "off" : "on"); |
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v4l2_info(sd, "test pattern: %s\n", |
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(reg_03 & 0x20) ? "enabled" : "disabled"); |
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v4l2_info(sd, "format: %ux%u\n", |
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ths8200_read(sd, THS8200_DTG2_PIXEL_CNT_MSB) * 256 + |
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ths8200_read(sd, THS8200_DTG2_PIXEL_CNT_LSB), |
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(ths8200_read(sd, THS8200_DTG2_LINE_CNT_MSB) & 0x07) * 256 + |
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ths8200_read(sd, THS8200_DTG2_LINE_CNT_LSB)); |
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v4l2_print_dv_timings(sd->name, "Configured format:", |
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&state->dv_timings, true); |
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return 0; |
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} |
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/* Power up/down ths8200 */ |
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static int ths8200_s_power(struct v4l2_subdev *sd, int on) |
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{ |
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struct ths8200_state *state = to_state(sd); |
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v4l2_dbg(1, debug, sd, "%s: power %s\n", __func__, on ? "on" : "off"); |
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state->power_on = on; |
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/* Power up/down - leave in reset state until input video is present */ |
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ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0xf2, (on ? 0x00 : 0x0c)); |
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return 0; |
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} |
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static const struct v4l2_subdev_core_ops ths8200_core_ops = { |
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.log_status = ths8200_log_status, |
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.s_power = ths8200_s_power, |
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#ifdef CONFIG_VIDEO_ADV_DEBUG |
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.g_register = ths8200_g_register, |
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.s_register = ths8200_s_register, |
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#endif |
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}; |
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/* ----------------------------------------------------------------------------- |
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* V4L2 subdev video operations |
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*/ |
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static int ths8200_s_stream(struct v4l2_subdev *sd, int enable) |
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{ |
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struct ths8200_state *state = to_state(sd); |
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if (enable && !state->power_on) |
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ths8200_s_power(sd, true); |
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ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0xfe, |
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(enable ? 0x01 : 0x00)); |
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v4l2_dbg(1, debug, sd, "%s: %sable\n", |
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__func__, (enable ? "en" : "dis")); |
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return 0; |
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} |
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static void ths8200_core_init(struct v4l2_subdev *sd) |
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{ |
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/* setup clocks */ |
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ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0x3f, 0xc0); |
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/**** Data path control (DATA) ****/ |
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/* Set FSADJ 700 mV, |
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* bypass 422-444 interpolation, |
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* input format 30 bit RGB444 |
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*/ |
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ths8200_write(sd, THS8200_DATA_CNTL, 0x70); |
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/* DTG Mode (Video blocked during blanking |
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* VESA slave |
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*/ |
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ths8200_write(sd, THS8200_DTG1_MODE, 0x87); |
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/**** Display Timing Generator Control, Part 1 (DTG1). ****/ |
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/* Disable embedded syncs on the output by setting |
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* the amplitude to zero for all channels. |
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*/ |
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ths8200_write(sd, THS8200_DTG1_Y_SYNC_MSB, 0x00); |
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ths8200_write(sd, THS8200_DTG1_CBCR_SYNC_MSB, 0x00); |
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} |
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static void ths8200_setup(struct v4l2_subdev *sd, struct v4l2_bt_timings *bt) |
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{ |
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uint8_t polarity = 0; |
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uint16_t line_start_active_video = (bt->vsync + bt->vbackporch); |
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uint16_t line_start_front_porch = (vtotal(bt) - bt->vfrontporch); |
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/*** System ****/ |
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/* Set chip in reset while it is configured */ |
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ths8200_s_stream(sd, false); |
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/* configure video output timings */ |
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ths8200_write(sd, THS8200_DTG1_SPEC_A, bt->hsync); |
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ths8200_write(sd, THS8200_DTG1_SPEC_B, bt->hfrontporch); |
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/* Zero for progressive scan formats.*/ |
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if (!bt->interlaced) |
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ths8200_write(sd, THS8200_DTG1_SPEC_C, 0x00); |
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/* Distance from leading edge of h sync to start of active video. |
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* MSB in 0x2b |
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*/ |
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ths8200_write(sd, THS8200_DTG1_SPEC_D_LSB, |
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(bt->hbackporch + bt->hsync) & 0xff); |
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/* Zero for SDTV-mode. MSB in 0x2b */ |
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ths8200_write(sd, THS8200_DTG1_SPEC_E_LSB, 0x00); |
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/* |
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* MSB for dtg1_spec(d/e/h). See comment for |
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* corresponding LSB registers. |
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*/ |
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ths8200_write(sd, THS8200_DTG1_SPEC_DEH_MSB, |
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((bt->hbackporch + bt->hsync) & 0x100) >> 1); |
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/* h front porch */ |
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ths8200_write(sd, THS8200_DTG1_SPEC_K_LSB, (bt->hfrontporch) & 0xff); |
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ths8200_write(sd, THS8200_DTG1_SPEC_K_MSB, |
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((bt->hfrontporch) & 0x700) >> 8); |
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/* Half the line length. Used to calculate SDTV line types. */ |
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ths8200_write(sd, THS8200_DTG1_SPEC_G_LSB, (htotal(bt)/2) & 0xff); |
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ths8200_write(sd, THS8200_DTG1_SPEC_G_MSB, |
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((htotal(bt)/2) >> 8) & 0x0f); |
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/* Total pixels per line (ex. 720p: 1650) */ |
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ths8200_write(sd, THS8200_DTG1_TOT_PIXELS_MSB, htotal(bt) >> 8); |
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ths8200_write(sd, THS8200_DTG1_TOT_PIXELS_LSB, htotal(bt) & 0xff); |
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/* Frame height and field height */ |
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/* Field height should be programmed higher than frame_size for |
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* progressive scan formats |
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*/ |
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ths8200_write(sd, THS8200_DTG1_FRAME_FIELD_SZ_MSB, |
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((vtotal(bt) >> 4) & 0xf0) + 0x7); |
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ths8200_write(sd, THS8200_DTG1_FRAME_SZ_LSB, vtotal(bt) & 0xff); |
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/* Should be programmed higher than frame_size |
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* for progressive formats |
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*/ |
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if (!bt->interlaced) |
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ths8200_write(sd, THS8200_DTG1_FIELD_SZ_LSB, 0xff); |
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/**** Display Timing Generator Control, Part 2 (DTG2). ****/ |
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/* Set breakpoint line numbers and types |
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* THS8200 generates line types with different properties. A line type |
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* that sets all the RGB-outputs to zero is used in the blanking areas, |
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* while a line type that enable the RGB-outputs is used in active video |
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* area. The line numbers for start of active video, start of front |
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* porch and after the last line in the frame must be set with the |
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* corresponding line types. |
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* |
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* Line types: |
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* 0x9 - Full normal sync pulse: Blocks data when dtg1_pass is off. |
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* Used in blanking area. |
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* 0x0 - Active video: Video data is always passed. Used in active |
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* video area. |
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*/ |
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ths8200_write_and_or(sd, THS8200_DTG2_BP1_2_MSB, 0x88, |
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((line_start_active_video >> 4) & 0x70) + |
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((line_start_front_porch >> 8) & 0x07)); |
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ths8200_write(sd, THS8200_DTG2_BP3_4_MSB, ((vtotal(bt)) >> 4) & 0x70); |
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ths8200_write(sd, THS8200_DTG2_BP1_LSB, line_start_active_video & 0xff); |
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ths8200_write(sd, THS8200_DTG2_BP2_LSB, line_start_front_porch & 0xff); |
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ths8200_write(sd, THS8200_DTG2_BP3_LSB, (vtotal(bt)) & 0xff); |
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/* line types */ |
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ths8200_write(sd, THS8200_DTG2_LINETYPE1, 0x90); |
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ths8200_write(sd, THS8200_DTG2_LINETYPE2, 0x90); |
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/* h sync width transmitted */ |
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ths8200_write(sd, THS8200_DTG2_HLENGTH_LSB, bt->hsync & 0xff); |
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ths8200_write_and_or(sd, THS8200_DTG2_HLENGTH_LSB_HDLY_MSB, 0x3f, |
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(bt->hsync >> 2) & 0xc0); |
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/* The pixel value h sync is asserted on */ |
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ths8200_write_and_or(sd, THS8200_DTG2_HLENGTH_LSB_HDLY_MSB, 0xe0, |
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(htotal(bt) >> 8) & 0x1f); |
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ths8200_write(sd, THS8200_DTG2_HLENGTH_HDLY_LSB, htotal(bt)); |
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/* v sync width transmitted (must add 1 to get correct output) */ |
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ths8200_write(sd, THS8200_DTG2_VLENGTH1_LSB, (bt->vsync + 1) & 0xff); |
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ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0x3f, |
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((bt->vsync + 1) >> 2) & 0xc0); |
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/* The pixel value v sync is asserted on (must add 1 to get correct output) */ |
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ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0xf8, |
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((vtotal(bt) + 1) >> 8) & 0x7); |
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ths8200_write(sd, THS8200_DTG2_VDLY1_LSB, vtotal(bt) + 1); |
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/* For progressive video vlength2 must be set to all 0 and vdly2 must |
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* be set to all 1. |
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*/ |
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ths8200_write(sd, THS8200_DTG2_VLENGTH2_LSB, 0x00); |
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ths8200_write(sd, THS8200_DTG2_VLENGTH2_MSB_VDLY2_MSB, 0x07); |
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ths8200_write(sd, THS8200_DTG2_VDLY2_LSB, 0xff); |
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/* Internal delay factors to synchronize the sync pulses and the data */ |
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/* Experimental values delays (hor 0, ver 0) */ |
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ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_MSB, 0); |
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ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_LSB, 0); |
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ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_MSB, 0); |
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ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_LSB, 0); |
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/* Polarity of received and transmitted sync signals */ |
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if (bt->polarities & V4L2_DV_HSYNC_POS_POL) { |
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polarity |= 0x01; /* HS_IN */ |
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polarity |= 0x08; /* HS_OUT */ |
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} |
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if (bt->polarities & V4L2_DV_VSYNC_POS_POL) { |
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polarity |= 0x02; /* VS_IN */ |
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polarity |= 0x10; /* VS_OUT */ |
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} |
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/* RGB mode, no embedded timings */ |
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/* Timing of video input bus is derived from HS, VS, and FID dedicated |
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* inputs |
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*/ |
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ths8200_write(sd, THS8200_DTG2_CNTL, 0x44 | polarity); |
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/* leave reset */ |
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ths8200_s_stream(sd, true); |
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v4l2_dbg(1, debug, sd, "%s: frame %dx%d, polarity %d\n" |
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"horizontal: front porch %d, back porch %d, sync %d\n" |
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"vertical: sync %d\n", __func__, htotal(bt), vtotal(bt), |
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polarity, bt->hfrontporch, bt->hbackporch, |
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bt->hsync, bt->vsync); |
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} |
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static int ths8200_s_dv_timings(struct v4l2_subdev *sd, |
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struct v4l2_dv_timings *timings) |
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{ |
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struct ths8200_state *state = to_state(sd); |
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v4l2_dbg(1, debug, sd, "%s:\n", __func__); |
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if (!v4l2_valid_dv_timings(timings, &ths8200_timings_cap, |
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NULL, NULL)) |
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return -EINVAL; |
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if (!v4l2_find_dv_timings_cap(timings, &ths8200_timings_cap, 10, |
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NULL, NULL)) { |
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v4l2_dbg(1, debug, sd, "Unsupported format\n"); |
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return -EINVAL; |
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} |
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timings->bt.flags &= ~V4L2_DV_FL_REDUCED_FPS; |
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/* save timings */ |
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state->dv_timings = *timings; |
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ths8200_setup(sd, &timings->bt); |
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return 0; |
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} |
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static int ths8200_g_dv_timings(struct v4l2_subdev *sd, |
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struct v4l2_dv_timings *timings) |
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{ |
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struct ths8200_state *state = to_state(sd); |
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v4l2_dbg(1, debug, sd, "%s:\n", __func__); |
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*timings = state->dv_timings; |
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return 0; |
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} |
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static int ths8200_enum_dv_timings(struct v4l2_subdev *sd, |
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struct v4l2_enum_dv_timings *timings) |
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{ |
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if (timings->pad != 0) |
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return -EINVAL; |
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return v4l2_enum_dv_timings_cap(timings, &ths8200_timings_cap, |
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NULL, NULL); |
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} |
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static int ths8200_dv_timings_cap(struct v4l2_subdev *sd, |
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struct v4l2_dv_timings_cap *cap) |
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{ |
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if (cap->pad != 0) |
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return -EINVAL; |
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*cap = ths8200_timings_cap; |
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return 0; |
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} |
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/* Specific video subsystem operation handlers */ |
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static const struct v4l2_subdev_video_ops ths8200_video_ops = { |
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.s_stream = ths8200_s_stream, |
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.s_dv_timings = ths8200_s_dv_timings, |
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.g_dv_timings = ths8200_g_dv_timings, |
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}; |
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static const struct v4l2_subdev_pad_ops ths8200_pad_ops = { |
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.enum_dv_timings = ths8200_enum_dv_timings, |
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.dv_timings_cap = ths8200_dv_timings_cap, |
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}; |
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/* V4L2 top level operation handlers */ |
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static const struct v4l2_subdev_ops ths8200_ops = { |
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.core = &ths8200_core_ops, |
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.video = &ths8200_video_ops, |
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.pad = &ths8200_pad_ops, |
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}; |
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static int ths8200_probe(struct i2c_client *client) |
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{ |
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struct ths8200_state *state; |
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struct v4l2_subdev *sd; |
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int error; |
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|
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/* Check if the adapter supports the needed features */ |
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if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) |
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return -EIO; |
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state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); |
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if (!state) |
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return -ENOMEM; |
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sd = &state->sd; |
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v4l2_i2c_subdev_init(sd, client, &ths8200_ops); |
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|
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state->chip_version = ths8200_read(sd, THS8200_VERSION); |
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v4l2_dbg(1, debug, sd, "chip version 0x%x\n", state->chip_version); |
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ths8200_core_init(sd); |
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error = v4l2_async_register_subdev(&state->sd); |
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if (error) |
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return error; |
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v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, |
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client->addr << 1, client->adapter->name); |
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|
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return 0; |
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} |
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static int ths8200_remove(struct i2c_client *client) |
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{ |
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struct v4l2_subdev *sd = i2c_get_clientdata(client); |
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struct ths8200_state *decoder = to_state(sd); |
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|
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v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name, |
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client->addr << 1, client->adapter->name); |
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|
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ths8200_s_power(sd, false); |
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v4l2_async_unregister_subdev(&decoder->sd); |
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|
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return 0; |
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} |
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|
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static const struct i2c_device_id ths8200_id[] = { |
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{ "ths8200", 0 }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(i2c, ths8200_id); |
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|
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#if IS_ENABLED(CONFIG_OF) |
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static const struct of_device_id ths8200_of_match[] = { |
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{ .compatible = "ti,ths8200", }, |
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{ /* sentinel */ }, |
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}; |
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MODULE_DEVICE_TABLE(of, ths8200_of_match); |
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#endif |
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|
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static struct i2c_driver ths8200_driver = { |
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.driver = { |
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.name = "ths8200", |
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.of_match_table = of_match_ptr(ths8200_of_match), |
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}, |
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.probe_new = ths8200_probe, |
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.remove = ths8200_remove, |
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.id_table = ths8200_id, |
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}; |
|
|
|
module_i2c_driver(ths8200_driver);
|
|
|