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543 lines
13 KiB
543 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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Driver for VES1893 and VES1993 QPSK Demodulators |
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Copyright (C) 1999 Convergence Integrated Media GmbH <[email protected]> |
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Copyright (C) 2001 Ronny Strutz <[email protected]> |
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Copyright (C) 2002 Dennis Noermann <[email protected]> |
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Copyright (C) 2002-2003 Andreas Oberritter <[email protected]> |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/init.h> |
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#include <linux/string.h> |
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#include <linux/slab.h> |
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#include <linux/delay.h> |
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#include <media/dvb_frontend.h> |
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#include "ves1x93.h" |
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struct ves1x93_state { |
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struct i2c_adapter* i2c; |
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/* configuration settings */ |
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const struct ves1x93_config* config; |
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struct dvb_frontend frontend; |
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/* previous uncorrected block counter */ |
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enum fe_spectral_inversion inversion; |
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u8 *init_1x93_tab; |
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u8 *init_1x93_wtab; |
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u8 tab_size; |
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u8 demod_type; |
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u32 frequency; |
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}; |
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static int debug; |
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#define dprintk if (debug) printk |
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#define DEMOD_VES1893 0 |
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#define DEMOD_VES1993 1 |
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static u8 init_1893_tab [] = { |
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0x01, 0xa4, 0x35, 0x80, 0x2a, 0x0b, 0x55, 0xc4, |
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0x09, 0x69, 0x00, 0x86, 0x4c, 0x28, 0x7f, 0x00, |
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0x00, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
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0x80, 0x00, 0x21, 0xb0, 0x14, 0x00, 0xdc, 0x00, |
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0x81, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
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0x00, 0x55, 0x00, 0x00, 0x7f, 0x00 |
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}; |
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static u8 init_1993_tab [] = { |
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0x00, 0x9c, 0x35, 0x80, 0x6a, 0x09, 0x72, 0x8c, |
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0x09, 0x6b, 0x00, 0x00, 0x4c, 0x08, 0x00, 0x00, |
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0x00, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
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0x80, 0x40, 0x21, 0xb0, 0x00, 0x00, 0x00, 0x10, |
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0x81, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
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0x00, 0x00, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, |
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0x00, 0x55, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, |
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0x00, 0x00, 0x0e, 0x80, 0x00 |
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}; |
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static u8 init_1893_wtab[] = |
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{ |
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1,1,1,1,1,1,1,1, 1,1,0,0,1,1,0,0, |
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0,1,0,0,0,0,0,0, 1,0,1,1,0,0,0,1, |
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1,1,1,0,0,0,0,0, 0,0,1,1,0,0,0,0, |
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1,1,1,0,1,1 |
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}; |
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static u8 init_1993_wtab[] = |
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{ |
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1,1,1,1,1,1,1,1, 1,1,0,0,1,1,0,0, |
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0,1,0,0,0,0,0,0, 1,1,1,1,0,0,0,1, |
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1,1,1,0,0,0,0,0, 0,0,1,1,0,0,0,0, |
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1,1,1,0,1,1,1,1, 1,1,1,1,1 |
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}; |
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static int ves1x93_writereg (struct ves1x93_state* state, u8 reg, u8 data) |
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{ |
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u8 buf [] = { 0x00, reg, data }; |
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struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 3 }; |
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int err; |
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if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) { |
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dprintk ("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __func__, err, reg, data); |
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return -EREMOTEIO; |
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} |
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return 0; |
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} |
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static u8 ves1x93_readreg (struct ves1x93_state* state, u8 reg) |
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{ |
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int ret; |
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u8 b0 [] = { 0x00, reg }; |
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u8 b1 [] = { 0 }; |
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struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 2 }, |
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{ .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } }; |
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ret = i2c_transfer (state->i2c, msg, 2); |
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if (ret != 2) return ret; |
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return b1[0]; |
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} |
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static int ves1x93_clr_bit (struct ves1x93_state* state) |
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{ |
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msleep(10); |
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ves1x93_writereg (state, 0, state->init_1x93_tab[0] & 0xfe); |
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ves1x93_writereg (state, 0, state->init_1x93_tab[0]); |
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msleep(50); |
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return 0; |
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} |
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static int ves1x93_set_inversion(struct ves1x93_state *state, |
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enum fe_spectral_inversion inversion) |
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{ |
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u8 val; |
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/* |
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* inversion on/off are interchanged because i and q seem to |
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* be swapped on the hardware |
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*/ |
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switch (inversion) { |
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case INVERSION_OFF: |
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val = 0xc0; |
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break; |
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case INVERSION_ON: |
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val = 0x80; |
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break; |
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case INVERSION_AUTO: |
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val = 0x00; |
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break; |
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default: |
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return -EINVAL; |
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} |
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return ves1x93_writereg (state, 0x0c, (state->init_1x93_tab[0x0c] & 0x3f) | val); |
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} |
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static int ves1x93_set_fec(struct ves1x93_state *state, enum fe_code_rate fec) |
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{ |
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if (fec == FEC_AUTO) |
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return ves1x93_writereg (state, 0x0d, 0x08); |
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else if (fec < FEC_1_2 || fec > FEC_8_9) |
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return -EINVAL; |
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else |
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return ves1x93_writereg (state, 0x0d, fec - FEC_1_2); |
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} |
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static enum fe_code_rate ves1x93_get_fec(struct ves1x93_state *state) |
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{ |
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return FEC_1_2 + ((ves1x93_readreg (state, 0x0d) >> 4) & 0x7); |
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} |
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static int ves1x93_set_symbolrate (struct ves1x93_state* state, u32 srate) |
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{ |
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u32 BDR; |
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u32 ratio; |
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u8 ADCONF, FCONF, FNR, AGCR; |
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u32 BDRI; |
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u32 tmp; |
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u32 FIN; |
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dprintk("%s: srate == %d\n", __func__, (unsigned int) srate); |
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if (srate > state->config->xin/2) |
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srate = state->config->xin/2; |
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if (srate < 500000) |
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srate = 500000; |
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#define MUL (1UL<<26) |
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FIN = (state->config->xin + 6000) >> 4; |
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tmp = srate << 6; |
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ratio = tmp / FIN; |
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tmp = (tmp % FIN) << 8; |
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ratio = (ratio << 8) + tmp / FIN; |
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tmp = (tmp % FIN) << 8; |
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ratio = (ratio << 8) + tmp / FIN; |
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FNR = 0xff; |
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if (ratio < MUL/3) FNR = 0; |
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if (ratio < (MUL*11)/50) FNR = 1; |
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if (ratio < MUL/6) FNR = 2; |
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if (ratio < MUL/9) FNR = 3; |
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if (ratio < MUL/12) FNR = 4; |
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if (ratio < (MUL*11)/200) FNR = 5; |
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if (ratio < MUL/24) FNR = 6; |
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if (ratio < (MUL*27)/1000) FNR = 7; |
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if (ratio < MUL/48) FNR = 8; |
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if (ratio < (MUL*137)/10000) FNR = 9; |
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if (FNR == 0xff) { |
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ADCONF = 0x89; |
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FCONF = 0x80; |
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FNR = 0; |
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} else { |
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ADCONF = 0x81; |
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FCONF = 0x88 | (FNR >> 1) | ((FNR & 0x01) << 5); |
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/*FCONF = 0x80 | ((FNR & 0x01) << 5) | (((FNR > 1) & 0x03) << 3) | ((FNR >> 1) & 0x07);*/ |
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} |
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BDR = (( (ratio << (FNR >> 1)) >> 4) + 1) >> 1; |
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BDRI = ( ((FIN << 8) / ((srate << (FNR >> 1)) >> 2)) + 1) >> 1; |
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dprintk("FNR= %d\n", FNR); |
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dprintk("ratio= %08x\n", (unsigned int) ratio); |
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dprintk("BDR= %08x\n", (unsigned int) BDR); |
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dprintk("BDRI= %02x\n", (unsigned int) BDRI); |
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if (BDRI > 0xff) |
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BDRI = 0xff; |
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ves1x93_writereg (state, 0x06, 0xff & BDR); |
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ves1x93_writereg (state, 0x07, 0xff & (BDR >> 8)); |
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ves1x93_writereg (state, 0x08, 0x0f & (BDR >> 16)); |
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ves1x93_writereg (state, 0x09, BDRI); |
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ves1x93_writereg (state, 0x20, ADCONF); |
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ves1x93_writereg (state, 0x21, FCONF); |
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AGCR = state->init_1x93_tab[0x05]; |
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if (state->config->invert_pwm) |
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AGCR |= 0x20; |
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if (srate < 6000000) |
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AGCR |= 0x80; |
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else |
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AGCR &= ~0x80; |
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ves1x93_writereg (state, 0x05, AGCR); |
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/* ves1993 hates this, will lose lock */ |
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if (state->demod_type != DEMOD_VES1993) |
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ves1x93_clr_bit (state); |
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return 0; |
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} |
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static int ves1x93_init (struct dvb_frontend* fe) |
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{ |
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struct ves1x93_state* state = fe->demodulator_priv; |
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int i; |
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int val; |
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dprintk("%s: init chip\n", __func__); |
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for (i = 0; i < state->tab_size; i++) { |
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if (state->init_1x93_wtab[i]) { |
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val = state->init_1x93_tab[i]; |
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if (state->config->invert_pwm && (i == 0x05)) val |= 0x20; /* invert PWM */ |
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ves1x93_writereg (state, i, val); |
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} |
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} |
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return 0; |
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} |
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static int ves1x93_set_voltage(struct dvb_frontend *fe, |
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enum fe_sec_voltage voltage) |
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{ |
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struct ves1x93_state* state = fe->demodulator_priv; |
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switch (voltage) { |
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case SEC_VOLTAGE_13: |
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return ves1x93_writereg (state, 0x1f, 0x20); |
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case SEC_VOLTAGE_18: |
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return ves1x93_writereg (state, 0x1f, 0x30); |
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case SEC_VOLTAGE_OFF: |
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return ves1x93_writereg (state, 0x1f, 0x00); |
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default: |
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return -EINVAL; |
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} |
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} |
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static int ves1x93_read_status(struct dvb_frontend *fe, |
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enum fe_status *status) |
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{ |
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struct ves1x93_state* state = fe->demodulator_priv; |
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u8 sync = ves1x93_readreg (state, 0x0e); |
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/* |
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* The ves1893 sometimes returns sync values that make no sense, |
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* because, e.g., the SIGNAL bit is 0, while some of the higher |
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* bits are 1 (and how can there be a CARRIER w/o a SIGNAL?). |
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* Tests showed that the VITERBI and SYNC bits are returned |
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* reliably, while the SIGNAL and CARRIER bits ar sometimes wrong. |
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* If such a case occurs, we read the value again, until we get a |
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* valid value. |
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*/ |
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int maxtry = 10; /* just for safety - let's not get stuck here */ |
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while ((sync & 0x03) != 0x03 && (sync & 0x0c) && maxtry--) { |
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msleep(10); |
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sync = ves1x93_readreg (state, 0x0e); |
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} |
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*status = 0; |
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if (sync & 1) |
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*status |= FE_HAS_SIGNAL; |
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if (sync & 2) |
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*status |= FE_HAS_CARRIER; |
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if (sync & 4) |
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*status |= FE_HAS_VITERBI; |
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if (sync & 8) |
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*status |= FE_HAS_SYNC; |
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if ((sync & 0x1f) == 0x1f) |
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*status |= FE_HAS_LOCK; |
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return 0; |
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} |
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static int ves1x93_read_ber(struct dvb_frontend* fe, u32* ber) |
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{ |
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struct ves1x93_state* state = fe->demodulator_priv; |
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*ber = ves1x93_readreg (state, 0x15); |
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*ber |= (ves1x93_readreg (state, 0x16) << 8); |
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*ber |= ((ves1x93_readreg (state, 0x17) & 0x0F) << 16); |
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*ber *= 10; |
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return 0; |
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} |
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static int ves1x93_read_signal_strength(struct dvb_frontend* fe, u16* strength) |
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{ |
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struct ves1x93_state* state = fe->demodulator_priv; |
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u8 signal = ~ves1x93_readreg (state, 0x0b); |
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*strength = (signal << 8) | signal; |
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return 0; |
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} |
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static int ves1x93_read_snr(struct dvb_frontend* fe, u16* snr) |
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{ |
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struct ves1x93_state* state = fe->demodulator_priv; |
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u8 _snr = ~ves1x93_readreg (state, 0x1c); |
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*snr = (_snr << 8) | _snr; |
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return 0; |
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} |
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static int ves1x93_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) |
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{ |
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struct ves1x93_state* state = fe->demodulator_priv; |
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*ucblocks = ves1x93_readreg (state, 0x18) & 0x7f; |
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if (*ucblocks == 0x7f) |
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*ucblocks = 0xffffffff; /* counter overflow... */ |
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ves1x93_writereg (state, 0x18, 0x00); /* reset the counter */ |
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ves1x93_writereg (state, 0x18, 0x80); /* dto. */ |
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return 0; |
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} |
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static int ves1x93_set_frontend(struct dvb_frontend *fe) |
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{ |
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struct dtv_frontend_properties *p = &fe->dtv_property_cache; |
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struct ves1x93_state* state = fe->demodulator_priv; |
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if (fe->ops.tuner_ops.set_params) { |
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fe->ops.tuner_ops.set_params(fe); |
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if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); |
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} |
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ves1x93_set_inversion (state, p->inversion); |
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ves1x93_set_fec(state, p->fec_inner); |
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ves1x93_set_symbolrate(state, p->symbol_rate); |
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state->inversion = p->inversion; |
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state->frequency = p->frequency; |
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return 0; |
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} |
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static int ves1x93_get_frontend(struct dvb_frontend *fe, |
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struct dtv_frontend_properties *p) |
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{ |
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struct ves1x93_state* state = fe->demodulator_priv; |
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int afc; |
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afc = ((int)((char)(ves1x93_readreg (state, 0x0a) << 1)))/2; |
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afc = (afc * (int)(p->symbol_rate/1000/8))/16; |
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p->frequency = state->frequency - afc; |
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/* |
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* inversion indicator is only valid |
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* if auto inversion was used |
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*/ |
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if (state->inversion == INVERSION_AUTO) |
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p->inversion = (ves1x93_readreg (state, 0x0f) & 2) ? |
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INVERSION_OFF : INVERSION_ON; |
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p->fec_inner = ves1x93_get_fec(state); |
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/* XXX FIXME: timing offset !! */ |
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return 0; |
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} |
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static int ves1x93_sleep(struct dvb_frontend* fe) |
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{ |
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struct ves1x93_state* state = fe->demodulator_priv; |
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return ves1x93_writereg (state, 0x00, 0x08); |
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} |
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static void ves1x93_release(struct dvb_frontend* fe) |
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{ |
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struct ves1x93_state* state = fe->demodulator_priv; |
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kfree(state); |
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} |
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static int ves1x93_i2c_gate_ctrl(struct dvb_frontend* fe, int enable) |
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{ |
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struct ves1x93_state* state = fe->demodulator_priv; |
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if (enable) { |
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return ves1x93_writereg(state, 0x00, 0x11); |
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} else { |
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return ves1x93_writereg(state, 0x00, 0x01); |
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} |
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} |
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static const struct dvb_frontend_ops ves1x93_ops; |
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struct dvb_frontend* ves1x93_attach(const struct ves1x93_config* config, |
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struct i2c_adapter* i2c) |
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{ |
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struct ves1x93_state* state = NULL; |
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u8 identity; |
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/* allocate memory for the internal state */ |
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state = kzalloc(sizeof(struct ves1x93_state), GFP_KERNEL); |
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if (state == NULL) goto error; |
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/* setup the state */ |
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state->config = config; |
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state->i2c = i2c; |
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state->inversion = INVERSION_OFF; |
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/* check if the demod is there + identify it */ |
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identity = ves1x93_readreg(state, 0x1e); |
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switch (identity) { |
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case 0xdc: /* VES1893A rev1 */ |
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printk("ves1x93: Detected ves1893a rev1\n"); |
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state->demod_type = DEMOD_VES1893; |
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state->init_1x93_tab = init_1893_tab; |
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state->init_1x93_wtab = init_1893_wtab; |
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state->tab_size = sizeof(init_1893_tab); |
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break; |
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case 0xdd: /* VES1893A rev2 */ |
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printk("ves1x93: Detected ves1893a rev2\n"); |
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state->demod_type = DEMOD_VES1893; |
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state->init_1x93_tab = init_1893_tab; |
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state->init_1x93_wtab = init_1893_wtab; |
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state->tab_size = sizeof(init_1893_tab); |
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break; |
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case 0xde: /* VES1993 */ |
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printk("ves1x93: Detected ves1993\n"); |
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state->demod_type = DEMOD_VES1993; |
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state->init_1x93_tab = init_1993_tab; |
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state->init_1x93_wtab = init_1993_wtab; |
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state->tab_size = sizeof(init_1993_tab); |
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break; |
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default: |
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goto error; |
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} |
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/* create dvb_frontend */ |
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memcpy(&state->frontend.ops, &ves1x93_ops, sizeof(struct dvb_frontend_ops)); |
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state->frontend.demodulator_priv = state; |
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return &state->frontend; |
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error: |
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kfree(state); |
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return NULL; |
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} |
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static const struct dvb_frontend_ops ves1x93_ops = { |
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.delsys = { SYS_DVBS }, |
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.info = { |
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.name = "VLSI VES1x93 DVB-S", |
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.frequency_min_hz = 950 * MHz, |
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.frequency_max_hz = 2150 * MHz, |
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.frequency_stepsize_hz = 125 * kHz, |
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.frequency_tolerance_hz = 29500 * kHz, |
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.symbol_rate_min = 1000000, |
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.symbol_rate_max = 45000000, |
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/* .symbol_rate_tolerance = ???,*/ |
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.caps = FE_CAN_INVERSION_AUTO | |
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FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | |
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FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | |
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FE_CAN_QPSK |
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}, |
|
|
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.release = ves1x93_release, |
|
|
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.init = ves1x93_init, |
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.sleep = ves1x93_sleep, |
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.i2c_gate_ctrl = ves1x93_i2c_gate_ctrl, |
|
|
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.set_frontend = ves1x93_set_frontend, |
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.get_frontend = ves1x93_get_frontend, |
|
|
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.read_status = ves1x93_read_status, |
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.read_ber = ves1x93_read_ber, |
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.read_signal_strength = ves1x93_read_signal_strength, |
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.read_snr = ves1x93_read_snr, |
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.read_ucblocks = ves1x93_read_ucblocks, |
|
|
|
.set_voltage = ves1x93_set_voltage, |
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}; |
|
|
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module_param(debug, int, 0644); |
|
|
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MODULE_DESCRIPTION("VLSI VES1x93 DVB-S Demodulator driver"); |
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MODULE_AUTHOR("Ralph Metzler"); |
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MODULE_LICENSE("GPL"); |
|
|
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EXPORT_SYMBOL(ves1x93_attach);
|
|
|