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16 KiB
775 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* cxd2880_tnrdmd_dvbt_mon.c |
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* Sony CXD2880 DVB-T2/T tuner + demodulator driver |
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* DVB-T monitor functions |
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* |
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* Copyright (C) 2016, 2017, 2018 Sony Semiconductor Solutions Corporation |
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*/ |
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#include "cxd2880_tnrdmd_mon.h" |
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#include "cxd2880_tnrdmd_dvbt.h" |
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#include "cxd2880_tnrdmd_dvbt_mon.h" |
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|
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#include <media/dvb_math.h> |
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static const int ref_dbm_1000[3][5] = { |
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{-93000, -91000, -90000, -89000, -88000}, |
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{-87000, -85000, -84000, -83000, -82000}, |
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{-82000, -80000, -78000, -77000, -76000}, |
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}; |
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static int is_tps_locked(struct cxd2880_tnrdmd *tnr_dmd); |
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int cxd2880_tnrdmd_dvbt_mon_sync_stat(struct cxd2880_tnrdmd |
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*tnr_dmd, u8 *sync_stat, |
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u8 *ts_lock_stat, |
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u8 *unlock_detected) |
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{ |
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u8 rdata = 0x00; |
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int ret; |
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if (!tnr_dmd || !sync_stat || !ts_lock_stat || !unlock_detected) |
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return -EINVAL; |
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if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE) |
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return -EINVAL; |
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if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT) |
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return -EINVAL; |
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ret = tnr_dmd->io->write_reg(tnr_dmd->io, |
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CXD2880_IO_TGT_DMD, |
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0x00, 0x0d); |
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if (ret) |
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return ret; |
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ret = tnr_dmd->io->read_regs(tnr_dmd->io, |
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CXD2880_IO_TGT_DMD, |
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0x10, &rdata, 1); |
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if (ret) |
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return ret; |
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*unlock_detected = (rdata & 0x10) ? 1 : 0; |
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*sync_stat = rdata & 0x07; |
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*ts_lock_stat = (rdata & 0x20) ? 1 : 0; |
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if (*sync_stat == 0x07) |
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return -EAGAIN; |
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return ret; |
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} |
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int cxd2880_tnrdmd_dvbt_mon_sync_stat_sub(struct cxd2880_tnrdmd |
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*tnr_dmd, u8 *sync_stat, |
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u8 *unlock_detected) |
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{ |
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u8 ts_lock_stat = 0; |
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if (!tnr_dmd || !sync_stat || !unlock_detected) |
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return -EINVAL; |
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if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN) |
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return -EINVAL; |
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return cxd2880_tnrdmd_dvbt_mon_sync_stat(tnr_dmd->diver_sub, |
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sync_stat, |
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&ts_lock_stat, |
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unlock_detected); |
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} |
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int cxd2880_tnrdmd_dvbt_mon_mode_guard(struct cxd2880_tnrdmd |
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*tnr_dmd, |
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enum cxd2880_dvbt_mode |
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*mode, |
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enum cxd2880_dvbt_guard |
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*guard) |
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{ |
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u8 rdata = 0x00; |
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int ret; |
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if (!tnr_dmd || !mode || !guard) |
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return -EINVAL; |
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if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE) |
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return -EINVAL; |
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if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT) |
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return -EINVAL; |
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ret = slvt_freeze_reg(tnr_dmd); |
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if (ret) |
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return ret; |
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ret = is_tps_locked(tnr_dmd); |
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if (ret) { |
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slvt_unfreeze_reg(tnr_dmd); |
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if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) |
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ret = |
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cxd2880_tnrdmd_dvbt_mon_mode_guard(tnr_dmd->diver_sub, |
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mode, guard); |
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return ret; |
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} |
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ret = tnr_dmd->io->write_reg(tnr_dmd->io, |
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CXD2880_IO_TGT_DMD, |
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0x00, 0x0d); |
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if (ret) { |
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slvt_unfreeze_reg(tnr_dmd); |
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return ret; |
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} |
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ret = tnr_dmd->io->read_regs(tnr_dmd->io, |
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CXD2880_IO_TGT_DMD, |
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0x1b, &rdata, 1); |
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if (ret) { |
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slvt_unfreeze_reg(tnr_dmd); |
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return ret; |
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} |
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slvt_unfreeze_reg(tnr_dmd); |
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*mode = (enum cxd2880_dvbt_mode)((rdata >> 2) & 0x03); |
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*guard = (enum cxd2880_dvbt_guard)(rdata & 0x03); |
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return ret; |
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} |
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int cxd2880_tnrdmd_dvbt_mon_carrier_offset(struct cxd2880_tnrdmd |
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*tnr_dmd, int *offset) |
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{ |
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u8 rdata[4]; |
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u32 ctl_val = 0; |
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int ret; |
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if (!tnr_dmd || !offset) |
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return -EINVAL; |
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if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE) |
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return -EINVAL; |
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if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT) |
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return -EINVAL; |
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ret = slvt_freeze_reg(tnr_dmd); |
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if (ret) |
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return ret; |
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ret = is_tps_locked(tnr_dmd); |
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if (ret) { |
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slvt_unfreeze_reg(tnr_dmd); |
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return ret; |
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} |
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ret = tnr_dmd->io->write_reg(tnr_dmd->io, |
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CXD2880_IO_TGT_DMD, |
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0x00, 0x0d); |
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if (ret) { |
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slvt_unfreeze_reg(tnr_dmd); |
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return ret; |
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} |
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ret = tnr_dmd->io->read_regs(tnr_dmd->io, |
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CXD2880_IO_TGT_DMD, |
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0x1d, rdata, 4); |
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if (ret) { |
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slvt_unfreeze_reg(tnr_dmd); |
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return ret; |
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} |
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slvt_unfreeze_reg(tnr_dmd); |
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ctl_val = |
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((rdata[0] & 0x1f) << 24) | (rdata[1] << 16) | (rdata[2] << 8) | |
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(rdata[3]); |
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*offset = cxd2880_convert2s_complement(ctl_val, 29); |
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*offset = -1 * ((*offset) * tnr_dmd->bandwidth / 235); |
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return ret; |
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} |
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int cxd2880_tnrdmd_dvbt_mon_carrier_offset_sub(struct |
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cxd2880_tnrdmd |
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*tnr_dmd, |
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int *offset) |
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{ |
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if (!tnr_dmd || !offset) |
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return -EINVAL; |
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if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN) |
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return -EINVAL; |
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return cxd2880_tnrdmd_dvbt_mon_carrier_offset(tnr_dmd->diver_sub, |
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offset); |
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} |
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int cxd2880_tnrdmd_dvbt_mon_tps_info(struct cxd2880_tnrdmd |
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*tnr_dmd, |
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struct cxd2880_dvbt_tpsinfo |
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*info) |
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{ |
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u8 rdata[7]; |
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u8 cell_id_ok = 0; |
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int ret; |
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if (!tnr_dmd || !info) |
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return -EINVAL; |
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if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE) |
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return -EINVAL; |
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if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT) |
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return -EINVAL; |
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ret = slvt_freeze_reg(tnr_dmd); |
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if (ret) |
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return ret; |
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ret = is_tps_locked(tnr_dmd); |
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if (ret) { |
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slvt_unfreeze_reg(tnr_dmd); |
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if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) |
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ret = |
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cxd2880_tnrdmd_dvbt_mon_tps_info(tnr_dmd->diver_sub, |
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info); |
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return ret; |
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} |
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ret = tnr_dmd->io->write_reg(tnr_dmd->io, |
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CXD2880_IO_TGT_DMD, |
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0x00, 0x0d); |
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if (ret) { |
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slvt_unfreeze_reg(tnr_dmd); |
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return ret; |
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} |
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ret = tnr_dmd->io->read_regs(tnr_dmd->io, |
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CXD2880_IO_TGT_DMD, |
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0x29, rdata, 7); |
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if (ret) { |
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slvt_unfreeze_reg(tnr_dmd); |
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return ret; |
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} |
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ret = tnr_dmd->io->write_reg(tnr_dmd->io, |
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CXD2880_IO_TGT_DMD, |
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0x00, 0x11); |
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if (ret) { |
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slvt_unfreeze_reg(tnr_dmd); |
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return ret; |
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} |
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ret = tnr_dmd->io->read_regs(tnr_dmd->io, |
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CXD2880_IO_TGT_DMD, |
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0xd5, &cell_id_ok, 1); |
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if (ret) { |
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slvt_unfreeze_reg(tnr_dmd); |
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return ret; |
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} |
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slvt_unfreeze_reg(tnr_dmd); |
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info->constellation = |
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(enum cxd2880_dvbt_constellation)((rdata[0] >> 6) & 0x03); |
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info->hierarchy = (enum cxd2880_dvbt_hierarchy)((rdata[0] >> 3) & 0x07); |
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info->rate_hp = (enum cxd2880_dvbt_coderate)(rdata[0] & 0x07); |
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info->rate_lp = (enum cxd2880_dvbt_coderate)((rdata[1] >> 5) & 0x07); |
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info->guard = (enum cxd2880_dvbt_guard)((rdata[1] >> 3) & 0x03); |
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info->mode = (enum cxd2880_dvbt_mode)((rdata[1] >> 1) & 0x03); |
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info->fnum = (rdata[2] >> 6) & 0x03; |
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info->length_indicator = rdata[2] & 0x3f; |
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info->cell_id = (rdata[3] << 8) | rdata[4]; |
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info->reserved_even = rdata[5] & 0x3f; |
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info->reserved_odd = rdata[6] & 0x3f; |
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info->cell_id_ok = cell_id_ok & 0x01; |
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return ret; |
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} |
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int cxd2880_tnrdmd_dvbt_mon_packet_error_number(struct |
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cxd2880_tnrdmd |
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*tnr_dmd, |
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u32 *pen) |
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{ |
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u8 rdata[3]; |
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int ret; |
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if (!tnr_dmd || !pen) |
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return -EINVAL; |
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if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB) |
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return -EINVAL; |
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if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE) |
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return -EINVAL; |
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if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT) |
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return -EINVAL; |
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ret = tnr_dmd->io->write_reg(tnr_dmd->io, |
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CXD2880_IO_TGT_DMD, |
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0x00, 0x0d); |
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if (ret) |
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return ret; |
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ret = tnr_dmd->io->read_regs(tnr_dmd->io, |
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CXD2880_IO_TGT_DMD, |
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0x26, rdata, 3); |
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if (ret) |
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return ret; |
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if (!(rdata[0] & 0x01)) |
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return -EAGAIN; |
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*pen = (rdata[1] << 8) | rdata[2]; |
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return ret; |
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} |
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int cxd2880_tnrdmd_dvbt_mon_spectrum_sense(struct cxd2880_tnrdmd |
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*tnr_dmd, |
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enum |
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cxd2880_tnrdmd_spectrum_sense |
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*sense) |
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{ |
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u8 data = 0; |
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int ret; |
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if (!tnr_dmd || !sense) |
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return -EINVAL; |
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if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE) |
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return -EINVAL; |
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if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT) |
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return -EINVAL; |
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ret = slvt_freeze_reg(tnr_dmd); |
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if (ret) |
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return ret; |
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ret = is_tps_locked(tnr_dmd); |
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if (ret) { |
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slvt_unfreeze_reg(tnr_dmd); |
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if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) |
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ret = cxd2880_tnrdmd_dvbt_mon_spectrum_sense(tnr_dmd->diver_sub, |
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sense); |
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return ret; |
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} |
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ret = tnr_dmd->io->write_reg(tnr_dmd->io, |
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CXD2880_IO_TGT_DMD, |
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0x00, 0x0d); |
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if (ret) { |
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slvt_unfreeze_reg(tnr_dmd); |
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return ret; |
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} |
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ret = tnr_dmd->io->read_regs(tnr_dmd->io, |
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CXD2880_IO_TGT_DMD, |
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0x1c, &data, sizeof(data)); |
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if (ret) { |
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slvt_unfreeze_reg(tnr_dmd); |
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return ret; |
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} |
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slvt_unfreeze_reg(tnr_dmd); |
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*sense = |
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(data & 0x01) ? CXD2880_TNRDMD_SPECTRUM_INV : |
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CXD2880_TNRDMD_SPECTRUM_NORMAL; |
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return ret; |
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} |
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static int dvbt_read_snr_reg(struct cxd2880_tnrdmd *tnr_dmd, |
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u16 *reg_value) |
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{ |
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u8 rdata[2]; |
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int ret; |
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if (!tnr_dmd || !reg_value) |
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return -EINVAL; |
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ret = slvt_freeze_reg(tnr_dmd); |
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if (ret) |
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return ret; |
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ret = is_tps_locked(tnr_dmd); |
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if (ret) { |
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slvt_unfreeze_reg(tnr_dmd); |
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return ret; |
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} |
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ret = tnr_dmd->io->write_reg(tnr_dmd->io, |
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CXD2880_IO_TGT_DMD, |
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0x00, 0x0d); |
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if (ret) { |
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slvt_unfreeze_reg(tnr_dmd); |
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return ret; |
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} |
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ret = tnr_dmd->io->read_regs(tnr_dmd->io, |
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CXD2880_IO_TGT_DMD, |
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0x13, rdata, 2); |
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if (ret) { |
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slvt_unfreeze_reg(tnr_dmd); |
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return ret; |
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} |
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slvt_unfreeze_reg(tnr_dmd); |
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*reg_value = (rdata[0] << 8) | rdata[1]; |
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return ret; |
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} |
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static int dvbt_calc_snr(struct cxd2880_tnrdmd *tnr_dmd, |
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u32 reg_value, int *snr) |
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{ |
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if (!tnr_dmd || !snr) |
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return -EINVAL; |
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if (reg_value == 0) |
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return -EAGAIN; |
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if (reg_value > 4996) |
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reg_value = 4996; |
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*snr = intlog10(reg_value) - intlog10(5350 - reg_value); |
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*snr = (*snr + 839) / 1678 + 28500; |
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return 0; |
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} |
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int cxd2880_tnrdmd_dvbt_mon_snr(struct cxd2880_tnrdmd *tnr_dmd, |
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int *snr) |
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{ |
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u16 reg_value = 0; |
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int ret; |
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if (!tnr_dmd || !snr) |
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return -EINVAL; |
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*snr = -1000 * 1000; |
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if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB) |
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return -EINVAL; |
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if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE) |
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return -EINVAL; |
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if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT) |
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return -EINVAL; |
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if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SINGLE) { |
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ret = dvbt_read_snr_reg(tnr_dmd, ®_value); |
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if (ret) |
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return ret; |
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ret = dvbt_calc_snr(tnr_dmd, reg_value, snr); |
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} else { |
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int snr_main = 0; |
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int snr_sub = 0; |
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ret = |
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cxd2880_tnrdmd_dvbt_mon_snr_diver(tnr_dmd, snr, &snr_main, |
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&snr_sub); |
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} |
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return ret; |
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} |
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int cxd2880_tnrdmd_dvbt_mon_snr_diver(struct cxd2880_tnrdmd |
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*tnr_dmd, int *snr, |
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int *snr_main, int *snr_sub) |
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{ |
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u16 reg_value = 0; |
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u32 reg_value_sum = 0; |
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int ret; |
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if (!tnr_dmd || !snr || !snr_main || !snr_sub) |
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return -EINVAL; |
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*snr = -1000 * 1000; |
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*snr_main = -1000 * 1000; |
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*snr_sub = -1000 * 1000; |
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if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN) |
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return -EINVAL; |
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if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE) |
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return -EINVAL; |
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if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT) |
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return -EINVAL; |
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ret = dvbt_read_snr_reg(tnr_dmd, ®_value); |
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if (!ret) { |
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ret = dvbt_calc_snr(tnr_dmd, reg_value, snr_main); |
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if (ret) |
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reg_value = 0; |
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} else if (ret == -EAGAIN) { |
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reg_value = 0; |
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} else { |
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return ret; |
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} |
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reg_value_sum += reg_value; |
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ret = dvbt_read_snr_reg(tnr_dmd->diver_sub, ®_value); |
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if (!ret) { |
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ret = dvbt_calc_snr(tnr_dmd->diver_sub, reg_value, snr_sub); |
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if (ret) |
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reg_value = 0; |
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} else if (ret == -EAGAIN) { |
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reg_value = 0; |
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} else { |
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return ret; |
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} |
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reg_value_sum += reg_value; |
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|
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return dvbt_calc_snr(tnr_dmd, reg_value_sum, snr); |
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} |
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|
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int cxd2880_tnrdmd_dvbt_mon_sampling_offset(struct cxd2880_tnrdmd |
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*tnr_dmd, int *ppm) |
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{ |
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u8 ctl_val_reg[5]; |
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u8 nominal_rate_reg[5]; |
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u32 trl_ctl_val = 0; |
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u32 trcg_nominal_rate = 0; |
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int num; |
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int den; |
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s8 diff_upper = 0; |
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int ret; |
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|
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if (!tnr_dmd || !ppm) |
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return -EINVAL; |
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|
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if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE) |
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return -EINVAL; |
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|
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if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT) |
|
return -EINVAL; |
|
|
|
ret = slvt_freeze_reg(tnr_dmd); |
|
if (ret) |
|
return ret; |
|
|
|
ret = is_tps_locked(tnr_dmd); |
|
if (ret) { |
|
slvt_unfreeze_reg(tnr_dmd); |
|
return ret; |
|
} |
|
|
|
ret = tnr_dmd->io->write_reg(tnr_dmd->io, |
|
CXD2880_IO_TGT_DMD, |
|
0x00, 0x0d); |
|
if (ret) { |
|
slvt_unfreeze_reg(tnr_dmd); |
|
return ret; |
|
} |
|
|
|
ret = tnr_dmd->io->read_regs(tnr_dmd->io, |
|
CXD2880_IO_TGT_DMD, |
|
0x21, ctl_val_reg, |
|
sizeof(ctl_val_reg)); |
|
if (ret) { |
|
slvt_unfreeze_reg(tnr_dmd); |
|
return ret; |
|
} |
|
|
|
ret = tnr_dmd->io->write_reg(tnr_dmd->io, |
|
CXD2880_IO_TGT_DMD, |
|
0x00, 0x04); |
|
if (ret) { |
|
slvt_unfreeze_reg(tnr_dmd); |
|
return ret; |
|
} |
|
|
|
ret = tnr_dmd->io->read_regs(tnr_dmd->io, |
|
CXD2880_IO_TGT_DMD, |
|
0x60, nominal_rate_reg, |
|
sizeof(nominal_rate_reg)); |
|
if (ret) { |
|
slvt_unfreeze_reg(tnr_dmd); |
|
return ret; |
|
} |
|
|
|
slvt_unfreeze_reg(tnr_dmd); |
|
|
|
diff_upper = |
|
(ctl_val_reg[0] & 0x7f) - (nominal_rate_reg[0] & 0x7f); |
|
|
|
if (diff_upper < -1 || diff_upper > 1) |
|
return -EAGAIN; |
|
|
|
trl_ctl_val = ctl_val_reg[1] << 24; |
|
trl_ctl_val |= ctl_val_reg[2] << 16; |
|
trl_ctl_val |= ctl_val_reg[3] << 8; |
|
trl_ctl_val |= ctl_val_reg[4]; |
|
|
|
trcg_nominal_rate = nominal_rate_reg[1] << 24; |
|
trcg_nominal_rate |= nominal_rate_reg[2] << 16; |
|
trcg_nominal_rate |= nominal_rate_reg[3] << 8; |
|
trcg_nominal_rate |= nominal_rate_reg[4]; |
|
|
|
trl_ctl_val >>= 1; |
|
trcg_nominal_rate >>= 1; |
|
|
|
if (diff_upper == 1) |
|
num = |
|
(int)((trl_ctl_val + 0x80000000u) - |
|
trcg_nominal_rate); |
|
else if (diff_upper == -1) |
|
num = |
|
-(int)((trcg_nominal_rate + 0x80000000u) - |
|
trl_ctl_val); |
|
else |
|
num = (int)(trl_ctl_val - trcg_nominal_rate); |
|
|
|
den = (nominal_rate_reg[0] & 0x7f) << 24; |
|
den |= nominal_rate_reg[1] << 16; |
|
den |= nominal_rate_reg[2] << 8; |
|
den |= nominal_rate_reg[3]; |
|
den = (den + (390625 / 2)) / 390625; |
|
|
|
den >>= 1; |
|
|
|
if (num >= 0) |
|
*ppm = (num + (den / 2)) / den; |
|
else |
|
*ppm = (num - (den / 2)) / den; |
|
|
|
return ret; |
|
} |
|
|
|
int cxd2880_tnrdmd_dvbt_mon_sampling_offset_sub(struct |
|
cxd2880_tnrdmd |
|
*tnr_dmd, int *ppm) |
|
{ |
|
if (!tnr_dmd || !ppm) |
|
return -EINVAL; |
|
|
|
if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN) |
|
return -EINVAL; |
|
|
|
return cxd2880_tnrdmd_dvbt_mon_sampling_offset(tnr_dmd->diver_sub, ppm); |
|
} |
|
|
|
static int dvbt_calc_ssi(struct cxd2880_tnrdmd *tnr_dmd, |
|
int rf_lvl, u8 *ssi) |
|
{ |
|
struct cxd2880_dvbt_tpsinfo tps; |
|
int prel; |
|
int temp_ssi = 0; |
|
int ret; |
|
|
|
if (!tnr_dmd || !ssi) |
|
return -EINVAL; |
|
|
|
ret = cxd2880_tnrdmd_dvbt_mon_tps_info(tnr_dmd, &tps); |
|
if (ret) |
|
return ret; |
|
|
|
if (tps.constellation >= CXD2880_DVBT_CONSTELLATION_RESERVED_3 || |
|
tps.rate_hp >= CXD2880_DVBT_CODERATE_RESERVED_5) |
|
return -EINVAL; |
|
|
|
prel = rf_lvl - ref_dbm_1000[tps.constellation][tps.rate_hp]; |
|
|
|
if (prel < -15000) |
|
temp_ssi = 0; |
|
else if (prel < 0) |
|
temp_ssi = ((2 * (prel + 15000)) + 1500) / 3000; |
|
else if (prel < 20000) |
|
temp_ssi = (((4 * prel) + 500) / 1000) + 10; |
|
else if (prel < 35000) |
|
temp_ssi = (((2 * (prel - 20000)) + 1500) / 3000) + 90; |
|
else |
|
temp_ssi = 100; |
|
|
|
*ssi = (temp_ssi > 100) ? 100 : (u8)temp_ssi; |
|
|
|
return ret; |
|
} |
|
|
|
int cxd2880_tnrdmd_dvbt_mon_ssi(struct cxd2880_tnrdmd *tnr_dmd, |
|
u8 *ssi) |
|
{ |
|
int rf_lvl = 0; |
|
int ret; |
|
|
|
if (!tnr_dmd || !ssi) |
|
return -EINVAL; |
|
|
|
if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB) |
|
return -EINVAL; |
|
|
|
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE) |
|
return -EINVAL; |
|
|
|
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT) |
|
return -EINVAL; |
|
|
|
ret = cxd2880_tnrdmd_mon_rf_lvl(tnr_dmd, &rf_lvl); |
|
if (ret) |
|
return ret; |
|
|
|
return dvbt_calc_ssi(tnr_dmd, rf_lvl, ssi); |
|
} |
|
|
|
int cxd2880_tnrdmd_dvbt_mon_ssi_sub(struct cxd2880_tnrdmd *tnr_dmd, |
|
u8 *ssi) |
|
{ |
|
int rf_lvl = 0; |
|
int ret; |
|
|
|
if (!tnr_dmd || !ssi) |
|
return -EINVAL; |
|
|
|
if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_MAIN) |
|
return -EINVAL; |
|
|
|
if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE) |
|
return -EINVAL; |
|
|
|
if (tnr_dmd->sys != CXD2880_DTV_SYS_DVBT) |
|
return -EINVAL; |
|
|
|
ret = cxd2880_tnrdmd_mon_rf_lvl(tnr_dmd->diver_sub, &rf_lvl); |
|
if (ret) |
|
return ret; |
|
|
|
return dvbt_calc_ssi(tnr_dmd, rf_lvl, ssi); |
|
} |
|
|
|
static int is_tps_locked(struct cxd2880_tnrdmd *tnr_dmd) |
|
{ |
|
u8 sync = 0; |
|
u8 tslock = 0; |
|
u8 early_unlock = 0; |
|
int ret; |
|
|
|
if (!tnr_dmd) |
|
return -EINVAL; |
|
|
|
ret = |
|
cxd2880_tnrdmd_dvbt_mon_sync_stat(tnr_dmd, &sync, &tslock, |
|
&early_unlock); |
|
if (ret) |
|
return ret; |
|
|
|
if (sync != 6) |
|
return -EAGAIN; |
|
|
|
return 0; |
|
}
|
|
|