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242 lines
6.5 KiB
242 lines
6.5 KiB
/* |
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* Allwinner A20/A31 SoCs NMI IRQ chip driver. |
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* |
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* Carlo Caione <[email protected]> |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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#define DRV_NAME "sunxi-nmi" |
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#define pr_fmt(fmt) DRV_NAME ": " fmt |
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#include <linux/bitops.h> |
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#include <linux/device.h> |
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#include <linux/io.h> |
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#include <linux/irq.h> |
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#include <linux/interrupt.h> |
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#include <linux/irqdomain.h> |
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#include <linux/of_irq.h> |
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#include <linux/of_address.h> |
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#include <linux/of_platform.h> |
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#include <linux/irqchip.h> |
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#include <linux/irqchip/chained_irq.h> |
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#define SUNXI_NMI_SRC_TYPE_MASK 0x00000003 |
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#define SUNXI_NMI_IRQ_BIT BIT(0) |
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/* |
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* For deprecated sun6i-a31-sc-nmi compatible. |
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*/ |
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#define SUN6I_NMI_CTRL 0x00 |
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#define SUN6I_NMI_PENDING 0x04 |
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#define SUN6I_NMI_ENABLE 0x34 |
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#define SUN7I_NMI_CTRL 0x00 |
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#define SUN7I_NMI_PENDING 0x04 |
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#define SUN7I_NMI_ENABLE 0x08 |
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#define SUN9I_NMI_CTRL 0x00 |
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#define SUN9I_NMI_ENABLE 0x04 |
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#define SUN9I_NMI_PENDING 0x08 |
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enum { |
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SUNXI_SRC_TYPE_LEVEL_LOW = 0, |
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SUNXI_SRC_TYPE_EDGE_FALLING, |
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SUNXI_SRC_TYPE_LEVEL_HIGH, |
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SUNXI_SRC_TYPE_EDGE_RISING, |
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}; |
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struct sunxi_sc_nmi_reg_offs { |
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u32 ctrl; |
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u32 pend; |
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u32 enable; |
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}; |
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static const struct sunxi_sc_nmi_reg_offs sun6i_reg_offs __initconst = { |
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.ctrl = SUN6I_NMI_CTRL, |
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.pend = SUN6I_NMI_PENDING, |
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.enable = SUN6I_NMI_ENABLE, |
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}; |
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static const struct sunxi_sc_nmi_reg_offs sun7i_reg_offs __initconst = { |
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.ctrl = SUN7I_NMI_CTRL, |
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.pend = SUN7I_NMI_PENDING, |
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.enable = SUN7I_NMI_ENABLE, |
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}; |
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static const struct sunxi_sc_nmi_reg_offs sun9i_reg_offs __initconst = { |
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.ctrl = SUN9I_NMI_CTRL, |
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.pend = SUN9I_NMI_PENDING, |
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.enable = SUN9I_NMI_ENABLE, |
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}; |
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static inline void sunxi_sc_nmi_write(struct irq_chip_generic *gc, u32 off, |
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u32 val) |
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{ |
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irq_reg_writel(gc, val, off); |
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} |
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static inline u32 sunxi_sc_nmi_read(struct irq_chip_generic *gc, u32 off) |
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{ |
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return irq_reg_readl(gc, off); |
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} |
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static void sunxi_sc_nmi_handle_irq(struct irq_desc *desc) |
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{ |
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struct irq_domain *domain = irq_desc_get_handler_data(desc); |
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struct irq_chip *chip = irq_desc_get_chip(desc); |
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unsigned int virq = irq_find_mapping(domain, 0); |
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chained_irq_enter(chip, desc); |
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generic_handle_irq(virq); |
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chained_irq_exit(chip, desc); |
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} |
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static int sunxi_sc_nmi_set_type(struct irq_data *data, unsigned int flow_type) |
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{ |
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); |
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struct irq_chip_type *ct = gc->chip_types; |
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u32 src_type_reg; |
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u32 ctrl_off = ct->regs.type; |
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unsigned int src_type; |
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unsigned int i; |
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irq_gc_lock(gc); |
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switch (flow_type & IRQF_TRIGGER_MASK) { |
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case IRQ_TYPE_EDGE_FALLING: |
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src_type = SUNXI_SRC_TYPE_EDGE_FALLING; |
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break; |
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case IRQ_TYPE_EDGE_RISING: |
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src_type = SUNXI_SRC_TYPE_EDGE_RISING; |
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break; |
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case IRQ_TYPE_LEVEL_HIGH: |
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src_type = SUNXI_SRC_TYPE_LEVEL_HIGH; |
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break; |
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case IRQ_TYPE_NONE: |
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case IRQ_TYPE_LEVEL_LOW: |
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src_type = SUNXI_SRC_TYPE_LEVEL_LOW; |
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break; |
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default: |
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irq_gc_unlock(gc); |
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pr_err("Cannot assign multiple trigger modes to IRQ %d.\n", |
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data->irq); |
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return -EBADR; |
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} |
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irqd_set_trigger_type(data, flow_type); |
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irq_setup_alt_chip(data, flow_type); |
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for (i = 0; i < gc->num_ct; i++, ct++) |
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if (ct->type & flow_type) |
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ctrl_off = ct->regs.type; |
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src_type_reg = sunxi_sc_nmi_read(gc, ctrl_off); |
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src_type_reg &= ~SUNXI_NMI_SRC_TYPE_MASK; |
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src_type_reg |= src_type; |
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sunxi_sc_nmi_write(gc, ctrl_off, src_type_reg); |
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irq_gc_unlock(gc); |
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return IRQ_SET_MASK_OK; |
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} |
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static int __init sunxi_sc_nmi_irq_init(struct device_node *node, |
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const struct sunxi_sc_nmi_reg_offs *reg_offs) |
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{ |
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struct irq_domain *domain; |
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struct irq_chip_generic *gc; |
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unsigned int irq; |
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unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; |
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int ret; |
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domain = irq_domain_add_linear(node, 1, &irq_generic_chip_ops, NULL); |
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if (!domain) { |
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pr_err("Could not register interrupt domain.\n"); |
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return -ENOMEM; |
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} |
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ret = irq_alloc_domain_generic_chips(domain, 1, 2, DRV_NAME, |
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handle_fasteoi_irq, clr, 0, |
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IRQ_GC_INIT_MASK_CACHE); |
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if (ret) { |
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pr_err("Could not allocate generic interrupt chip.\n"); |
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goto fail_irqd_remove; |
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} |
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irq = irq_of_parse_and_map(node, 0); |
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if (irq <= 0) { |
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pr_err("unable to parse irq\n"); |
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ret = -EINVAL; |
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goto fail_irqd_remove; |
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} |
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gc = irq_get_domain_generic_chip(domain, 0); |
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gc->reg_base = of_io_request_and_map(node, 0, of_node_full_name(node)); |
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if (IS_ERR(gc->reg_base)) { |
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pr_err("unable to map resource\n"); |
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ret = PTR_ERR(gc->reg_base); |
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goto fail_irqd_remove; |
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} |
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gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK; |
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gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; |
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gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; |
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gc->chip_types[0].chip.irq_eoi = irq_gc_ack_set_bit; |
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gc->chip_types[0].chip.irq_set_type = sunxi_sc_nmi_set_type; |
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gc->chip_types[0].chip.flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED; |
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gc->chip_types[0].regs.ack = reg_offs->pend; |
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gc->chip_types[0].regs.mask = reg_offs->enable; |
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gc->chip_types[0].regs.type = reg_offs->ctrl; |
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gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH; |
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gc->chip_types[1].chip.name = gc->chip_types[0].chip.name; |
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gc->chip_types[1].chip.irq_ack = irq_gc_ack_set_bit; |
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gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit; |
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gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit; |
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gc->chip_types[1].chip.irq_set_type = sunxi_sc_nmi_set_type; |
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gc->chip_types[1].regs.ack = reg_offs->pend; |
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gc->chip_types[1].regs.mask = reg_offs->enable; |
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gc->chip_types[1].regs.type = reg_offs->ctrl; |
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gc->chip_types[1].handler = handle_edge_irq; |
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/* Disable any active interrupts */ |
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sunxi_sc_nmi_write(gc, reg_offs->enable, 0); |
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/* Clear any pending NMI interrupts */ |
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sunxi_sc_nmi_write(gc, reg_offs->pend, SUNXI_NMI_IRQ_BIT); |
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irq_set_chained_handler_and_data(irq, sunxi_sc_nmi_handle_irq, domain); |
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return 0; |
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fail_irqd_remove: |
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irq_domain_remove(domain); |
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return ret; |
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} |
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static int __init sun6i_sc_nmi_irq_init(struct device_node *node, |
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struct device_node *parent) |
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{ |
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return sunxi_sc_nmi_irq_init(node, &sun6i_reg_offs); |
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} |
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IRQCHIP_DECLARE(sun6i_sc_nmi, "allwinner,sun6i-a31-sc-nmi", sun6i_sc_nmi_irq_init); |
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static int __init sun7i_sc_nmi_irq_init(struct device_node *node, |
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struct device_node *parent) |
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{ |
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return sunxi_sc_nmi_irq_init(node, &sun7i_reg_offs); |
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} |
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IRQCHIP_DECLARE(sun7i_sc_nmi, "allwinner,sun7i-a20-sc-nmi", sun7i_sc_nmi_irq_init); |
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static int __init sun9i_nmi_irq_init(struct device_node *node, |
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struct device_node *parent) |
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{ |
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return sunxi_sc_nmi_irq_init(node, &sun9i_reg_offs); |
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} |
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IRQCHIP_DECLARE(sun9i_nmi, "allwinner,sun9i-a80-nmi", sun9i_nmi_irq_init);
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