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239 lines
6.5 KiB
239 lines
6.5 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Aspeed AST24XX, AST25XX, and AST26XX SCU Interrupt Controller |
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* Copyright 2019 IBM Corporation |
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* |
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* Eddie James <[email protected]> |
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*/ |
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#include <linux/bitops.h> |
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#include <linux/irq.h> |
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#include <linux/irqchip.h> |
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#include <linux/irqchip/chained_irq.h> |
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#include <linux/irqdomain.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/of_irq.h> |
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#include <linux/regmap.h> |
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#define ASPEED_SCU_IC_REG 0x018 |
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#define ASPEED_SCU_IC_SHIFT 0 |
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#define ASPEED_SCU_IC_ENABLE GENMASK(6, ASPEED_SCU_IC_SHIFT) |
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#define ASPEED_SCU_IC_NUM_IRQS 7 |
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#define ASPEED_SCU_IC_STATUS_SHIFT 16 |
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#define ASPEED_AST2600_SCU_IC0_REG 0x560 |
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#define ASPEED_AST2600_SCU_IC0_SHIFT 0 |
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#define ASPEED_AST2600_SCU_IC0_ENABLE \ |
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GENMASK(5, ASPEED_AST2600_SCU_IC0_SHIFT) |
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#define ASPEED_AST2600_SCU_IC0_NUM_IRQS 6 |
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#define ASPEED_AST2600_SCU_IC1_REG 0x570 |
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#define ASPEED_AST2600_SCU_IC1_SHIFT 4 |
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#define ASPEED_AST2600_SCU_IC1_ENABLE \ |
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GENMASK(5, ASPEED_AST2600_SCU_IC1_SHIFT) |
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#define ASPEED_AST2600_SCU_IC1_NUM_IRQS 2 |
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struct aspeed_scu_ic { |
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unsigned long irq_enable; |
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unsigned long irq_shift; |
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unsigned int num_irqs; |
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unsigned int reg; |
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struct regmap *scu; |
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struct irq_domain *irq_domain; |
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}; |
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static void aspeed_scu_ic_irq_handler(struct irq_desc *desc) |
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{ |
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unsigned int irq; |
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unsigned int sts; |
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unsigned long bit; |
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unsigned long enabled; |
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unsigned long max; |
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unsigned long status; |
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struct aspeed_scu_ic *scu_ic = irq_desc_get_handler_data(desc); |
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struct irq_chip *chip = irq_desc_get_chip(desc); |
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unsigned int mask = scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT; |
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chained_irq_enter(chip, desc); |
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/* |
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* The SCU IC has just one register to control its operation and read |
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* status. The interrupt enable bits occupy the lower 16 bits of the |
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* register, while the interrupt status bits occupy the upper 16 bits. |
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* The status bit for a given interrupt is always 16 bits shifted from |
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* the enable bit for the same interrupt. |
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* Therefore, perform the IRQ operations in the enable bit space by |
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* shifting the status down to get the mapping and then back up to |
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* clear the bit. |
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*/ |
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regmap_read(scu_ic->scu, scu_ic->reg, &sts); |
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enabled = sts & scu_ic->irq_enable; |
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status = (sts >> ASPEED_SCU_IC_STATUS_SHIFT) & enabled; |
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bit = scu_ic->irq_shift; |
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max = scu_ic->num_irqs + bit; |
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for_each_set_bit_from(bit, &status, max) { |
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irq = irq_find_mapping(scu_ic->irq_domain, |
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bit - scu_ic->irq_shift); |
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generic_handle_irq(irq); |
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regmap_update_bits(scu_ic->scu, scu_ic->reg, mask, |
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BIT(bit + ASPEED_SCU_IC_STATUS_SHIFT)); |
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} |
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chained_irq_exit(chip, desc); |
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} |
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static void aspeed_scu_ic_irq_mask(struct irq_data *data) |
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{ |
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struct aspeed_scu_ic *scu_ic = irq_data_get_irq_chip_data(data); |
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unsigned int mask = BIT(data->hwirq + scu_ic->irq_shift) | |
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(scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT); |
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/* |
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* Status bits are cleared by writing 1. In order to prevent the mask |
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* operation from clearing the status bits, they should be under the |
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* mask and written with 0. |
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*/ |
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regmap_update_bits(scu_ic->scu, scu_ic->reg, mask, 0); |
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} |
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static void aspeed_scu_ic_irq_unmask(struct irq_data *data) |
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{ |
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struct aspeed_scu_ic *scu_ic = irq_data_get_irq_chip_data(data); |
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unsigned int bit = BIT(data->hwirq + scu_ic->irq_shift); |
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unsigned int mask = bit | |
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(scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT); |
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/* |
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* Status bits are cleared by writing 1. In order to prevent the unmask |
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* operation from clearing the status bits, they should be under the |
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* mask and written with 0. |
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*/ |
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regmap_update_bits(scu_ic->scu, scu_ic->reg, mask, bit); |
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} |
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static int aspeed_scu_ic_irq_set_affinity(struct irq_data *data, |
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const struct cpumask *dest, |
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bool force) |
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{ |
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return -EINVAL; |
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} |
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static struct irq_chip aspeed_scu_ic_chip = { |
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.name = "aspeed-scu-ic", |
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.irq_mask = aspeed_scu_ic_irq_mask, |
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.irq_unmask = aspeed_scu_ic_irq_unmask, |
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.irq_set_affinity = aspeed_scu_ic_irq_set_affinity, |
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}; |
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static int aspeed_scu_ic_map(struct irq_domain *domain, unsigned int irq, |
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irq_hw_number_t hwirq) |
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{ |
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irq_set_chip_and_handler(irq, &aspeed_scu_ic_chip, handle_level_irq); |
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irq_set_chip_data(irq, domain->host_data); |
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return 0; |
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} |
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static const struct irq_domain_ops aspeed_scu_ic_domain_ops = { |
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.map = aspeed_scu_ic_map, |
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}; |
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static int aspeed_scu_ic_of_init_common(struct aspeed_scu_ic *scu_ic, |
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struct device_node *node) |
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{ |
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int irq; |
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int rc = 0; |
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if (!node->parent) { |
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rc = -ENODEV; |
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goto err; |
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} |
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scu_ic->scu = syscon_node_to_regmap(node->parent); |
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if (IS_ERR(scu_ic->scu)) { |
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rc = PTR_ERR(scu_ic->scu); |
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goto err; |
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} |
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irq = irq_of_parse_and_map(node, 0); |
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if (irq < 0) { |
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rc = irq; |
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goto err; |
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} |
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scu_ic->irq_domain = irq_domain_add_linear(node, scu_ic->num_irqs, |
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&aspeed_scu_ic_domain_ops, |
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scu_ic); |
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if (!scu_ic->irq_domain) { |
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rc = -ENOMEM; |
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goto err; |
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} |
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irq_set_chained_handler_and_data(irq, aspeed_scu_ic_irq_handler, |
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scu_ic); |
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return 0; |
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err: |
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kfree(scu_ic); |
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return rc; |
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} |
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static int __init aspeed_scu_ic_of_init(struct device_node *node, |
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struct device_node *parent) |
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{ |
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struct aspeed_scu_ic *scu_ic = kzalloc(sizeof(*scu_ic), GFP_KERNEL); |
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if (!scu_ic) |
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return -ENOMEM; |
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scu_ic->irq_enable = ASPEED_SCU_IC_ENABLE; |
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scu_ic->irq_shift = ASPEED_SCU_IC_SHIFT; |
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scu_ic->num_irqs = ASPEED_SCU_IC_NUM_IRQS; |
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scu_ic->reg = ASPEED_SCU_IC_REG; |
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return aspeed_scu_ic_of_init_common(scu_ic, node); |
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} |
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static int __init aspeed_ast2600_scu_ic0_of_init(struct device_node *node, |
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struct device_node *parent) |
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{ |
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struct aspeed_scu_ic *scu_ic = kzalloc(sizeof(*scu_ic), GFP_KERNEL); |
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if (!scu_ic) |
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return -ENOMEM; |
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scu_ic->irq_enable = ASPEED_AST2600_SCU_IC0_ENABLE; |
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scu_ic->irq_shift = ASPEED_AST2600_SCU_IC0_SHIFT; |
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scu_ic->num_irqs = ASPEED_AST2600_SCU_IC0_NUM_IRQS; |
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scu_ic->reg = ASPEED_AST2600_SCU_IC0_REG; |
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return aspeed_scu_ic_of_init_common(scu_ic, node); |
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} |
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static int __init aspeed_ast2600_scu_ic1_of_init(struct device_node *node, |
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struct device_node *parent) |
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{ |
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struct aspeed_scu_ic *scu_ic = kzalloc(sizeof(*scu_ic), GFP_KERNEL); |
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if (!scu_ic) |
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return -ENOMEM; |
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scu_ic->irq_enable = ASPEED_AST2600_SCU_IC1_ENABLE; |
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scu_ic->irq_shift = ASPEED_AST2600_SCU_IC1_SHIFT; |
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scu_ic->num_irqs = ASPEED_AST2600_SCU_IC1_NUM_IRQS; |
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scu_ic->reg = ASPEED_AST2600_SCU_IC1_REG; |
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return aspeed_scu_ic_of_init_common(scu_ic, node); |
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} |
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IRQCHIP_DECLARE(ast2400_scu_ic, "aspeed,ast2400-scu-ic", aspeed_scu_ic_of_init); |
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IRQCHIP_DECLARE(ast2500_scu_ic, "aspeed,ast2500-scu-ic", aspeed_scu_ic_of_init); |
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IRQCHIP_DECLARE(ast2600_scu_ic0, "aspeed,ast2600-scu-ic0", |
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aspeed_ast2600_scu_ic0_of_init); |
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IRQCHIP_DECLARE(ast2600_scu_ic1, "aspeed,ast2600-scu-ic1", |
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aspeed_ast2600_scu_ic1_of_init);
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