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414 lines
9.8 KiB
414 lines
9.8 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* This file is part of STM32 DAC driver |
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* |
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved |
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* Authors: Amelie Delaunay <[email protected]> |
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* Fabrice Gasnier <[email protected]> |
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*/ |
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#include <linux/bitfield.h> |
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#include <linux/delay.h> |
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#include <linux/iio/iio.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_runtime.h> |
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#include "stm32-dac-core.h" |
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#define STM32_DAC_CHANNEL_1 1 |
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#define STM32_DAC_CHANNEL_2 2 |
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#define STM32_DAC_IS_CHAN_1(ch) ((ch) & STM32_DAC_CHANNEL_1) |
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#define STM32_DAC_AUTO_SUSPEND_DELAY_MS 2000 |
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/** |
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* struct stm32_dac - private data of DAC driver |
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* @common: reference to DAC common data |
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* @lock: lock to protect against potential races when reading |
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* and update CR, to keep it in sync with pm_runtime |
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*/ |
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struct stm32_dac { |
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struct stm32_dac_common *common; |
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struct mutex lock; |
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}; |
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static int stm32_dac_is_enabled(struct iio_dev *indio_dev, int channel) |
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{ |
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struct stm32_dac *dac = iio_priv(indio_dev); |
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u32 en, val; |
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int ret; |
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ret = regmap_read(dac->common->regmap, STM32_DAC_CR, &val); |
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if (ret < 0) |
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return ret; |
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if (STM32_DAC_IS_CHAN_1(channel)) |
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en = FIELD_GET(STM32_DAC_CR_EN1, val); |
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else |
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en = FIELD_GET(STM32_DAC_CR_EN2, val); |
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return !!en; |
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} |
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static int stm32_dac_set_enable_state(struct iio_dev *indio_dev, int ch, |
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bool enable) |
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{ |
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struct stm32_dac *dac = iio_priv(indio_dev); |
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struct device *dev = indio_dev->dev.parent; |
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u32 msk = STM32_DAC_IS_CHAN_1(ch) ? STM32_DAC_CR_EN1 : STM32_DAC_CR_EN2; |
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u32 en = enable ? msk : 0; |
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int ret; |
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/* already enabled / disabled ? */ |
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mutex_lock(&dac->lock); |
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ret = stm32_dac_is_enabled(indio_dev, ch); |
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if (ret < 0 || enable == !!ret) { |
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mutex_unlock(&dac->lock); |
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return ret < 0 ? ret : 0; |
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} |
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if (enable) { |
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ret = pm_runtime_get_sync(dev); |
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if (ret < 0) { |
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pm_runtime_put_noidle(dev); |
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mutex_unlock(&dac->lock); |
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return ret; |
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} |
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} |
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ret = regmap_update_bits(dac->common->regmap, STM32_DAC_CR, msk, en); |
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mutex_unlock(&dac->lock); |
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if (ret < 0) { |
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dev_err(&indio_dev->dev, "%s failed\n", en ? |
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"Enable" : "Disable"); |
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goto err_put_pm; |
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} |
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/* |
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* When HFSEL is set, it is not allowed to write the DHRx register |
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* during 8 clock cycles after the ENx bit is set. It is not allowed |
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* to make software/hardware trigger during this period either. |
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*/ |
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if (en && dac->common->hfsel) |
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udelay(1); |
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if (!enable) { |
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pm_runtime_mark_last_busy(dev); |
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pm_runtime_put_autosuspend(dev); |
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} |
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return 0; |
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err_put_pm: |
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if (enable) { |
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pm_runtime_mark_last_busy(dev); |
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pm_runtime_put_autosuspend(dev); |
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} |
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return ret; |
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} |
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static int stm32_dac_get_value(struct stm32_dac *dac, int channel, int *val) |
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{ |
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int ret; |
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if (STM32_DAC_IS_CHAN_1(channel)) |
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ret = regmap_read(dac->common->regmap, STM32_DAC_DOR1, val); |
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else |
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ret = regmap_read(dac->common->regmap, STM32_DAC_DOR2, val); |
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return ret ? ret : IIO_VAL_INT; |
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} |
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static int stm32_dac_set_value(struct stm32_dac *dac, int channel, int val) |
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{ |
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int ret; |
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if (STM32_DAC_IS_CHAN_1(channel)) |
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ret = regmap_write(dac->common->regmap, STM32_DAC_DHR12R1, val); |
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else |
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ret = regmap_write(dac->common->regmap, STM32_DAC_DHR12R2, val); |
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return ret; |
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} |
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static int stm32_dac_read_raw(struct iio_dev *indio_dev, |
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struct iio_chan_spec const *chan, |
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int *val, int *val2, long mask) |
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{ |
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struct stm32_dac *dac = iio_priv(indio_dev); |
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switch (mask) { |
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case IIO_CHAN_INFO_RAW: |
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return stm32_dac_get_value(dac, chan->channel, val); |
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case IIO_CHAN_INFO_SCALE: |
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*val = dac->common->vref_mv; |
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*val2 = chan->scan_type.realbits; |
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return IIO_VAL_FRACTIONAL_LOG2; |
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default: |
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return -EINVAL; |
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} |
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} |
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static int stm32_dac_write_raw(struct iio_dev *indio_dev, |
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struct iio_chan_spec const *chan, |
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int val, int val2, long mask) |
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{ |
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struct stm32_dac *dac = iio_priv(indio_dev); |
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switch (mask) { |
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case IIO_CHAN_INFO_RAW: |
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return stm32_dac_set_value(dac, chan->channel, val); |
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default: |
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return -EINVAL; |
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} |
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} |
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static int stm32_dac_debugfs_reg_access(struct iio_dev *indio_dev, |
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unsigned reg, unsigned writeval, |
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unsigned *readval) |
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{ |
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struct stm32_dac *dac = iio_priv(indio_dev); |
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if (!readval) |
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return regmap_write(dac->common->regmap, reg, writeval); |
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else |
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return regmap_read(dac->common->regmap, reg, readval); |
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} |
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static const struct iio_info stm32_dac_iio_info = { |
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.read_raw = stm32_dac_read_raw, |
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.write_raw = stm32_dac_write_raw, |
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.debugfs_reg_access = stm32_dac_debugfs_reg_access, |
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}; |
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static const char * const stm32_dac_powerdown_modes[] = { |
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"three_state", |
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}; |
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static int stm32_dac_get_powerdown_mode(struct iio_dev *indio_dev, |
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const struct iio_chan_spec *chan) |
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{ |
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return 0; |
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} |
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static int stm32_dac_set_powerdown_mode(struct iio_dev *indio_dev, |
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const struct iio_chan_spec *chan, |
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unsigned int type) |
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{ |
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return 0; |
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} |
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static ssize_t stm32_dac_read_powerdown(struct iio_dev *indio_dev, |
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uintptr_t private, |
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const struct iio_chan_spec *chan, |
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char *buf) |
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{ |
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int ret = stm32_dac_is_enabled(indio_dev, chan->channel); |
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if (ret < 0) |
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return ret; |
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return sprintf(buf, "%d\n", ret ? 0 : 1); |
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} |
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static ssize_t stm32_dac_write_powerdown(struct iio_dev *indio_dev, |
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uintptr_t private, |
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const struct iio_chan_spec *chan, |
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const char *buf, size_t len) |
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{ |
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bool powerdown; |
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int ret; |
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ret = strtobool(buf, &powerdown); |
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if (ret) |
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return ret; |
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ret = stm32_dac_set_enable_state(indio_dev, chan->channel, !powerdown); |
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if (ret) |
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return ret; |
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return len; |
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} |
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static const struct iio_enum stm32_dac_powerdown_mode_en = { |
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.items = stm32_dac_powerdown_modes, |
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.num_items = ARRAY_SIZE(stm32_dac_powerdown_modes), |
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.get = stm32_dac_get_powerdown_mode, |
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.set = stm32_dac_set_powerdown_mode, |
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}; |
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static const struct iio_chan_spec_ext_info stm32_dac_ext_info[] = { |
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{ |
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.name = "powerdown", |
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.read = stm32_dac_read_powerdown, |
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.write = stm32_dac_write_powerdown, |
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.shared = IIO_SEPARATE, |
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}, |
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IIO_ENUM("powerdown_mode", IIO_SEPARATE, &stm32_dac_powerdown_mode_en), |
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IIO_ENUM_AVAILABLE("powerdown_mode", &stm32_dac_powerdown_mode_en), |
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{}, |
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}; |
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#define STM32_DAC_CHANNEL(chan, name) { \ |
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.type = IIO_VOLTAGE, \ |
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.indexed = 1, \ |
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.output = 1, \ |
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.channel = chan, \ |
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.info_mask_separate = \ |
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BIT(IIO_CHAN_INFO_RAW) | \ |
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BIT(IIO_CHAN_INFO_SCALE), \ |
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/* scan_index is always 0 as num_channels is 1 */ \ |
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.scan_type = { \ |
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.sign = 'u', \ |
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.realbits = 12, \ |
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.storagebits = 16, \ |
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}, \ |
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.datasheet_name = name, \ |
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.ext_info = stm32_dac_ext_info \ |
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} |
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static const struct iio_chan_spec stm32_dac_channels[] = { |
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STM32_DAC_CHANNEL(STM32_DAC_CHANNEL_1, "out1"), |
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STM32_DAC_CHANNEL(STM32_DAC_CHANNEL_2, "out2"), |
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}; |
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static int stm32_dac_chan_of_init(struct iio_dev *indio_dev) |
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{ |
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struct device_node *np = indio_dev->dev.of_node; |
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unsigned int i; |
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u32 channel; |
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int ret; |
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ret = of_property_read_u32(np, "reg", &channel); |
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if (ret) { |
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dev_err(&indio_dev->dev, "Failed to read reg property\n"); |
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return ret; |
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} |
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for (i = 0; i < ARRAY_SIZE(stm32_dac_channels); i++) { |
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if (stm32_dac_channels[i].channel == channel) |
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break; |
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} |
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if (i >= ARRAY_SIZE(stm32_dac_channels)) { |
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dev_err(&indio_dev->dev, "Invalid reg property\n"); |
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return -EINVAL; |
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} |
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indio_dev->channels = &stm32_dac_channels[i]; |
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/* |
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* Expose only one channel here, as they can be used independently, |
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* with separate trigger. Then separate IIO devices are instantiated |
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* to manage this. |
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*/ |
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indio_dev->num_channels = 1; |
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return 0; |
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}; |
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static int stm32_dac_probe(struct platform_device *pdev) |
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{ |
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struct device_node *np = pdev->dev.of_node; |
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struct device *dev = &pdev->dev; |
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struct iio_dev *indio_dev; |
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struct stm32_dac *dac; |
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int ret; |
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if (!np) |
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return -ENODEV; |
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indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*dac)); |
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if (!indio_dev) |
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return -ENOMEM; |
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platform_set_drvdata(pdev, indio_dev); |
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dac = iio_priv(indio_dev); |
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dac->common = dev_get_drvdata(pdev->dev.parent); |
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indio_dev->name = dev_name(&pdev->dev); |
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indio_dev->dev.of_node = pdev->dev.of_node; |
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indio_dev->info = &stm32_dac_iio_info; |
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indio_dev->modes = INDIO_DIRECT_MODE; |
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mutex_init(&dac->lock); |
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ret = stm32_dac_chan_of_init(indio_dev); |
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if (ret < 0) |
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return ret; |
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/* Get stm32-dac-core PM online */ |
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pm_runtime_get_noresume(dev); |
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pm_runtime_set_active(dev); |
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pm_runtime_set_autosuspend_delay(dev, STM32_DAC_AUTO_SUSPEND_DELAY_MS); |
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pm_runtime_use_autosuspend(dev); |
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pm_runtime_enable(dev); |
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ret = iio_device_register(indio_dev); |
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if (ret) |
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goto err_pm_put; |
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pm_runtime_mark_last_busy(dev); |
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pm_runtime_put_autosuspend(dev); |
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return 0; |
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err_pm_put: |
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pm_runtime_disable(dev); |
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pm_runtime_set_suspended(dev); |
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pm_runtime_put_noidle(dev); |
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return ret; |
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} |
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static int stm32_dac_remove(struct platform_device *pdev) |
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{ |
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struct iio_dev *indio_dev = platform_get_drvdata(pdev); |
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pm_runtime_get_sync(&pdev->dev); |
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iio_device_unregister(indio_dev); |
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pm_runtime_disable(&pdev->dev); |
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pm_runtime_set_suspended(&pdev->dev); |
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pm_runtime_put_noidle(&pdev->dev); |
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return 0; |
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} |
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static int __maybe_unused stm32_dac_suspend(struct device *dev) |
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{ |
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struct iio_dev *indio_dev = dev_get_drvdata(dev); |
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int channel = indio_dev->channels[0].channel; |
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int ret; |
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/* Ensure DAC is disabled before suspend */ |
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ret = stm32_dac_is_enabled(indio_dev, channel); |
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if (ret) |
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return ret < 0 ? ret : -EBUSY; |
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return pm_runtime_force_suspend(dev); |
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} |
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static const struct dev_pm_ops stm32_dac_pm_ops = { |
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SET_SYSTEM_SLEEP_PM_OPS(stm32_dac_suspend, pm_runtime_force_resume) |
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}; |
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static const struct of_device_id stm32_dac_of_match[] = { |
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{ .compatible = "st,stm32-dac", }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, stm32_dac_of_match); |
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static struct platform_driver stm32_dac_driver = { |
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.probe = stm32_dac_probe, |
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.remove = stm32_dac_remove, |
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.driver = { |
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.name = "stm32-dac", |
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.of_match_table = stm32_dac_of_match, |
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.pm = &stm32_dac_pm_ops, |
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}, |
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}; |
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module_platform_driver(stm32_dac_driver); |
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MODULE_ALIAS("platform:stm32-dac"); |
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MODULE_AUTHOR("Amelie Delaunay <[email protected]>"); |
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MODULE_DESCRIPTION("STMicroelectronics STM32 DAC driver"); |
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MODULE_LICENSE("GPL v2");
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