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550 lines
13 KiB
550 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Holt Integrated Circuits HI-8435 threshold detector driver |
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* |
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* Copyright (C) 2015 Zodiac Inflight Innovations |
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* Copyright (C) 2015 Cogent Embedded, Inc. |
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*/ |
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#include <linux/delay.h> |
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#include <linux/iio/events.h> |
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#include <linux/iio/iio.h> |
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#include <linux/iio/sysfs.h> |
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#include <linux/iio/trigger.h> |
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#include <linux/iio/trigger_consumer.h> |
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#include <linux/iio/triggered_event.h> |
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#include <linux/interrupt.h> |
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#include <linux/module.h> |
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#include <linux/mod_devicetable.h> |
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#include <linux/spi/spi.h> |
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#include <linux/gpio/consumer.h> |
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#define DRV_NAME "hi8435" |
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/* Register offsets for HI-8435 */ |
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#define HI8435_CTRL_REG 0x02 |
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#define HI8435_PSEN_REG 0x04 |
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#define HI8435_TMDATA_REG 0x1E |
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#define HI8435_GOCENHYS_REG 0x3A |
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#define HI8435_SOCENHYS_REG 0x3C |
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#define HI8435_SO7_0_REG 0x10 |
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#define HI8435_SO15_8_REG 0x12 |
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#define HI8435_SO23_16_REG 0x14 |
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#define HI8435_SO31_24_REG 0x16 |
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#define HI8435_SO31_0_REG 0x78 |
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#define HI8435_WRITE_OPCODE 0x00 |
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#define HI8435_READ_OPCODE 0x80 |
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/* CTRL register bits */ |
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#define HI8435_CTRL_TEST 0x01 |
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#define HI8435_CTRL_SRST 0x02 |
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struct hi8435_priv { |
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struct spi_device *spi; |
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struct mutex lock; |
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unsigned long event_scan_mask; /* soft mask/unmask channels events */ |
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unsigned int event_prev_val; |
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unsigned threshold_lo[2]; /* GND-Open and Supply-Open thresholds */ |
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unsigned threshold_hi[2]; /* GND-Open and Supply-Open thresholds */ |
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u8 reg_buffer[3] ____cacheline_aligned; |
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}; |
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static int hi8435_readb(struct hi8435_priv *priv, u8 reg, u8 *val) |
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{ |
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reg |= HI8435_READ_OPCODE; |
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return spi_write_then_read(priv->spi, ®, 1, val, 1); |
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} |
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static int hi8435_readw(struct hi8435_priv *priv, u8 reg, u16 *val) |
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{ |
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int ret; |
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__be16 be_val; |
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reg |= HI8435_READ_OPCODE; |
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ret = spi_write_then_read(priv->spi, ®, 1, &be_val, 2); |
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*val = be16_to_cpu(be_val); |
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return ret; |
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} |
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static int hi8435_readl(struct hi8435_priv *priv, u8 reg, u32 *val) |
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{ |
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int ret; |
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__be32 be_val; |
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reg |= HI8435_READ_OPCODE; |
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ret = spi_write_then_read(priv->spi, ®, 1, &be_val, 4); |
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*val = be32_to_cpu(be_val); |
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return ret; |
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} |
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static int hi8435_writeb(struct hi8435_priv *priv, u8 reg, u8 val) |
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{ |
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priv->reg_buffer[0] = reg | HI8435_WRITE_OPCODE; |
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priv->reg_buffer[1] = val; |
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return spi_write(priv->spi, priv->reg_buffer, 2); |
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} |
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static int hi8435_writew(struct hi8435_priv *priv, u8 reg, u16 val) |
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{ |
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priv->reg_buffer[0] = reg | HI8435_WRITE_OPCODE; |
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priv->reg_buffer[1] = (val >> 8) & 0xff; |
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priv->reg_buffer[2] = val & 0xff; |
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return spi_write(priv->spi, priv->reg_buffer, 3); |
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} |
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static int hi8435_read_raw(struct iio_dev *idev, |
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const struct iio_chan_spec *chan, |
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int *val, int *val2, long mask) |
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{ |
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struct hi8435_priv *priv = iio_priv(idev); |
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u32 tmp; |
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int ret; |
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switch (mask) { |
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case IIO_CHAN_INFO_RAW: |
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ret = hi8435_readl(priv, HI8435_SO31_0_REG, &tmp); |
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if (ret < 0) |
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return ret; |
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*val = !!(tmp & BIT(chan->channel)); |
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return IIO_VAL_INT; |
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default: |
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return -EINVAL; |
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} |
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} |
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static int hi8435_read_event_config(struct iio_dev *idev, |
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const struct iio_chan_spec *chan, |
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enum iio_event_type type, |
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enum iio_event_direction dir) |
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{ |
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struct hi8435_priv *priv = iio_priv(idev); |
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return !!(priv->event_scan_mask & BIT(chan->channel)); |
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} |
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static int hi8435_write_event_config(struct iio_dev *idev, |
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const struct iio_chan_spec *chan, |
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enum iio_event_type type, |
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enum iio_event_direction dir, int state) |
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{ |
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struct hi8435_priv *priv = iio_priv(idev); |
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int ret; |
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u32 tmp; |
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if (state) { |
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ret = hi8435_readl(priv, HI8435_SO31_0_REG, &tmp); |
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if (ret < 0) |
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return ret; |
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if (tmp & BIT(chan->channel)) |
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priv->event_prev_val |= BIT(chan->channel); |
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else |
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priv->event_prev_val &= ~BIT(chan->channel); |
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priv->event_scan_mask |= BIT(chan->channel); |
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} else |
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priv->event_scan_mask &= ~BIT(chan->channel); |
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return 0; |
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} |
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static int hi8435_read_event_value(struct iio_dev *idev, |
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const struct iio_chan_spec *chan, |
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enum iio_event_type type, |
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enum iio_event_direction dir, |
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enum iio_event_info info, |
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int *val, int *val2) |
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{ |
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struct hi8435_priv *priv = iio_priv(idev); |
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int ret; |
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u8 mode, psen; |
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u16 reg; |
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ret = hi8435_readb(priv, HI8435_PSEN_REG, &psen); |
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if (ret < 0) |
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return ret; |
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/* Supply-Open or GND-Open sensing mode */ |
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mode = !!(psen & BIT(chan->channel / 8)); |
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ret = hi8435_readw(priv, mode ? HI8435_SOCENHYS_REG : |
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HI8435_GOCENHYS_REG, ®); |
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if (ret < 0) |
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return ret; |
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if (dir == IIO_EV_DIR_FALLING) |
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*val = ((reg & 0xff) - (reg >> 8)) / 2; |
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else if (dir == IIO_EV_DIR_RISING) |
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*val = ((reg & 0xff) + (reg >> 8)) / 2; |
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return IIO_VAL_INT; |
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} |
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static int hi8435_write_event_value(struct iio_dev *idev, |
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const struct iio_chan_spec *chan, |
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enum iio_event_type type, |
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enum iio_event_direction dir, |
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enum iio_event_info info, |
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int val, int val2) |
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{ |
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struct hi8435_priv *priv = iio_priv(idev); |
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int ret; |
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u8 mode, psen; |
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u16 reg; |
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ret = hi8435_readb(priv, HI8435_PSEN_REG, &psen); |
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if (ret < 0) |
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return ret; |
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/* Supply-Open or GND-Open sensing mode */ |
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mode = !!(psen & BIT(chan->channel / 8)); |
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ret = hi8435_readw(priv, mode ? HI8435_SOCENHYS_REG : |
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HI8435_GOCENHYS_REG, ®); |
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if (ret < 0) |
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return ret; |
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if (dir == IIO_EV_DIR_FALLING) { |
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/* falling threshold range 2..21V, hysteresis minimum 2V */ |
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if (val < 2 || val > 21 || (val + 2) > priv->threshold_hi[mode]) |
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return -EINVAL; |
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if (val == priv->threshold_lo[mode]) |
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return 0; |
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priv->threshold_lo[mode] = val; |
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/* hysteresis must not be odd */ |
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if ((priv->threshold_hi[mode] - priv->threshold_lo[mode]) % 2) |
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priv->threshold_hi[mode]--; |
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} else if (dir == IIO_EV_DIR_RISING) { |
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/* rising threshold range 3..22V, hysteresis minimum 2V */ |
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if (val < 3 || val > 22 || val < (priv->threshold_lo[mode] + 2)) |
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return -EINVAL; |
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if (val == priv->threshold_hi[mode]) |
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return 0; |
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priv->threshold_hi[mode] = val; |
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/* hysteresis must not be odd */ |
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if ((priv->threshold_hi[mode] - priv->threshold_lo[mode]) % 2) |
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priv->threshold_lo[mode]++; |
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} |
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/* program thresholds */ |
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mutex_lock(&priv->lock); |
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ret = hi8435_readw(priv, mode ? HI8435_SOCENHYS_REG : |
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HI8435_GOCENHYS_REG, ®); |
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if (ret < 0) { |
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mutex_unlock(&priv->lock); |
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return ret; |
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} |
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/* hysteresis */ |
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reg = priv->threshold_hi[mode] - priv->threshold_lo[mode]; |
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reg <<= 8; |
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/* threshold center */ |
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reg |= (priv->threshold_hi[mode] + priv->threshold_lo[mode]); |
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ret = hi8435_writew(priv, mode ? HI8435_SOCENHYS_REG : |
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HI8435_GOCENHYS_REG, reg); |
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mutex_unlock(&priv->lock); |
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return ret; |
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} |
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static int hi8435_debugfs_reg_access(struct iio_dev *idev, |
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unsigned reg, unsigned writeval, |
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unsigned *readval) |
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{ |
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struct hi8435_priv *priv = iio_priv(idev); |
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int ret; |
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u8 val; |
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if (readval != NULL) { |
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ret = hi8435_readb(priv, reg, &val); |
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*readval = val; |
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} else { |
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val = (u8)writeval; |
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ret = hi8435_writeb(priv, reg, val); |
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} |
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return ret; |
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} |
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static const struct iio_event_spec hi8435_events[] = { |
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{ |
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.type = IIO_EV_TYPE_THRESH, |
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.dir = IIO_EV_DIR_RISING, |
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.mask_separate = BIT(IIO_EV_INFO_VALUE), |
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}, { |
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.type = IIO_EV_TYPE_THRESH, |
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.dir = IIO_EV_DIR_FALLING, |
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.mask_separate = BIT(IIO_EV_INFO_VALUE), |
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}, { |
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.type = IIO_EV_TYPE_THRESH, |
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.dir = IIO_EV_DIR_EITHER, |
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.mask_separate = BIT(IIO_EV_INFO_ENABLE), |
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}, |
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}; |
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static int hi8435_get_sensing_mode(struct iio_dev *idev, |
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const struct iio_chan_spec *chan) |
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{ |
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struct hi8435_priv *priv = iio_priv(idev); |
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int ret; |
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u8 reg; |
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ret = hi8435_readb(priv, HI8435_PSEN_REG, ®); |
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if (ret < 0) |
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return ret; |
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return !!(reg & BIT(chan->channel / 8)); |
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} |
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static int hi8435_set_sensing_mode(struct iio_dev *idev, |
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const struct iio_chan_spec *chan, |
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unsigned int mode) |
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{ |
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struct hi8435_priv *priv = iio_priv(idev); |
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int ret; |
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u8 reg; |
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mutex_lock(&priv->lock); |
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ret = hi8435_readb(priv, HI8435_PSEN_REG, ®); |
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if (ret < 0) { |
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mutex_unlock(&priv->lock); |
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return ret; |
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} |
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reg &= ~BIT(chan->channel / 8); |
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if (mode) |
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reg |= BIT(chan->channel / 8); |
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ret = hi8435_writeb(priv, HI8435_PSEN_REG, reg); |
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mutex_unlock(&priv->lock); |
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return ret; |
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} |
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static const char * const hi8435_sensing_modes[] = { "GND-Open", |
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"Supply-Open" }; |
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static const struct iio_enum hi8435_sensing_mode = { |
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.items = hi8435_sensing_modes, |
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.num_items = ARRAY_SIZE(hi8435_sensing_modes), |
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.get = hi8435_get_sensing_mode, |
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.set = hi8435_set_sensing_mode, |
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}; |
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static const struct iio_chan_spec_ext_info hi8435_ext_info[] = { |
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IIO_ENUM("sensing_mode", IIO_SEPARATE, &hi8435_sensing_mode), |
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IIO_ENUM_AVAILABLE("sensing_mode", &hi8435_sensing_mode), |
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{}, |
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}; |
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#define HI8435_VOLTAGE_CHANNEL(num) \ |
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{ \ |
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.type = IIO_VOLTAGE, \ |
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.indexed = 1, \ |
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.channel = num, \ |
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ |
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.event_spec = hi8435_events, \ |
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.num_event_specs = ARRAY_SIZE(hi8435_events), \ |
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.ext_info = hi8435_ext_info, \ |
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} |
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static const struct iio_chan_spec hi8435_channels[] = { |
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HI8435_VOLTAGE_CHANNEL(0), |
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HI8435_VOLTAGE_CHANNEL(1), |
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HI8435_VOLTAGE_CHANNEL(2), |
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HI8435_VOLTAGE_CHANNEL(3), |
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HI8435_VOLTAGE_CHANNEL(4), |
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HI8435_VOLTAGE_CHANNEL(5), |
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HI8435_VOLTAGE_CHANNEL(6), |
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HI8435_VOLTAGE_CHANNEL(7), |
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HI8435_VOLTAGE_CHANNEL(8), |
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HI8435_VOLTAGE_CHANNEL(9), |
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HI8435_VOLTAGE_CHANNEL(10), |
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HI8435_VOLTAGE_CHANNEL(11), |
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HI8435_VOLTAGE_CHANNEL(12), |
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HI8435_VOLTAGE_CHANNEL(13), |
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HI8435_VOLTAGE_CHANNEL(14), |
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HI8435_VOLTAGE_CHANNEL(15), |
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HI8435_VOLTAGE_CHANNEL(16), |
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HI8435_VOLTAGE_CHANNEL(17), |
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HI8435_VOLTAGE_CHANNEL(18), |
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HI8435_VOLTAGE_CHANNEL(19), |
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HI8435_VOLTAGE_CHANNEL(20), |
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HI8435_VOLTAGE_CHANNEL(21), |
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HI8435_VOLTAGE_CHANNEL(22), |
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HI8435_VOLTAGE_CHANNEL(23), |
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HI8435_VOLTAGE_CHANNEL(24), |
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HI8435_VOLTAGE_CHANNEL(25), |
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HI8435_VOLTAGE_CHANNEL(26), |
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HI8435_VOLTAGE_CHANNEL(27), |
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HI8435_VOLTAGE_CHANNEL(28), |
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HI8435_VOLTAGE_CHANNEL(29), |
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HI8435_VOLTAGE_CHANNEL(30), |
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HI8435_VOLTAGE_CHANNEL(31), |
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IIO_CHAN_SOFT_TIMESTAMP(32), |
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}; |
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static const struct iio_info hi8435_info = { |
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.read_raw = hi8435_read_raw, |
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.read_event_config = hi8435_read_event_config, |
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.write_event_config = hi8435_write_event_config, |
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.read_event_value = hi8435_read_event_value, |
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.write_event_value = hi8435_write_event_value, |
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.debugfs_reg_access = hi8435_debugfs_reg_access, |
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}; |
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static void hi8435_iio_push_event(struct iio_dev *idev, unsigned int val) |
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{ |
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struct hi8435_priv *priv = iio_priv(idev); |
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enum iio_event_direction dir; |
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unsigned int i; |
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unsigned int status = priv->event_prev_val ^ val; |
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if (!status) |
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return; |
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for_each_set_bit(i, &priv->event_scan_mask, 32) { |
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if (status & BIT(i)) { |
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dir = val & BIT(i) ? IIO_EV_DIR_RISING : |
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IIO_EV_DIR_FALLING; |
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iio_push_event(idev, |
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IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, i, |
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IIO_EV_TYPE_THRESH, dir), |
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iio_get_time_ns(idev)); |
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} |
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} |
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priv->event_prev_val = val; |
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} |
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static irqreturn_t hi8435_trigger_handler(int irq, void *private) |
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{ |
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struct iio_poll_func *pf = private; |
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struct iio_dev *idev = pf->indio_dev; |
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struct hi8435_priv *priv = iio_priv(idev); |
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u32 val; |
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int ret; |
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ret = hi8435_readl(priv, HI8435_SO31_0_REG, &val); |
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if (ret < 0) |
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goto err_read; |
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hi8435_iio_push_event(idev, val); |
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err_read: |
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iio_trigger_notify_done(idev->trig); |
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return IRQ_HANDLED; |
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} |
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static void hi8435_triggered_event_cleanup(void *data) |
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{ |
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iio_triggered_event_cleanup(data); |
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} |
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static int hi8435_probe(struct spi_device *spi) |
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{ |
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struct iio_dev *idev; |
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struct hi8435_priv *priv; |
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struct gpio_desc *reset_gpio; |
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int ret; |
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idev = devm_iio_device_alloc(&spi->dev, sizeof(*priv)); |
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if (!idev) |
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return -ENOMEM; |
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priv = iio_priv(idev); |
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priv->spi = spi; |
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reset_gpio = devm_gpiod_get(&spi->dev, NULL, GPIOD_OUT_LOW); |
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if (IS_ERR(reset_gpio)) { |
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/* chip s/w reset if h/w reset failed */ |
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hi8435_writeb(priv, HI8435_CTRL_REG, HI8435_CTRL_SRST); |
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hi8435_writeb(priv, HI8435_CTRL_REG, 0); |
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} else { |
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udelay(5); |
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gpiod_set_value_cansleep(reset_gpio, 1); |
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} |
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spi_set_drvdata(spi, idev); |
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mutex_init(&priv->lock); |
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idev->name = spi_get_device_id(spi)->name; |
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idev->modes = INDIO_DIRECT_MODE; |
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idev->info = &hi8435_info; |
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idev->channels = hi8435_channels; |
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idev->num_channels = ARRAY_SIZE(hi8435_channels); |
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|
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/* unmask all events */ |
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priv->event_scan_mask = ~(0); |
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/* |
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* There is a restriction in the chip - the hysteresis can not be odd. |
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* If the hysteresis is set to odd value then chip gets into lock state |
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* and not functional anymore. |
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* After chip reset the thresholds are in undefined state, so we need to |
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* initialize thresholds to some initial values and then prevent |
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* userspace setting odd hysteresis. |
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* |
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* Set threshold low voltage to 2V, threshold high voltage to 4V |
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* for both GND-Open and Supply-Open sensing modes. |
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*/ |
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priv->threshold_lo[0] = priv->threshold_lo[1] = 2; |
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priv->threshold_hi[0] = priv->threshold_hi[1] = 4; |
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hi8435_writew(priv, HI8435_GOCENHYS_REG, 0x206); |
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hi8435_writew(priv, HI8435_SOCENHYS_REG, 0x206); |
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ret = iio_triggered_event_setup(idev, NULL, hi8435_trigger_handler); |
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if (ret) |
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return ret; |
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ret = devm_add_action_or_reset(&spi->dev, |
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hi8435_triggered_event_cleanup, |
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idev); |
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if (ret) |
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return ret; |
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return devm_iio_device_register(&spi->dev, idev); |
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} |
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static const struct of_device_id hi8435_dt_ids[] = { |
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{ .compatible = "holt,hi8435" }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, hi8435_dt_ids); |
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|
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static const struct spi_device_id hi8435_id[] = { |
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{ "hi8435", 0}, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(spi, hi8435_id); |
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static struct spi_driver hi8435_driver = { |
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.driver = { |
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.name = DRV_NAME, |
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.of_match_table = hi8435_dt_ids, |
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}, |
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.probe = hi8435_probe, |
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.id_table = hi8435_id, |
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}; |
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module_spi_driver(hi8435_driver); |
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|
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MODULE_LICENSE("GPL"); |
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MODULE_AUTHOR("Vladimir Barinov"); |
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MODULE_DESCRIPTION("HI-8435 threshold detector");
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