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710 lines
17 KiB
710 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Driver for the Diolan DLN-2 USB-ADC adapter |
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* |
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* Copyright (c) 2017 Jack Andersen |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/types.h> |
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#include <linux/platform_device.h> |
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#include <linux/mfd/dln2.h> |
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#include <linux/iio/iio.h> |
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#include <linux/iio/sysfs.h> |
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#include <linux/iio/trigger.h> |
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#include <linux/iio/trigger_consumer.h> |
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#include <linux/iio/triggered_buffer.h> |
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#include <linux/iio/buffer.h> |
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#include <linux/iio/kfifo_buf.h> |
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#define DLN2_ADC_MOD_NAME "dln2-adc" |
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#define DLN2_ADC_ID 0x06 |
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#define DLN2_ADC_GET_CHANNEL_COUNT DLN2_CMD(0x01, DLN2_ADC_ID) |
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#define DLN2_ADC_ENABLE DLN2_CMD(0x02, DLN2_ADC_ID) |
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#define DLN2_ADC_DISABLE DLN2_CMD(0x03, DLN2_ADC_ID) |
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#define DLN2_ADC_CHANNEL_ENABLE DLN2_CMD(0x05, DLN2_ADC_ID) |
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#define DLN2_ADC_CHANNEL_DISABLE DLN2_CMD(0x06, DLN2_ADC_ID) |
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#define DLN2_ADC_SET_RESOLUTION DLN2_CMD(0x08, DLN2_ADC_ID) |
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#define DLN2_ADC_CHANNEL_GET_VAL DLN2_CMD(0x0A, DLN2_ADC_ID) |
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#define DLN2_ADC_CHANNEL_GET_ALL_VAL DLN2_CMD(0x0B, DLN2_ADC_ID) |
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#define DLN2_ADC_CHANNEL_SET_CFG DLN2_CMD(0x0C, DLN2_ADC_ID) |
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#define DLN2_ADC_CHANNEL_GET_CFG DLN2_CMD(0x0D, DLN2_ADC_ID) |
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#define DLN2_ADC_CONDITION_MET_EV DLN2_CMD(0x10, DLN2_ADC_ID) |
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#define DLN2_ADC_EVENT_NONE 0 |
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#define DLN2_ADC_EVENT_BELOW 1 |
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#define DLN2_ADC_EVENT_LEVEL_ABOVE 2 |
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#define DLN2_ADC_EVENT_OUTSIDE 3 |
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#define DLN2_ADC_EVENT_INSIDE 4 |
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#define DLN2_ADC_EVENT_ALWAYS 5 |
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#define DLN2_ADC_MAX_CHANNELS 8 |
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#define DLN2_ADC_DATA_BITS 10 |
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/* |
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* Plays similar role to iio_demux_table in subsystem core; except allocated |
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* in a fixed 8-element array. |
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*/ |
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struct dln2_adc_demux_table { |
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unsigned int from; |
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unsigned int to; |
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unsigned int length; |
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}; |
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struct dln2_adc { |
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struct platform_device *pdev; |
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struct iio_chan_spec iio_channels[DLN2_ADC_MAX_CHANNELS + 1]; |
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int port, trigger_chan; |
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struct iio_trigger *trig; |
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struct mutex mutex; |
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/* Cached sample period in milliseconds */ |
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unsigned int sample_period; |
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/* Demux table */ |
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unsigned int demux_count; |
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struct dln2_adc_demux_table demux[DLN2_ADC_MAX_CHANNELS]; |
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/* Precomputed timestamp padding offset and length */ |
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unsigned int ts_pad_offset, ts_pad_length; |
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}; |
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struct dln2_adc_port_chan { |
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u8 port; |
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u8 chan; |
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}; |
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struct dln2_adc_get_all_vals { |
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__le16 channel_mask; |
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__le16 values[DLN2_ADC_MAX_CHANNELS]; |
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}; |
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static void dln2_adc_add_demux(struct dln2_adc *dln2, |
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unsigned int in_loc, unsigned int out_loc, |
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unsigned int length) |
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{ |
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struct dln2_adc_demux_table *p = dln2->demux_count ? |
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&dln2->demux[dln2->demux_count - 1] : NULL; |
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if (p && p->from + p->length == in_loc && |
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p->to + p->length == out_loc) { |
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p->length += length; |
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} else if (dln2->demux_count < DLN2_ADC_MAX_CHANNELS) { |
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p = &dln2->demux[dln2->demux_count++]; |
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p->from = in_loc; |
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p->to = out_loc; |
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p->length = length; |
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} |
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} |
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static void dln2_adc_update_demux(struct dln2_adc *dln2) |
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{ |
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int in_ind = -1, out_ind; |
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unsigned int in_loc = 0, out_loc = 0; |
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struct iio_dev *indio_dev = platform_get_drvdata(dln2->pdev); |
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/* Clear out any old demux */ |
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dln2->demux_count = 0; |
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/* Optimize all 8-channels case */ |
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if (indio_dev->masklength && |
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(*indio_dev->active_scan_mask & 0xff) == 0xff) { |
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dln2_adc_add_demux(dln2, 0, 0, 16); |
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dln2->ts_pad_offset = 0; |
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dln2->ts_pad_length = 0; |
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return; |
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} |
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/* Build demux table from fixed 8-channels to active_scan_mask */ |
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for_each_set_bit(out_ind, |
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indio_dev->active_scan_mask, |
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indio_dev->masklength) { |
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/* Handle timestamp separately */ |
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if (out_ind == DLN2_ADC_MAX_CHANNELS) |
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break; |
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for (++in_ind; in_ind != out_ind; ++in_ind) |
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in_loc += 2; |
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dln2_adc_add_demux(dln2, in_loc, out_loc, 2); |
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out_loc += 2; |
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in_loc += 2; |
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} |
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if (indio_dev->scan_timestamp) { |
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size_t ts_offset = indio_dev->scan_bytes / sizeof(int64_t) - 1; |
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dln2->ts_pad_offset = out_loc; |
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dln2->ts_pad_length = ts_offset * sizeof(int64_t) - out_loc; |
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} else { |
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dln2->ts_pad_offset = 0; |
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dln2->ts_pad_length = 0; |
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} |
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} |
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static int dln2_adc_get_chan_count(struct dln2_adc *dln2) |
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{ |
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int ret; |
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u8 port = dln2->port; |
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u8 count; |
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int olen = sizeof(count); |
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ret = dln2_transfer(dln2->pdev, DLN2_ADC_GET_CHANNEL_COUNT, |
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&port, sizeof(port), &count, &olen); |
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if (ret < 0) { |
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dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__); |
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return ret; |
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} |
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if (olen < sizeof(count)) |
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return -EPROTO; |
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return count; |
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} |
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static int dln2_adc_set_port_resolution(struct dln2_adc *dln2) |
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{ |
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int ret; |
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struct dln2_adc_port_chan port_chan = { |
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.port = dln2->port, |
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.chan = DLN2_ADC_DATA_BITS, |
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}; |
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ret = dln2_transfer_tx(dln2->pdev, DLN2_ADC_SET_RESOLUTION, |
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&port_chan, sizeof(port_chan)); |
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if (ret < 0) |
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dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__); |
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return ret; |
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} |
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static int dln2_adc_set_chan_enabled(struct dln2_adc *dln2, |
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int channel, bool enable) |
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{ |
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int ret; |
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struct dln2_adc_port_chan port_chan = { |
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.port = dln2->port, |
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.chan = channel, |
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}; |
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u16 cmd = enable ? DLN2_ADC_CHANNEL_ENABLE : DLN2_ADC_CHANNEL_DISABLE; |
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ret = dln2_transfer_tx(dln2->pdev, cmd, &port_chan, sizeof(port_chan)); |
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if (ret < 0) |
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dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__); |
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return ret; |
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} |
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static int dln2_adc_set_port_enabled(struct dln2_adc *dln2, bool enable, |
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u16 *conflict_out) |
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{ |
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int ret; |
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u8 port = dln2->port; |
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__le16 conflict; |
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int olen = sizeof(conflict); |
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u16 cmd = enable ? DLN2_ADC_ENABLE : DLN2_ADC_DISABLE; |
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if (conflict_out) |
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*conflict_out = 0; |
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ret = dln2_transfer(dln2->pdev, cmd, &port, sizeof(port), |
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&conflict, &olen); |
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if (ret < 0) { |
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dev_dbg(&dln2->pdev->dev, "Problem in %s(%d)\n", |
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__func__, (int)enable); |
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if (conflict_out && enable && olen >= sizeof(conflict)) |
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*conflict_out = le16_to_cpu(conflict); |
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return ret; |
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} |
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if (enable && olen < sizeof(conflict)) |
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return -EPROTO; |
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return ret; |
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} |
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static int dln2_adc_set_chan_period(struct dln2_adc *dln2, |
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unsigned int channel, unsigned int period) |
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{ |
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int ret; |
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struct { |
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struct dln2_adc_port_chan port_chan; |
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__u8 type; |
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__le16 period; |
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__le16 low; |
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__le16 high; |
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} __packed set_cfg = { |
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.port_chan.port = dln2->port, |
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.port_chan.chan = channel, |
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.type = period ? DLN2_ADC_EVENT_ALWAYS : DLN2_ADC_EVENT_NONE, |
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.period = cpu_to_le16(period) |
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}; |
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ret = dln2_transfer_tx(dln2->pdev, DLN2_ADC_CHANNEL_SET_CFG, |
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&set_cfg, sizeof(set_cfg)); |
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if (ret < 0) |
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dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__); |
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return ret; |
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} |
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static int dln2_adc_read(struct dln2_adc *dln2, unsigned int channel) |
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{ |
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int ret, i; |
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struct iio_dev *indio_dev = platform_get_drvdata(dln2->pdev); |
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u16 conflict; |
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__le16 value; |
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int olen = sizeof(value); |
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struct dln2_adc_port_chan port_chan = { |
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.port = dln2->port, |
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.chan = channel, |
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}; |
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ret = iio_device_claim_direct_mode(indio_dev); |
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if (ret < 0) |
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return ret; |
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ret = dln2_adc_set_chan_enabled(dln2, channel, true); |
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if (ret < 0) |
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goto release_direct; |
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ret = dln2_adc_set_port_enabled(dln2, true, &conflict); |
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if (ret < 0) { |
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if (conflict) { |
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dev_err(&dln2->pdev->dev, |
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"ADC pins conflict with mask %04X\n", |
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(int)conflict); |
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ret = -EBUSY; |
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} |
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goto disable_chan; |
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} |
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/* |
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* Call GET_VAL twice due to initial zero-return immediately after |
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* enabling channel. |
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*/ |
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for (i = 0; i < 2; ++i) { |
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ret = dln2_transfer(dln2->pdev, DLN2_ADC_CHANNEL_GET_VAL, |
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&port_chan, sizeof(port_chan), |
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&value, &olen); |
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if (ret < 0) { |
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dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__); |
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goto disable_port; |
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} |
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if (olen < sizeof(value)) { |
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ret = -EPROTO; |
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goto disable_port; |
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} |
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} |
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ret = le16_to_cpu(value); |
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disable_port: |
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dln2_adc_set_port_enabled(dln2, false, NULL); |
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disable_chan: |
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dln2_adc_set_chan_enabled(dln2, channel, false); |
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release_direct: |
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iio_device_release_direct_mode(indio_dev); |
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return ret; |
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} |
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static int dln2_adc_read_all(struct dln2_adc *dln2, |
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struct dln2_adc_get_all_vals *get_all_vals) |
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{ |
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int ret; |
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__u8 port = dln2->port; |
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int olen = sizeof(*get_all_vals); |
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ret = dln2_transfer(dln2->pdev, DLN2_ADC_CHANNEL_GET_ALL_VAL, |
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&port, sizeof(port), get_all_vals, &olen); |
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if (ret < 0) { |
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dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__); |
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return ret; |
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} |
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if (olen < sizeof(*get_all_vals)) |
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return -EPROTO; |
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return ret; |
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} |
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static int dln2_adc_read_raw(struct iio_dev *indio_dev, |
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struct iio_chan_spec const *chan, |
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int *val, |
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int *val2, |
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long mask) |
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{ |
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int ret; |
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unsigned int microhertz; |
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struct dln2_adc *dln2 = iio_priv(indio_dev); |
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switch (mask) { |
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case IIO_CHAN_INFO_RAW: |
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mutex_lock(&dln2->mutex); |
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ret = dln2_adc_read(dln2, chan->channel); |
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mutex_unlock(&dln2->mutex); |
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if (ret < 0) |
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return ret; |
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*val = ret; |
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return IIO_VAL_INT; |
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case IIO_CHAN_INFO_SCALE: |
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/* |
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* Voltage reference is fixed at 3.3v |
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* 3.3 / (1 << 10) * 1000000000 |
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*/ |
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*val = 0; |
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*val2 = 3222656; |
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return IIO_VAL_INT_PLUS_NANO; |
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case IIO_CHAN_INFO_SAMP_FREQ: |
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if (dln2->sample_period) { |
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microhertz = 1000000000 / dln2->sample_period; |
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*val = microhertz / 1000000; |
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*val2 = microhertz % 1000000; |
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} else { |
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*val = 0; |
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*val2 = 0; |
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} |
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return IIO_VAL_INT_PLUS_MICRO; |
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default: |
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return -EINVAL; |
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} |
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} |
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static int dln2_adc_write_raw(struct iio_dev *indio_dev, |
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struct iio_chan_spec const *chan, |
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int val, |
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int val2, |
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long mask) |
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{ |
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int ret; |
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unsigned int microhertz; |
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struct dln2_adc *dln2 = iio_priv(indio_dev); |
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switch (mask) { |
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case IIO_CHAN_INFO_SAMP_FREQ: |
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microhertz = 1000000 * val + val2; |
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mutex_lock(&dln2->mutex); |
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dln2->sample_period = |
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microhertz ? 1000000000 / microhertz : UINT_MAX; |
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if (dln2->sample_period > 65535) { |
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dln2->sample_period = 65535; |
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dev_warn(&dln2->pdev->dev, |
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"clamping period to 65535ms\n"); |
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} |
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/* |
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* The first requested channel is arbitrated as a shared |
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* trigger source, so only one event is registered with the |
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* DLN. The event handler will then read all enabled channel |
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* values using DLN2_ADC_CHANNEL_GET_ALL_VAL to maintain |
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* synchronization between ADC readings. |
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*/ |
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if (dln2->trigger_chan != -1) |
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ret = dln2_adc_set_chan_period(dln2, |
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dln2->trigger_chan, dln2->sample_period); |
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else |
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ret = 0; |
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mutex_unlock(&dln2->mutex); |
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return ret; |
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default: |
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return -EINVAL; |
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} |
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} |
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static int dln2_update_scan_mode(struct iio_dev *indio_dev, |
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const unsigned long *scan_mask) |
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{ |
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struct dln2_adc *dln2 = iio_priv(indio_dev); |
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int chan_count = indio_dev->num_channels - 1; |
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int ret, i, j; |
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mutex_lock(&dln2->mutex); |
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for (i = 0; i < chan_count; ++i) { |
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ret = dln2_adc_set_chan_enabled(dln2, i, |
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test_bit(i, scan_mask)); |
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if (ret < 0) { |
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for (j = 0; j < i; ++j) |
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dln2_adc_set_chan_enabled(dln2, j, false); |
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mutex_unlock(&dln2->mutex); |
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dev_err(&dln2->pdev->dev, |
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"Unable to enable ADC channel %d\n", i); |
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return -EBUSY; |
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} |
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} |
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dln2_adc_update_demux(dln2); |
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mutex_unlock(&dln2->mutex); |
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return 0; |
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} |
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#define DLN2_ADC_CHAN(lval, idx) { \ |
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lval.type = IIO_VOLTAGE; \ |
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lval.channel = idx; \ |
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lval.indexed = 1; \ |
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lval.info_mask_separate = BIT(IIO_CHAN_INFO_RAW); \ |
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lval.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) | \ |
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BIT(IIO_CHAN_INFO_SAMP_FREQ); \ |
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lval.scan_index = idx; \ |
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lval.scan_type.sign = 'u'; \ |
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lval.scan_type.realbits = DLN2_ADC_DATA_BITS; \ |
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lval.scan_type.storagebits = 16; \ |
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lval.scan_type.endianness = IIO_LE; \ |
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} |
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/* Assignment version of IIO_CHAN_SOFT_TIMESTAMP */ |
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#define IIO_CHAN_SOFT_TIMESTAMP_ASSIGN(lval, _si) { \ |
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lval.type = IIO_TIMESTAMP; \ |
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lval.channel = -1; \ |
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lval.scan_index = _si; \ |
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lval.scan_type.sign = 's'; \ |
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lval.scan_type.realbits = 64; \ |
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lval.scan_type.storagebits = 64; \ |
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} |
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static const struct iio_info dln2_adc_info = { |
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.read_raw = dln2_adc_read_raw, |
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.write_raw = dln2_adc_write_raw, |
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.update_scan_mode = dln2_update_scan_mode, |
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}; |
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static irqreturn_t dln2_adc_trigger_h(int irq, void *p) |
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{ |
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struct iio_poll_func *pf = p; |
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struct iio_dev *indio_dev = pf->indio_dev; |
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struct { |
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__le16 values[DLN2_ADC_MAX_CHANNELS]; |
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int64_t timestamp_space; |
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} data; |
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struct dln2_adc_get_all_vals dev_data; |
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struct dln2_adc *dln2 = iio_priv(indio_dev); |
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const struct dln2_adc_demux_table *t; |
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int ret, i; |
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mutex_lock(&dln2->mutex); |
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ret = dln2_adc_read_all(dln2, &dev_data); |
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mutex_unlock(&dln2->mutex); |
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if (ret < 0) |
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goto done; |
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/* Demux operation */ |
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for (i = 0; i < dln2->demux_count; ++i) { |
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t = &dln2->demux[i]; |
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memcpy((void *)data.values + t->to, |
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(void *)dev_data.values + t->from, t->length); |
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} |
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/* Zero padding space between values and timestamp */ |
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if (dln2->ts_pad_length) |
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memset((void *)data.values + dln2->ts_pad_offset, |
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0, dln2->ts_pad_length); |
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iio_push_to_buffers_with_timestamp(indio_dev, &data, |
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iio_get_time_ns(indio_dev)); |
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done: |
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iio_trigger_notify_done(indio_dev->trig); |
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return IRQ_HANDLED; |
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} |
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static int dln2_adc_triggered_buffer_postenable(struct iio_dev *indio_dev) |
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{ |
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int ret; |
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struct dln2_adc *dln2 = iio_priv(indio_dev); |
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u16 conflict; |
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unsigned int trigger_chan; |
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mutex_lock(&dln2->mutex); |
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/* Enable ADC */ |
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ret = dln2_adc_set_port_enabled(dln2, true, &conflict); |
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if (ret < 0) { |
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mutex_unlock(&dln2->mutex); |
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dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__); |
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if (conflict) { |
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dev_err(&dln2->pdev->dev, |
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"ADC pins conflict with mask %04X\n", |
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(int)conflict); |
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ret = -EBUSY; |
|
} |
|
return ret; |
|
} |
|
|
|
/* Assign trigger channel based on first enabled channel */ |
|
trigger_chan = find_first_bit(indio_dev->active_scan_mask, |
|
indio_dev->masklength); |
|
if (trigger_chan < DLN2_ADC_MAX_CHANNELS) { |
|
dln2->trigger_chan = trigger_chan; |
|
ret = dln2_adc_set_chan_period(dln2, dln2->trigger_chan, |
|
dln2->sample_period); |
|
mutex_unlock(&dln2->mutex); |
|
if (ret < 0) { |
|
dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__); |
|
return ret; |
|
} |
|
} else { |
|
dln2->trigger_chan = -1; |
|
mutex_unlock(&dln2->mutex); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int dln2_adc_triggered_buffer_predisable(struct iio_dev *indio_dev) |
|
{ |
|
int ret; |
|
struct dln2_adc *dln2 = iio_priv(indio_dev); |
|
|
|
mutex_lock(&dln2->mutex); |
|
|
|
/* Disable trigger channel */ |
|
if (dln2->trigger_chan != -1) { |
|
dln2_adc_set_chan_period(dln2, dln2->trigger_chan, 0); |
|
dln2->trigger_chan = -1; |
|
} |
|
|
|
/* Disable ADC */ |
|
ret = dln2_adc_set_port_enabled(dln2, false, NULL); |
|
|
|
mutex_unlock(&dln2->mutex); |
|
if (ret < 0) |
|
dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__); |
|
|
|
return ret; |
|
} |
|
|
|
static const struct iio_buffer_setup_ops dln2_adc_buffer_setup_ops = { |
|
.postenable = dln2_adc_triggered_buffer_postenable, |
|
.predisable = dln2_adc_triggered_buffer_predisable, |
|
}; |
|
|
|
static void dln2_adc_event(struct platform_device *pdev, u16 echo, |
|
const void *data, int len) |
|
{ |
|
struct iio_dev *indio_dev = platform_get_drvdata(pdev); |
|
struct dln2_adc *dln2 = iio_priv(indio_dev); |
|
|
|
/* Called via URB completion handler */ |
|
iio_trigger_poll(dln2->trig); |
|
} |
|
|
|
static int dln2_adc_probe(struct platform_device *pdev) |
|
{ |
|
struct device *dev = &pdev->dev; |
|
struct dln2_adc *dln2; |
|
struct dln2_platform_data *pdata = dev_get_platdata(&pdev->dev); |
|
struct iio_dev *indio_dev; |
|
int i, ret, chans; |
|
|
|
indio_dev = devm_iio_device_alloc(dev, sizeof(*dln2)); |
|
if (!indio_dev) { |
|
dev_err(dev, "failed allocating iio device\n"); |
|
return -ENOMEM; |
|
} |
|
|
|
dln2 = iio_priv(indio_dev); |
|
dln2->pdev = pdev; |
|
dln2->port = pdata->port; |
|
dln2->trigger_chan = -1; |
|
mutex_init(&dln2->mutex); |
|
|
|
platform_set_drvdata(pdev, indio_dev); |
|
|
|
ret = dln2_adc_set_port_resolution(dln2); |
|
if (ret < 0) { |
|
dev_err(dev, "failed to set ADC resolution to 10 bits\n"); |
|
return ret; |
|
} |
|
|
|
chans = dln2_adc_get_chan_count(dln2); |
|
if (chans < 0) { |
|
dev_err(dev, "failed to get channel count: %d\n", chans); |
|
return chans; |
|
} |
|
if (chans > DLN2_ADC_MAX_CHANNELS) { |
|
chans = DLN2_ADC_MAX_CHANNELS; |
|
dev_warn(dev, "clamping channels to %d\n", |
|
DLN2_ADC_MAX_CHANNELS); |
|
} |
|
|
|
for (i = 0; i < chans; ++i) |
|
DLN2_ADC_CHAN(dln2->iio_channels[i], i) |
|
IIO_CHAN_SOFT_TIMESTAMP_ASSIGN(dln2->iio_channels[i], i); |
|
|
|
indio_dev->name = DLN2_ADC_MOD_NAME; |
|
indio_dev->info = &dln2_adc_info; |
|
indio_dev->modes = INDIO_DIRECT_MODE; |
|
indio_dev->channels = dln2->iio_channels; |
|
indio_dev->num_channels = chans + 1; |
|
indio_dev->setup_ops = &dln2_adc_buffer_setup_ops; |
|
|
|
dln2->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", |
|
indio_dev->name, indio_dev->id); |
|
if (!dln2->trig) { |
|
dev_err(dev, "failed to allocate trigger\n"); |
|
return -ENOMEM; |
|
} |
|
iio_trigger_set_drvdata(dln2->trig, dln2); |
|
devm_iio_trigger_register(dev, dln2->trig); |
|
iio_trigger_set_immutable(indio_dev, dln2->trig); |
|
|
|
ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, |
|
dln2_adc_trigger_h, |
|
&dln2_adc_buffer_setup_ops); |
|
if (ret) { |
|
dev_err(dev, "failed to allocate triggered buffer: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
ret = dln2_register_event_cb(pdev, DLN2_ADC_CONDITION_MET_EV, |
|
dln2_adc_event); |
|
if (ret) { |
|
dev_err(dev, "failed to setup DLN2 periodic event: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
ret = iio_device_register(indio_dev); |
|
if (ret) { |
|
dev_err(dev, "failed to register iio device: %d\n", ret); |
|
goto unregister_event; |
|
} |
|
|
|
return ret; |
|
|
|
unregister_event: |
|
dln2_unregister_event_cb(pdev, DLN2_ADC_CONDITION_MET_EV); |
|
|
|
return ret; |
|
} |
|
|
|
static int dln2_adc_remove(struct platform_device *pdev) |
|
{ |
|
struct iio_dev *indio_dev = platform_get_drvdata(pdev); |
|
|
|
iio_device_unregister(indio_dev); |
|
dln2_unregister_event_cb(pdev, DLN2_ADC_CONDITION_MET_EV); |
|
return 0; |
|
} |
|
|
|
static struct platform_driver dln2_adc_driver = { |
|
.driver.name = DLN2_ADC_MOD_NAME, |
|
.probe = dln2_adc_probe, |
|
.remove = dln2_adc_remove, |
|
}; |
|
|
|
module_platform_driver(dln2_adc_driver); |
|
|
|
MODULE_AUTHOR("Jack Andersen <[email protected]"); |
|
MODULE_DESCRIPTION("Driver for the Diolan DLN2 ADC interface"); |
|
MODULE_LICENSE("GPL v2"); |
|
MODULE_ALIAS("platform:dln2-adc");
|
|
|