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125 lines
4.0 KiB
125 lines
4.0 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/** |
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* Copyright (C) ST-Ericsson SA 2010 |
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* Author: Shujuan Chen <[email protected]> for ST-Ericsson. |
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* Author: Jonas Linde <[email protected]> for ST-Ericsson. |
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* Author: Joakim Bech <[email protected]> for ST-Ericsson. |
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* Author: Berne Hebark <[email protected]> for ST-Ericsson. |
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* Author: Niklas Hernaeus <[email protected]> for ST-Ericsson. |
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*/ |
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#ifndef __CRYP_IRQP_H_ |
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#define __CRYP_IRQP_H_ |
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#include "cryp_irq.h" |
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/** |
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* |
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* CRYP Registers - Offset mapping |
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* +-----------------+ |
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* 00h | CRYP_CR | Configuration register |
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* +-----------------+ |
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* 04h | CRYP_SR | Status register |
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* +-----------------+ |
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* 08h | CRYP_DIN | Data In register |
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* +-----------------+ |
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* 0ch | CRYP_DOUT | Data out register |
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* +-----------------+ |
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* 10h | CRYP_DMACR | DMA control register |
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* +-----------------+ |
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* 14h | CRYP_IMSC | IMSC |
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* +-----------------+ |
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* 18h | CRYP_RIS | Raw interrupt status |
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* +-----------------+ |
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* 1ch | CRYP_MIS | Masked interrupt status. |
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* +-----------------+ |
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* Key registers |
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* IVR registers |
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* Peripheral |
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* Cell IDs |
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* |
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* Refer data structure for other register map |
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*/ |
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/** |
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* struct cryp_register |
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* @cr - Configuration register |
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* @status - Status register |
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* @din - Data input register |
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* @din_size - Data input size register |
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* @dout - Data output register |
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* @dout_size - Data output size register |
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* @dmacr - Dma control register |
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* @imsc - Interrupt mask set/clear register |
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* @ris - Raw interrupt status |
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* @mis - Masked interrupt statu register |
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* @key_1_l - Key register 1 L |
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* @key_1_r - Key register 1 R |
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* @key_2_l - Key register 2 L |
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* @key_2_r - Key register 2 R |
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* @key_3_l - Key register 3 L |
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* @key_3_r - Key register 3 R |
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* @key_4_l - Key register 4 L |
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* @key_4_r - Key register 4 R |
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* @init_vect_0_l - init vector 0 L |
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* @init_vect_0_r - init vector 0 R |
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* @init_vect_1_l - init vector 1 L |
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* @init_vect_1_r - init vector 1 R |
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* @cryp_unused1 - unused registers |
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* @itcr - Integration test control register |
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* @itip - Integration test input register |
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* @itop - Integration test output register |
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* @cryp_unused2 - unused registers |
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* @periphId0 - FE0 CRYP Peripheral Identication Register |
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* @periphId1 - FE4 |
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* @periphId2 - FE8 |
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* @periphId3 - FEC |
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* @pcellId0 - FF0 CRYP PCell Identication Register |
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* @pcellId1 - FF4 |
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* @pcellId2 - FF8 |
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* @pcellId3 - FFC |
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*/ |
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struct cryp_register { |
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u32 cr; /* Configuration register */ |
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u32 sr; /* Status register */ |
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u32 din; /* Data input register */ |
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u32 din_size; /* Data input size register */ |
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u32 dout; /* Data output register */ |
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u32 dout_size; /* Data output size register */ |
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u32 dmacr; /* Dma control register */ |
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u32 imsc; /* Interrupt mask set/clear register */ |
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u32 ris; /* Raw interrupt status */ |
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u32 mis; /* Masked interrupt statu register */ |
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u32 key_1_l; /*Key register 1 L */ |
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u32 key_1_r; /*Key register 1 R */ |
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u32 key_2_l; /*Key register 2 L */ |
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u32 key_2_r; /*Key register 2 R */ |
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u32 key_3_l; /*Key register 3 L */ |
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u32 key_3_r; /*Key register 3 R */ |
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u32 key_4_l; /*Key register 4 L */ |
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u32 key_4_r; /*Key register 4 R */ |
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u32 init_vect_0_l; /*init vector 0 L */ |
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u32 init_vect_0_r; /*init vector 0 R */ |
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u32 init_vect_1_l; /*init vector 1 L */ |
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u32 init_vect_1_r; /*init vector 1 R */ |
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u32 cryp_unused1[(0x80 - 0x58) / sizeof(u32)]; /* unused registers */ |
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u32 itcr; /*Integration test control register */ |
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u32 itip; /*Integration test input register */ |
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u32 itop; /*Integration test output register */ |
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u32 cryp_unused2[(0xFE0 - 0x8C) / sizeof(u32)]; /* unused registers */ |
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u32 periphId0; /* FE0 CRYP Peripheral Identication Register */ |
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u32 periphId1; /* FE4 */ |
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u32 periphId2; /* FE8 */ |
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u32 periphId3; /* FEC */ |
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u32 pcellId0; /* FF0 CRYP PCell Identication Register */ |
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u32 pcellId1; /* FF4 */ |
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u32 pcellId2; /* FF8 */ |
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u32 pcellId3; /* FFC */ |
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}; |
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#endif
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