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545 lines
15 KiB
545 lines
15 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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// |
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// Copyright(c) 2020 Intel Corporation. All rights reserved. |
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// |
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// Author: Cezary Rojewski <[email protected]> |
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// |
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#include <linux/devcoredump.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/firmware.h> |
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#include <linux/pci.h> |
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#include <linux/pxa2xx_ssp.h> |
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#include "core.h" |
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#include "messages.h" |
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#include "registers.h" |
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static bool catpt_dma_filter(struct dma_chan *chan, void *param) |
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{ |
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return param == chan->device->dev; |
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} |
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/* |
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* Either engine 0 or 1 can be used for image loading. |
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* Align with Windows driver equivalent and stick to engine 1. |
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*/ |
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#define CATPT_DMA_DEVID 1 |
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#define CATPT_DMA_DSP_ADDR_MASK GENMASK(31, 20) |
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struct dma_chan *catpt_dma_request_config_chan(struct catpt_dev *cdev) |
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{ |
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struct dma_slave_config config; |
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struct dma_chan *chan; |
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dma_cap_mask_t mask; |
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int ret; |
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dma_cap_zero(mask); |
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dma_cap_set(DMA_MEMCPY, mask); |
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chan = dma_request_channel(mask, catpt_dma_filter, cdev->dev); |
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if (!chan) { |
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dev_err(cdev->dev, "request channel failed\n"); |
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return ERR_PTR(-ENODEV); |
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} |
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memset(&config, 0, sizeof(config)); |
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config.direction = DMA_MEM_TO_DEV; |
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config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
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config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
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config.src_maxburst = 16; |
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config.dst_maxburst = 16; |
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ret = dmaengine_slave_config(chan, &config); |
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if (ret) { |
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dev_err(cdev->dev, "slave config failed: %d\n", ret); |
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dma_release_channel(chan); |
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return ERR_PTR(ret); |
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} |
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return chan; |
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} |
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static int catpt_dma_memcpy(struct catpt_dev *cdev, struct dma_chan *chan, |
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dma_addr_t dst_addr, dma_addr_t src_addr, |
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size_t size) |
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{ |
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struct dma_async_tx_descriptor *desc; |
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enum dma_status status; |
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int ret; |
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desc = dmaengine_prep_dma_memcpy(chan, dst_addr, src_addr, size, |
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DMA_CTRL_ACK); |
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if (!desc) { |
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dev_err(cdev->dev, "prep dma memcpy failed\n"); |
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return -EIO; |
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} |
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/* enable demand mode for dma channel */ |
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catpt_updatel_shim(cdev, HMDC, |
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CATPT_HMDC_HDDA(CATPT_DMA_DEVID, chan->chan_id), |
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CATPT_HMDC_HDDA(CATPT_DMA_DEVID, chan->chan_id)); |
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ret = dma_submit_error(dmaengine_submit(desc)); |
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if (ret) { |
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dev_err(cdev->dev, "submit tx failed: %d\n", ret); |
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goto clear_hdda; |
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} |
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status = dma_wait_for_async_tx(desc); |
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ret = (status == DMA_COMPLETE) ? 0 : -EPROTO; |
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clear_hdda: |
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/* regardless of status, disable access to HOST memory in demand mode */ |
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catpt_updatel_shim(cdev, HMDC, |
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CATPT_HMDC_HDDA(CATPT_DMA_DEVID, chan->chan_id), 0); |
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return ret; |
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} |
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int catpt_dma_memcpy_todsp(struct catpt_dev *cdev, struct dma_chan *chan, |
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dma_addr_t dst_addr, dma_addr_t src_addr, |
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size_t size) |
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{ |
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return catpt_dma_memcpy(cdev, chan, dst_addr | CATPT_DMA_DSP_ADDR_MASK, |
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src_addr, size); |
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} |
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int catpt_dma_memcpy_fromdsp(struct catpt_dev *cdev, struct dma_chan *chan, |
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dma_addr_t dst_addr, dma_addr_t src_addr, |
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size_t size) |
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{ |
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return catpt_dma_memcpy(cdev, chan, dst_addr, |
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src_addr | CATPT_DMA_DSP_ADDR_MASK, size); |
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} |
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int catpt_dmac_probe(struct catpt_dev *cdev) |
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{ |
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struct dw_dma_chip *dmac; |
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int ret; |
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dmac = devm_kzalloc(cdev->dev, sizeof(*dmac), GFP_KERNEL); |
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if (!dmac) |
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return -ENOMEM; |
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dmac->regs = cdev->lpe_ba + cdev->spec->host_dma_offset[CATPT_DMA_DEVID]; |
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dmac->dev = cdev->dev; |
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dmac->irq = cdev->irq; |
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ret = dma_coerce_mask_and_coherent(cdev->dev, DMA_BIT_MASK(31)); |
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if (ret) |
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return ret; |
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/* |
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* Caller is responsible for putting device in D0 to allow |
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* for I/O and memory access before probing DW. |
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*/ |
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ret = dw_dma_probe(dmac); |
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if (ret) |
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return ret; |
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cdev->dmac = dmac; |
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return 0; |
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} |
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void catpt_dmac_remove(struct catpt_dev *cdev) |
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{ |
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/* |
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* As do_dma_remove() juggles with pm_runtime_get_xxx() and |
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* pm_runtime_put_xxx() while both ADSP and DW 'devices' are part of |
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* the same module, caller makes sure pm_runtime_disable() is invoked |
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* before removing DW to prevent postmortem resume and suspend. |
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*/ |
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dw_dma_remove(cdev->dmac); |
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} |
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static void catpt_dsp_set_srampge(struct catpt_dev *cdev, struct resource *sram, |
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unsigned long mask, unsigned long new) |
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{ |
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unsigned long old; |
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u32 off = sram->start; |
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u32 b = __ffs(mask); |
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old = catpt_readl_pci(cdev, VDRTCTL0) & mask; |
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dev_dbg(cdev->dev, "SRAMPGE [0x%08lx] 0x%08lx -> 0x%08lx", |
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mask, old, new); |
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if (old == new) |
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return; |
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catpt_updatel_pci(cdev, VDRTCTL0, mask, new); |
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/* wait for SRAM power gating to propagate */ |
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udelay(60); |
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/* |
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* Dummy read as the very first access after block enable |
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* to prevent byte loss in future operations. |
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*/ |
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for_each_clear_bit_from(b, &new, fls_long(mask)) { |
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u8 buf[4]; |
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/* newly enabled: new bit=0 while old bit=1 */ |
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if (test_bit(b, &old)) { |
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dev_dbg(cdev->dev, "sanitize block %ld: off 0x%08x\n", |
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b - __ffs(mask), off); |
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memcpy_fromio(buf, cdev->lpe_ba + off, sizeof(buf)); |
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} |
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off += CATPT_MEMBLOCK_SIZE; |
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} |
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} |
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void catpt_dsp_update_srampge(struct catpt_dev *cdev, struct resource *sram, |
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unsigned long mask) |
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{ |
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struct resource *res; |
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unsigned long new = 0; |
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/* flag all busy blocks */ |
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for (res = sram->child; res; res = res->sibling) { |
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u32 h, l; |
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h = (res->end - sram->start) / CATPT_MEMBLOCK_SIZE; |
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l = (res->start - sram->start) / CATPT_MEMBLOCK_SIZE; |
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new |= GENMASK(h, l); |
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} |
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/* offset value given mask's start and invert it as ON=b0 */ |
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new = ~(new << __ffs(mask)) & mask; |
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/* disable core clock gating */ |
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catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 0); |
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catpt_dsp_set_srampge(cdev, sram, mask, new); |
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/* enable core clock gating */ |
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catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, |
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CATPT_VDRTCTL2_DCLCGE); |
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} |
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int catpt_dsp_stall(struct catpt_dev *cdev, bool stall) |
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{ |
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u32 reg, val; |
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val = stall ? CATPT_CS_STALL : 0; |
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catpt_updatel_shim(cdev, CS1, CATPT_CS_STALL, val); |
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return catpt_readl_poll_shim(cdev, CS1, |
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reg, (reg & CATPT_CS_STALL) == val, |
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500, 10000); |
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} |
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static int catpt_dsp_reset(struct catpt_dev *cdev, bool reset) |
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{ |
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u32 reg, val; |
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val = reset ? CATPT_CS_RST : 0; |
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catpt_updatel_shim(cdev, CS1, CATPT_CS_RST, val); |
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return catpt_readl_poll_shim(cdev, CS1, |
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reg, (reg & CATPT_CS_RST) == val, |
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500, 10000); |
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} |
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void lpt_dsp_pll_shutdown(struct catpt_dev *cdev, bool enable) |
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{ |
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u32 val; |
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val = enable ? LPT_VDRTCTL0_APLLSE : 0; |
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catpt_updatel_pci(cdev, VDRTCTL0, LPT_VDRTCTL0_APLLSE, val); |
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} |
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void wpt_dsp_pll_shutdown(struct catpt_dev *cdev, bool enable) |
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{ |
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u32 val; |
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val = enable ? WPT_VDRTCTL2_APLLSE : 0; |
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catpt_updatel_pci(cdev, VDRTCTL2, WPT_VDRTCTL2_APLLSE, val); |
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} |
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static int catpt_dsp_select_lpclock(struct catpt_dev *cdev, bool lp, bool waiti) |
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{ |
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u32 mask, reg, val; |
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int ret; |
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mutex_lock(&cdev->clk_mutex); |
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val = lp ? CATPT_CS_LPCS : 0; |
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reg = catpt_readl_shim(cdev, CS1) & CATPT_CS_LPCS; |
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dev_dbg(cdev->dev, "LPCS [0x%08lx] 0x%08x -> 0x%08x", |
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CATPT_CS_LPCS, reg, val); |
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if (reg == val) { |
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mutex_unlock(&cdev->clk_mutex); |
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return 0; |
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} |
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if (waiti) { |
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/* wait for DSP to signal WAIT state */ |
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ret = catpt_readl_poll_shim(cdev, ISD, |
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reg, (reg & CATPT_ISD_DCPWM), |
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500, 10000); |
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if (ret) { |
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dev_warn(cdev->dev, "await WAITI timeout\n"); |
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/* no signal - only high clock selection allowed */ |
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if (lp) { |
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mutex_unlock(&cdev->clk_mutex); |
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return 0; |
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} |
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} |
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} |
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ret = catpt_readl_poll_shim(cdev, CLKCTL, |
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reg, !(reg & CATPT_CLKCTL_CFCIP), |
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500, 10000); |
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if (ret) |
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dev_warn(cdev->dev, "clock change still in progress\n"); |
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/* default to DSP core & audio fabric high clock */ |
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val |= CATPT_CS_DCS_HIGH; |
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mask = CATPT_CS_LPCS | CATPT_CS_DCS; |
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catpt_updatel_shim(cdev, CS1, mask, val); |
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ret = catpt_readl_poll_shim(cdev, CLKCTL, |
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reg, !(reg & CATPT_CLKCTL_CFCIP), |
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500, 10000); |
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if (ret) |
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dev_warn(cdev->dev, "clock change still in progress\n"); |
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/* update PLL accordingly */ |
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cdev->spec->pll_shutdown(cdev, lp); |
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mutex_unlock(&cdev->clk_mutex); |
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return 0; |
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} |
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int catpt_dsp_update_lpclock(struct catpt_dev *cdev) |
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{ |
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struct catpt_stream_runtime *stream; |
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list_for_each_entry(stream, &cdev->stream_list, node) |
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if (stream->prepared) |
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return catpt_dsp_select_lpclock(cdev, false, true); |
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return catpt_dsp_select_lpclock(cdev, true, true); |
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} |
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/* bring registers to their defaults as HW won't reset itself */ |
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static void catpt_dsp_set_regs_defaults(struct catpt_dev *cdev) |
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{ |
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int i; |
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catpt_writel_shim(cdev, CS1, CATPT_CS_DEFAULT); |
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catpt_writel_shim(cdev, ISC, CATPT_ISC_DEFAULT); |
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catpt_writel_shim(cdev, ISD, CATPT_ISD_DEFAULT); |
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catpt_writel_shim(cdev, IMC, CATPT_IMC_DEFAULT); |
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catpt_writel_shim(cdev, IMD, CATPT_IMD_DEFAULT); |
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catpt_writel_shim(cdev, IPCC, CATPT_IPCC_DEFAULT); |
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catpt_writel_shim(cdev, IPCD, CATPT_IPCD_DEFAULT); |
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catpt_writel_shim(cdev, CLKCTL, CATPT_CLKCTL_DEFAULT); |
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catpt_writel_shim(cdev, CS2, CATPT_CS2_DEFAULT); |
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catpt_writel_shim(cdev, LTRC, CATPT_LTRC_DEFAULT); |
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catpt_writel_shim(cdev, HMDC, CATPT_HMDC_DEFAULT); |
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for (i = 0; i < CATPT_SSP_COUNT; i++) { |
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catpt_writel_ssp(cdev, i, SSCR0, CATPT_SSC0_DEFAULT); |
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catpt_writel_ssp(cdev, i, SSCR1, CATPT_SSC1_DEFAULT); |
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catpt_writel_ssp(cdev, i, SSSR, CATPT_SSS_DEFAULT); |
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catpt_writel_ssp(cdev, i, SSITR, CATPT_SSIT_DEFAULT); |
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catpt_writel_ssp(cdev, i, SSDR, CATPT_SSD_DEFAULT); |
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catpt_writel_ssp(cdev, i, SSTO, CATPT_SSTO_DEFAULT); |
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catpt_writel_ssp(cdev, i, SSPSP, CATPT_SSPSP_DEFAULT); |
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catpt_writel_ssp(cdev, i, SSTSA, CATPT_SSTSA_DEFAULT); |
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catpt_writel_ssp(cdev, i, SSRSA, CATPT_SSRSA_DEFAULT); |
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catpt_writel_ssp(cdev, i, SSTSS, CATPT_SSTSS_DEFAULT); |
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catpt_writel_ssp(cdev, i, SSCR2, CATPT_SSCR2_DEFAULT); |
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catpt_writel_ssp(cdev, i, SSPSP2, CATPT_SSPSP2_DEFAULT); |
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} |
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} |
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int catpt_dsp_power_down(struct catpt_dev *cdev) |
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{ |
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u32 mask, val; |
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/* disable core clock gating */ |
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catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 0); |
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catpt_dsp_reset(cdev, true); |
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/* set 24Mhz clock for both SSPs */ |
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catpt_updatel_shim(cdev, CS1, CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1), |
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CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1)); |
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catpt_dsp_select_lpclock(cdev, true, false); |
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/* disable MCLK */ |
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catpt_updatel_shim(cdev, CLKCTL, CATPT_CLKCTL_SMOS, 0); |
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catpt_dsp_set_regs_defaults(cdev); |
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/* switch clock gating */ |
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mask = CATPT_VDRTCTL2_CGEALL & (~CATPT_VDRTCTL2_DCLCGE); |
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val = mask & (~CATPT_VDRTCTL2_DTCGE); |
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catpt_updatel_pci(cdev, VDRTCTL2, mask, val); |
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/* enable DTCGE separatelly */ |
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catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DTCGE, |
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CATPT_VDRTCTL2_DTCGE); |
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/* SRAM power gating all */ |
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catpt_dsp_set_srampge(cdev, &cdev->dram, cdev->spec->dram_mask, |
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cdev->spec->dram_mask); |
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catpt_dsp_set_srampge(cdev, &cdev->iram, cdev->spec->iram_mask, |
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cdev->spec->iram_mask); |
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mask = cdev->spec->d3srampgd_bit | cdev->spec->d3pgd_bit; |
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catpt_updatel_pci(cdev, VDRTCTL0, mask, cdev->spec->d3pgd_bit); |
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catpt_updatel_pci(cdev, PMCS, PCI_PM_CTRL_STATE_MASK, PCI_D3hot); |
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/* give hw time to drop off */ |
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udelay(50); |
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/* enable core clock gating */ |
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catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, |
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CATPT_VDRTCTL2_DCLCGE); |
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udelay(50); |
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return 0; |
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} |
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int catpt_dsp_power_up(struct catpt_dev *cdev) |
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{ |
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u32 mask, val; |
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/* disable core clock gating */ |
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catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 0); |
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/* switch clock gating */ |
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mask = CATPT_VDRTCTL2_CGEALL & (~CATPT_VDRTCTL2_DCLCGE); |
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val = mask & (~CATPT_VDRTCTL2_DTCGE); |
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catpt_updatel_pci(cdev, VDRTCTL2, mask, val); |
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catpt_updatel_pci(cdev, PMCS, PCI_PM_CTRL_STATE_MASK, PCI_D0); |
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/* SRAM power gating none */ |
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mask = cdev->spec->d3srampgd_bit | cdev->spec->d3pgd_bit; |
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catpt_updatel_pci(cdev, VDRTCTL0, mask, mask); |
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catpt_dsp_set_srampge(cdev, &cdev->dram, cdev->spec->dram_mask, 0); |
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catpt_dsp_set_srampge(cdev, &cdev->iram, cdev->spec->iram_mask, 0); |
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catpt_dsp_set_regs_defaults(cdev); |
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/* restore MCLK */ |
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catpt_updatel_shim(cdev, CLKCTL, CATPT_CLKCTL_SMOS, CATPT_CLKCTL_SMOS); |
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catpt_dsp_select_lpclock(cdev, false, false); |
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/* set 24Mhz clock for both SSPs */ |
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catpt_updatel_shim(cdev, CS1, CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1), |
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CATPT_CS_SBCS(0) | CATPT_CS_SBCS(1)); |
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catpt_dsp_reset(cdev, false); |
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/* enable core clock gating */ |
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catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, |
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CATPT_VDRTCTL2_DCLCGE); |
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/* generate int deassert msg to fix inversed int logic */ |
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catpt_updatel_shim(cdev, IMC, CATPT_IMC_IPCDB | CATPT_IMC_IPCCD, 0); |
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return 0; |
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} |
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#define CATPT_DUMP_MAGIC 0xcd42 |
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#define CATPT_DUMP_SECTION_ID_FILE 0x00 |
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#define CATPT_DUMP_SECTION_ID_IRAM 0x01 |
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#define CATPT_DUMP_SECTION_ID_DRAM 0x02 |
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#define CATPT_DUMP_SECTION_ID_REGS 0x03 |
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#define CATPT_DUMP_HASH_SIZE 20 |
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struct catpt_dump_section_hdr { |
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u16 magic; |
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u8 core_id; |
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u8 section_id; |
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u32 size; |
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}; |
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int catpt_coredump(struct catpt_dev *cdev) |
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{ |
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struct catpt_dump_section_hdr *hdr; |
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size_t dump_size, regs_size; |
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u8 *dump, *pos; |
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const char *eof; |
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char *info; |
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int i; |
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regs_size = CATPT_SHIM_REGS_SIZE; |
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regs_size += CATPT_DMA_COUNT * CATPT_DMA_REGS_SIZE; |
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regs_size += CATPT_SSP_COUNT * CATPT_SSP_REGS_SIZE; |
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dump_size = resource_size(&cdev->dram); |
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dump_size += resource_size(&cdev->iram); |
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dump_size += regs_size; |
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/* account for header of each section and hash chunk */ |
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dump_size += 4 * sizeof(*hdr) + CATPT_DUMP_HASH_SIZE; |
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dump = vzalloc(dump_size); |
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if (!dump) |
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return -ENOMEM; |
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pos = dump; |
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hdr = (struct catpt_dump_section_hdr *)pos; |
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hdr->magic = CATPT_DUMP_MAGIC; |
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hdr->core_id = cdev->spec->core_id; |
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hdr->section_id = CATPT_DUMP_SECTION_ID_FILE; |
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hdr->size = dump_size - sizeof(*hdr); |
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pos += sizeof(*hdr); |
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info = cdev->ipc.config.fw_info; |
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eof = info + FW_INFO_SIZE_MAX; |
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/* navigate to fifth info segment (fw hash) */ |
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for (i = 0; i < 4 && info < eof; i++, info++) { |
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/* info segments are separated by space each */ |
|
info = strnchr(info, eof - info, ' '); |
|
if (!info) |
|
break; |
|
} |
|
|
|
if (i == 4 && info) |
|
memcpy(pos, info, min_t(u32, eof - info, CATPT_DUMP_HASH_SIZE)); |
|
pos += CATPT_DUMP_HASH_SIZE; |
|
|
|
hdr = (struct catpt_dump_section_hdr *)pos; |
|
hdr->magic = CATPT_DUMP_MAGIC; |
|
hdr->core_id = cdev->spec->core_id; |
|
hdr->section_id = CATPT_DUMP_SECTION_ID_IRAM; |
|
hdr->size = resource_size(&cdev->iram); |
|
pos += sizeof(*hdr); |
|
|
|
memcpy_fromio(pos, cdev->lpe_ba + cdev->iram.start, hdr->size); |
|
pos += hdr->size; |
|
|
|
hdr = (struct catpt_dump_section_hdr *)pos; |
|
hdr->magic = CATPT_DUMP_MAGIC; |
|
hdr->core_id = cdev->spec->core_id; |
|
hdr->section_id = CATPT_DUMP_SECTION_ID_DRAM; |
|
hdr->size = resource_size(&cdev->dram); |
|
pos += sizeof(*hdr); |
|
|
|
memcpy_fromio(pos, cdev->lpe_ba + cdev->dram.start, hdr->size); |
|
pos += hdr->size; |
|
|
|
hdr = (struct catpt_dump_section_hdr *)pos; |
|
hdr->magic = CATPT_DUMP_MAGIC; |
|
hdr->core_id = cdev->spec->core_id; |
|
hdr->section_id = CATPT_DUMP_SECTION_ID_REGS; |
|
hdr->size = regs_size; |
|
pos += sizeof(*hdr); |
|
|
|
memcpy_fromio(pos, catpt_shim_addr(cdev), CATPT_SHIM_REGS_SIZE); |
|
pos += CATPT_SHIM_REGS_SIZE; |
|
|
|
for (i = 0; i < CATPT_SSP_COUNT; i++) { |
|
memcpy_fromio(pos, catpt_ssp_addr(cdev, i), |
|
CATPT_SSP_REGS_SIZE); |
|
pos += CATPT_SSP_REGS_SIZE; |
|
} |
|
for (i = 0; i < CATPT_DMA_COUNT; i++) { |
|
memcpy_fromio(pos, catpt_dma_addr(cdev, i), |
|
CATPT_DMA_REGS_SIZE); |
|
pos += CATPT_DMA_REGS_SIZE; |
|
} |
|
|
|
dev_coredumpv(cdev->dev, dump, dump_size, GFP_KERNEL); |
|
|
|
return 0; |
|
}
|
|
|