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82 lines
2.3 KiB
82 lines
2.3 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* wm8978.h -- codec driver for WM8978 |
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* |
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* Copyright 2009 Guennadi Liakhovetski <[email protected]> |
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*/ |
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#ifndef __WM8978_H__ |
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#define __WM8978_H__ |
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/* |
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* Register values. |
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*/ |
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#define WM8978_RESET 0x00 |
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#define WM8978_POWER_MANAGEMENT_1 0x01 |
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#define WM8978_POWER_MANAGEMENT_2 0x02 |
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#define WM8978_POWER_MANAGEMENT_3 0x03 |
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#define WM8978_AUDIO_INTERFACE 0x04 |
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#define WM8978_COMPANDING_CONTROL 0x05 |
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#define WM8978_CLOCKING 0x06 |
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#define WM8978_ADDITIONAL_CONTROL 0x07 |
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#define WM8978_GPIO_CONTROL 0x08 |
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#define WM8978_JACK_DETECT_CONTROL_1 0x09 |
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#define WM8978_DAC_CONTROL 0x0A |
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#define WM8978_LEFT_DAC_DIGITAL_VOLUME 0x0B |
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#define WM8978_RIGHT_DAC_DIGITAL_VOLUME 0x0C |
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#define WM8978_JACK_DETECT_CONTROL_2 0x0D |
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#define WM8978_ADC_CONTROL 0x0E |
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#define WM8978_LEFT_ADC_DIGITAL_VOLUME 0x0F |
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#define WM8978_RIGHT_ADC_DIGITAL_VOLUME 0x10 |
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#define WM8978_EQ1 0x12 |
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#define WM8978_EQ2 0x13 |
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#define WM8978_EQ3 0x14 |
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#define WM8978_EQ4 0x15 |
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#define WM8978_EQ5 0x16 |
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#define WM8978_DAC_LIMITER_1 0x18 |
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#define WM8978_DAC_LIMITER_2 0x19 |
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#define WM8978_NOTCH_FILTER_1 0x1b |
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#define WM8978_NOTCH_FILTER_2 0x1c |
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#define WM8978_NOTCH_FILTER_3 0x1d |
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#define WM8978_NOTCH_FILTER_4 0x1e |
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#define WM8978_ALC_CONTROL_1 0x20 |
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#define WM8978_ALC_CONTROL_2 0x21 |
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#define WM8978_ALC_CONTROL_3 0x22 |
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#define WM8978_NOISE_GATE 0x23 |
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#define WM8978_PLL_N 0x24 |
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#define WM8978_PLL_K1 0x25 |
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#define WM8978_PLL_K2 0x26 |
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#define WM8978_PLL_K3 0x27 |
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#define WM8978_3D_CONTROL 0x29 |
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#define WM8978_BEEP_CONTROL 0x2b |
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#define WM8978_INPUT_CONTROL 0x2c |
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#define WM8978_LEFT_INP_PGA_CONTROL 0x2d |
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#define WM8978_RIGHT_INP_PGA_CONTROL 0x2e |
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#define WM8978_LEFT_ADC_BOOST_CONTROL 0x2f |
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#define WM8978_RIGHT_ADC_BOOST_CONTROL 0x30 |
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#define WM8978_OUTPUT_CONTROL 0x31 |
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#define WM8978_LEFT_MIXER_CONTROL 0x32 |
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#define WM8978_RIGHT_MIXER_CONTROL 0x33 |
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#define WM8978_LOUT1_HP_CONTROL 0x34 |
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#define WM8978_ROUT1_HP_CONTROL 0x35 |
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#define WM8978_LOUT2_SPK_CONTROL 0x36 |
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#define WM8978_ROUT2_SPK_CONTROL 0x37 |
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#define WM8978_OUT3_MIXER_CONTROL 0x38 |
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#define WM8978_OUT4_MIXER_CONTROL 0x39 |
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#define WM8978_MAX_REGISTER 0x39 |
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#define WM8978_CACHEREGNUM 58 |
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/* Clock divider Id's */ |
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enum wm8978_clk_id { |
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WM8978_OPCLKRATE, |
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WM8978_BCLKDIV, |
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}; |
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enum wm8978_sysclk_src { |
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WM8978_MCLK = 0, |
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WM8978_PLL, |
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}; |
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#endif /* __WM8978_H__ */
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