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631 lines
16 KiB
631 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0 |
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#include <linux/bits.h> |
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#include <linux/bitfield.h> |
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#include <linux/delay.h> |
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#include <linux/gpio/consumer.h> |
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#include <linux/i2c.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/regmap.h> |
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#include <linux/regulator/consumer.h> |
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#include <sound/pcm.h> |
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#include <sound/pcm_params.h> |
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#include <sound/soc.h> |
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#include <sound/tlv.h> |
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#define RT9120_REG_DEVID 0x00 |
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#define RT9120_REG_I2SFMT 0x02 |
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#define RT9120_REG_I2SWL 0x03 |
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#define RT9120_REG_SDIOSEL 0x04 |
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#define RT9120_REG_SYSCTL 0x05 |
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#define RT9120_REG_SPKGAIN 0x07 |
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#define RT9120_REG_VOLRAMP 0x0A |
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#define RT9120_REG_ERRRPT 0x10 |
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#define RT9120_REG_MSVOL 0x20 |
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#define RT9120_REG_SWRESET 0x40 |
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#define RT9120_REG_INTERCFG 0x63 |
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#define RT9120_REG_INTERNAL0 0x65 |
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#define RT9120_REG_INTERNAL1 0x69 |
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#define RT9120_REG_UVPOPT 0x6C |
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#define RT9120_REG_DIGCFG 0xF8 |
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#define RT9120_VID_MASK GENMASK(15, 8) |
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#define RT9120_SWRST_MASK BIT(7) |
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#define RT9120_MUTE_MASK GENMASK(5, 4) |
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#define RT9120_I2SFMT_MASK GENMASK(4, 2) |
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#define RT9120_I2SFMT_SHIFT 2 |
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#define RT9120_CFG_FMT_I2S 0 |
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#define RT9120_CFG_FMT_LEFTJ 1 |
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#define RT9120_CFG_FMT_RIGHTJ 2 |
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#define RT9120_CFG_FMT_DSPA 3 |
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#define RT9120_CFG_FMT_DSPB 7 |
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#define RT9120_AUDBIT_MASK GENMASK(1, 0) |
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#define RT9120_CFG_AUDBIT_16 0 |
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#define RT9120_CFG_AUDBIT_20 1 |
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#define RT9120_CFG_AUDBIT_24 2 |
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#define RT9120_AUDWL_MASK GENMASK(5, 0) |
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#define RT9120_CFG_WORDLEN_16 16 |
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#define RT9120_CFG_WORDLEN_24 24 |
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#define RT9120_CFG_WORDLEN_32 32 |
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#define RT9120_DVDD_UVSEL_MASK GENMASK(5, 4) |
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#define RT9120_AUTOSYNC_MASK BIT(6) |
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#define RT9120_VENDOR_ID 0x42 |
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#define RT9120S_VENDOR_ID 0x43 |
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#define RT9120_RESET_WAITMS 20 |
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#define RT9120_CHIPON_WAITMS 20 |
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#define RT9120_AMPON_WAITMS 50 |
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#define RT9120_AMPOFF_WAITMS 100 |
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#define RT9120_LVAPP_THRESUV 2000000 |
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/* 8000 to 192000 supported , only 176400 not support */ |
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#define RT9120_RATES_MASK (SNDRV_PCM_RATE_8000_192000 &\ |
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~SNDRV_PCM_RATE_176400) |
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#define RT9120_FMTS_MASK (SNDRV_PCM_FMTBIT_S16_LE |\ |
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SNDRV_PCM_FMTBIT_S24_LE |\ |
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SNDRV_PCM_FMTBIT_S32_LE) |
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enum { |
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CHIP_IDX_RT9120 = 0, |
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CHIP_IDX_RT9120S, |
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CHIP_IDX_MAX |
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}; |
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struct rt9120_data { |
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struct device *dev; |
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struct regmap *regmap; |
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struct gpio_desc *pwdnn_gpio; |
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int chip_idx; |
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}; |
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/* 11bit [min,max,step] = [-103.9375dB, 24dB, 0.0625dB] */ |
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static const DECLARE_TLV_DB_SCALE(digital_tlv, -1039375, 625, 1); |
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/* {6, 8, 10, 12, 13, 14, 15, 16}dB */ |
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static const DECLARE_TLV_DB_RANGE(classd_tlv, |
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0, 3, TLV_DB_SCALE_ITEM(600, 200, 0), |
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4, 7, TLV_DB_SCALE_ITEM(1300, 100, 0) |
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); |
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static const char * const sdo_select_text[] = { |
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"None", "INTF", "Final", "RMS Detect" |
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}; |
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static const struct soc_enum sdo_select_enum = |
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SOC_ENUM_SINGLE(RT9120_REG_SDIOSEL, 4, ARRAY_SIZE(sdo_select_text), |
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sdo_select_text); |
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static const struct snd_kcontrol_new rt9120_snd_controls[] = { |
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SOC_SINGLE_TLV("MS Volume", RT9120_REG_MSVOL, 0, 2047, 1, digital_tlv), |
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SOC_SINGLE_TLV("SPK Gain Volume", RT9120_REG_SPKGAIN, 0, 7, 0, classd_tlv), |
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SOC_SINGLE("PBTL Switch", RT9120_REG_SYSCTL, 3, 1, 0), |
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SOC_ENUM("SDO Select", sdo_select_enum), |
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}; |
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static int internal_power_event(struct snd_soc_dapm_widget *w, |
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struct snd_kcontrol *kcontrol, int event) |
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{ |
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struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); |
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switch (event) { |
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case SND_SOC_DAPM_PRE_PMU: |
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snd_soc_component_write(comp, RT9120_REG_ERRRPT, 0); |
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break; |
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case SND_SOC_DAPM_POST_PMU: |
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msleep(RT9120_AMPON_WAITMS); |
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break; |
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case SND_SOC_DAPM_POST_PMD: |
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msleep(RT9120_AMPOFF_WAITMS); |
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break; |
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default: |
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break; |
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} |
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return 0; |
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} |
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static const struct snd_soc_dapm_widget rt9120_dapm_widgets[] = { |
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SND_SOC_DAPM_MIXER("DMIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
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SND_SOC_DAPM_DAC("LDAC", NULL, SND_SOC_NOPM, 0, 0), |
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SND_SOC_DAPM_DAC("RDAC", NULL, SND_SOC_NOPM, 0, 0), |
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SND_SOC_DAPM_SUPPLY("PWND", RT9120_REG_SYSCTL, 6, 1, |
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internal_power_event, SND_SOC_DAPM_PRE_PMU | |
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SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), |
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SND_SOC_DAPM_PGA("SPKL PA", SND_SOC_NOPM, 0, 0, NULL, 0), |
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SND_SOC_DAPM_PGA("SPKR PA", SND_SOC_NOPM, 0, 0, NULL, 0), |
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SND_SOC_DAPM_OUTPUT("SPKL"), |
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SND_SOC_DAPM_OUTPUT("SPKR"), |
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}; |
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static const struct snd_soc_dapm_route rt9120_dapm_routes[] = { |
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{ "DMIX", NULL, "AIF Playback" }, |
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/* SPKL */ |
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{ "LDAC", NULL, "PWND" }, |
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{ "LDAC", NULL, "DMIX" }, |
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{ "SPKL PA", NULL, "LDAC" }, |
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{ "SPKL", NULL, "SPKL PA" }, |
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/* SPKR */ |
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{ "RDAC", NULL, "PWND" }, |
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{ "RDAC", NULL, "DMIX" }, |
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{ "SPKR PA", NULL, "RDAC" }, |
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{ "SPKR", NULL, "SPKR PA" }, |
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/* Cap */ |
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{ "AIF Capture", NULL, "LDAC" }, |
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{ "AIF Capture", NULL, "RDAC" }, |
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}; |
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static int rt9120_codec_probe(struct snd_soc_component *comp) |
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{ |
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struct rt9120_data *data = snd_soc_component_get_drvdata(comp); |
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snd_soc_component_init_regmap(comp, data->regmap); |
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pm_runtime_get_sync(comp->dev); |
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/* Internal setting */ |
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if (data->chip_idx == CHIP_IDX_RT9120S) { |
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snd_soc_component_write(comp, RT9120_REG_INTERCFG, 0xde); |
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snd_soc_component_write(comp, RT9120_REG_INTERNAL0, 0x66); |
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} else |
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snd_soc_component_write(comp, RT9120_REG_INTERNAL0, 0x04); |
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pm_runtime_mark_last_busy(comp->dev); |
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pm_runtime_put(comp->dev); |
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return 0; |
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} |
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static const struct snd_soc_component_driver rt9120_component_driver = { |
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.probe = rt9120_codec_probe, |
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.controls = rt9120_snd_controls, |
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.num_controls = ARRAY_SIZE(rt9120_snd_controls), |
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.dapm_widgets = rt9120_dapm_widgets, |
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.num_dapm_widgets = ARRAY_SIZE(rt9120_dapm_widgets), |
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.dapm_routes = rt9120_dapm_routes, |
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.num_dapm_routes = ARRAY_SIZE(rt9120_dapm_routes), |
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.endianness = 1, |
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}; |
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static int rt9120_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
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{ |
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struct snd_soc_component *comp = dai->component; |
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unsigned int format; |
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
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case SND_SOC_DAIFMT_I2S: |
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format = RT9120_CFG_FMT_I2S; |
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break; |
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case SND_SOC_DAIFMT_LEFT_J: |
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format = RT9120_CFG_FMT_LEFTJ; |
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break; |
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case SND_SOC_DAIFMT_RIGHT_J: |
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format = RT9120_CFG_FMT_RIGHTJ; |
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break; |
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case SND_SOC_DAIFMT_DSP_A: |
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format = RT9120_CFG_FMT_DSPA; |
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break; |
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case SND_SOC_DAIFMT_DSP_B: |
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format = RT9120_CFG_FMT_DSPB; |
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break; |
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default: |
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dev_err(dai->dev, "Unknown dai format\n"); |
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return -EINVAL; |
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} |
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snd_soc_component_update_bits(comp, RT9120_REG_I2SFMT, |
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RT9120_I2SFMT_MASK, |
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format << RT9120_I2SFMT_SHIFT); |
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return 0; |
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} |
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static int rt9120_hw_params(struct snd_pcm_substream *substream, |
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struct snd_pcm_hw_params *param, |
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struct snd_soc_dai *dai) |
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{ |
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struct snd_soc_component *comp = dai->component; |
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unsigned int param_width, param_slot_width, auto_sync; |
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int width, fs; |
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switch (width = params_width(param)) { |
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case 16: |
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param_width = RT9120_CFG_AUDBIT_16; |
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break; |
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case 20: |
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param_width = RT9120_CFG_AUDBIT_20; |
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break; |
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case 24: |
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case 32: |
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param_width = RT9120_CFG_AUDBIT_24; |
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break; |
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default: |
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dev_err(dai->dev, "Unsupported data width [%d]\n", width); |
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return -EINVAL; |
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} |
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snd_soc_component_update_bits(comp, RT9120_REG_I2SFMT, |
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RT9120_AUDBIT_MASK, param_width); |
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switch (width = params_physical_width(param)) { |
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case 16: |
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param_slot_width = RT9120_CFG_WORDLEN_16; |
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break; |
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case 24: |
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param_slot_width = RT9120_CFG_WORDLEN_24; |
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break; |
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case 32: |
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param_slot_width = RT9120_CFG_WORDLEN_32; |
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break; |
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default: |
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dev_err(dai->dev, "Unsupported slot width [%d]\n", width); |
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return -EINVAL; |
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} |
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snd_soc_component_update_bits(comp, RT9120_REG_I2SWL, |
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RT9120_AUDWL_MASK, param_slot_width); |
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fs = width * params_channels(param); |
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/* If fs is divided by 48, disable auto sync */ |
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if (fs % 48 == 0) |
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auto_sync = 0; |
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else |
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auto_sync = RT9120_AUTOSYNC_MASK; |
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snd_soc_component_update_bits(comp, RT9120_REG_DIGCFG, |
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RT9120_AUTOSYNC_MASK, auto_sync); |
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return 0; |
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} |
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static const struct snd_soc_dai_ops rt9120_dai_ops = { |
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.set_fmt = rt9120_set_fmt, |
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.hw_params = rt9120_hw_params, |
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}; |
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static struct snd_soc_dai_driver rt9120_dai = { |
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.name = "rt9120_aif", |
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.playback = { |
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.stream_name = "AIF Playback", |
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.rates = RT9120_RATES_MASK, |
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.formats = RT9120_FMTS_MASK, |
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.rate_max = 192000, |
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.rate_min = 8000, |
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.channels_min = 1, |
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.channels_max = 2, |
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}, |
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.capture = { |
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.stream_name = "AIF Capture", |
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.rates = RT9120_RATES_MASK, |
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.formats = RT9120_FMTS_MASK, |
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.rate_max = 192000, |
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.rate_min = 8000, |
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.channels_min = 1, |
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.channels_max = 2, |
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}, |
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.ops = &rt9120_dai_ops, |
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.symmetric_rate = 1, |
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.symmetric_sample_bits = 1, |
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}; |
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static const struct regmap_range rt9120_rd_yes_ranges[] = { |
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regmap_reg_range(0x00, 0x0C), |
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regmap_reg_range(0x10, 0x15), |
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regmap_reg_range(0x20, 0x27), |
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regmap_reg_range(0x30, 0x38), |
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regmap_reg_range(0x3A, 0x40), |
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regmap_reg_range(0x63, 0x63), |
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regmap_reg_range(0x65, 0x65), |
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regmap_reg_range(0x69, 0x69), |
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regmap_reg_range(0x6C, 0x6C), |
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regmap_reg_range(0xF8, 0xF8) |
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}; |
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static const struct regmap_access_table rt9120_rd_table = { |
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.yes_ranges = rt9120_rd_yes_ranges, |
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.n_yes_ranges = ARRAY_SIZE(rt9120_rd_yes_ranges), |
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}; |
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static const struct regmap_range rt9120_wr_yes_ranges[] = { |
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regmap_reg_range(0x00, 0x00), |
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regmap_reg_range(0x02, 0x0A), |
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regmap_reg_range(0x10, 0x15), |
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regmap_reg_range(0x20, 0x27), |
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regmap_reg_range(0x30, 0x38), |
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regmap_reg_range(0x3A, 0x3D), |
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regmap_reg_range(0x40, 0x40), |
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regmap_reg_range(0x63, 0x63), |
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regmap_reg_range(0x65, 0x65), |
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regmap_reg_range(0x69, 0x69), |
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regmap_reg_range(0x6C, 0x6C), |
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regmap_reg_range(0xF8, 0xF8) |
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}; |
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static const struct regmap_access_table rt9120_wr_table = { |
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.yes_ranges = rt9120_wr_yes_ranges, |
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.n_yes_ranges = ARRAY_SIZE(rt9120_wr_yes_ranges), |
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}; |
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static bool rt9120_volatile_reg(struct device *dev, unsigned int reg) |
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{ |
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switch (reg) { |
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case 0x00 ... 0x01: |
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case 0x10: |
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case 0x30 ... 0x40: |
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return true; |
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default: |
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return false; |
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} |
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} |
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static int rt9120_get_reg_size(unsigned int reg) |
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{ |
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switch (reg) { |
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case 0x00: |
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case 0x20 ... 0x27: |
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return 2; |
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case 0x30 ... 0x3D: |
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return 3; |
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case 0x3E ... 0x3F: |
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return 4; |
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default: |
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return 1; |
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} |
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} |
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static int rt9120_reg_read(void *context, unsigned int reg, unsigned int *val) |
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{ |
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struct rt9120_data *data = context; |
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struct i2c_client *i2c = to_i2c_client(data->dev); |
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int size = rt9120_get_reg_size(reg); |
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u8 raw[4] = {0}; |
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int ret; |
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ret = i2c_smbus_read_i2c_block_data(i2c, reg, size, raw); |
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if (ret < 0) |
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return ret; |
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else if (ret != size) |
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return -EIO; |
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switch (size) { |
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case 4: |
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*val = be32_to_cpup((__be32 *)raw); |
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break; |
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case 3: |
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*val = raw[0] << 16 | raw[1] << 8 | raw[2]; |
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break; |
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case 2: |
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*val = be16_to_cpup((__be16 *)raw); |
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break; |
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default: |
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*val = raw[0]; |
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} |
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return 0; |
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} |
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static int rt9120_reg_write(void *context, unsigned int reg, unsigned int val) |
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{ |
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struct rt9120_data *data = context; |
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struct i2c_client *i2c = to_i2c_client(data->dev); |
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int size = rt9120_get_reg_size(reg); |
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__be32 be32_val; |
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u8 *rawp = (u8 *)&be32_val; |
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int offs = 4 - size; |
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be32_val = cpu_to_be32(val); |
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return i2c_smbus_write_i2c_block_data(i2c, reg, size, rawp + offs); |
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} |
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static const struct reg_default rt9120_reg_defaults[] = { |
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{ .reg = 0x02, .def = 0x02 }, |
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{ .reg = 0x03, .def = 0xf2 }, |
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{ .reg = 0x04, .def = 0x01 }, |
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{ .reg = 0x05, .def = 0xc0 }, |
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{ .reg = 0x06, .def = 0x28 }, |
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{ .reg = 0x07, .def = 0x04 }, |
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{ .reg = 0x08, .def = 0xff }, |
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{ .reg = 0x09, .def = 0x01 }, |
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{ .reg = 0x0a, .def = 0x01 }, |
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{ .reg = 0x0b, .def = 0x00 }, |
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{ .reg = 0x0c, .def = 0x04 }, |
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{ .reg = 0x11, .def = 0x30 }, |
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{ .reg = 0x12, .def = 0x08 }, |
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{ .reg = 0x13, .def = 0x12 }, |
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{ .reg = 0x14, .def = 0x09 }, |
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{ .reg = 0x15, .def = 0x00 }, |
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{ .reg = 0x20, .def = 0x7ff }, |
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{ .reg = 0x21, .def = 0x180 }, |
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{ .reg = 0x22, .def = 0x180 }, |
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{ .reg = 0x23, .def = 0x00 }, |
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{ .reg = 0x24, .def = 0x80 }, |
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{ .reg = 0x25, .def = 0x180 }, |
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{ .reg = 0x26, .def = 0x640 }, |
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{ .reg = 0x27, .def = 0x180 }, |
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{ .reg = 0x63, .def = 0x5e }, |
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{ .reg = 0x65, .def = 0x66 }, |
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{ .reg = 0x6c, .def = 0xe0 }, |
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{ .reg = 0xf8, .def = 0x44 }, |
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}; |
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static const struct regmap_config rt9120_regmap_config = { |
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.reg_bits = 8, |
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.val_bits = 32, |
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.max_register = RT9120_REG_DIGCFG, |
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.reg_defaults = rt9120_reg_defaults, |
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.num_reg_defaults = ARRAY_SIZE(rt9120_reg_defaults), |
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.cache_type = REGCACHE_RBTREE, |
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|
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.reg_read = rt9120_reg_read, |
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.reg_write = rt9120_reg_write, |
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.volatile_reg = rt9120_volatile_reg, |
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.wr_table = &rt9120_wr_table, |
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.rd_table = &rt9120_rd_table, |
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}; |
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static int rt9120_check_vendor_info(struct rt9120_data *data) |
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{ |
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unsigned int devid; |
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int ret; |
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|
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ret = regmap_read(data->regmap, RT9120_REG_DEVID, &devid); |
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if (ret) |
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return ret; |
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|
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devid = FIELD_GET(RT9120_VID_MASK, devid); |
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switch (devid) { |
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case RT9120_VENDOR_ID: |
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data->chip_idx = CHIP_IDX_RT9120; |
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break; |
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case RT9120S_VENDOR_ID: |
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data->chip_idx = CHIP_IDX_RT9120S; |
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break; |
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default: |
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dev_err(data->dev, "DEVID not correct [0x%0x]\n", devid); |
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return -ENODEV; |
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} |
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|
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return 0; |
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} |
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|
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static int rt9120_do_register_reset(struct rt9120_data *data) |
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{ |
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int ret; |
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|
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ret = regmap_write(data->regmap, RT9120_REG_SWRESET, |
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RT9120_SWRST_MASK); |
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if (ret) |
|
return ret; |
|
|
|
msleep(RT9120_RESET_WAITMS); |
|
return 0; |
|
} |
|
|
|
static int rt9120_probe(struct i2c_client *i2c) |
|
{ |
|
struct rt9120_data *data; |
|
struct regulator *dvdd_supply; |
|
int dvdd_supply_volt, ret; |
|
|
|
data = devm_kzalloc(&i2c->dev, sizeof(*data), GFP_KERNEL); |
|
if (!data) |
|
return -ENOMEM; |
|
|
|
data->dev = &i2c->dev; |
|
i2c_set_clientdata(i2c, data); |
|
|
|
data->pwdnn_gpio = devm_gpiod_get_optional(&i2c->dev, "pwdnn", |
|
GPIOD_OUT_HIGH); |
|
if (IS_ERR(data->pwdnn_gpio)) { |
|
dev_err(&i2c->dev, "Failed to initialize 'pwdnn' gpio\n"); |
|
return PTR_ERR(data->pwdnn_gpio); |
|
} else if (data->pwdnn_gpio) { |
|
dev_dbg(&i2c->dev, "'pwdnn' from low to high, wait chip on\n"); |
|
msleep(RT9120_CHIPON_WAITMS); |
|
} |
|
|
|
data->regmap = devm_regmap_init(&i2c->dev, NULL, data, |
|
&rt9120_regmap_config); |
|
if (IS_ERR(data->regmap)) { |
|
ret = PTR_ERR(data->regmap); |
|
dev_err(&i2c->dev, "Failed to init regmap [%d]\n", ret); |
|
return ret; |
|
} |
|
|
|
ret = rt9120_check_vendor_info(data); |
|
if (ret) { |
|
dev_err(&i2c->dev, "Failed to check vendor info\n"); |
|
return ret; |
|
} |
|
|
|
ret = rt9120_do_register_reset(data); |
|
if (ret) { |
|
dev_err(&i2c->dev, "Failed to do register reset\n"); |
|
return ret; |
|
} |
|
|
|
dvdd_supply = devm_regulator_get(&i2c->dev, "dvdd"); |
|
if (IS_ERR(dvdd_supply)) { |
|
dev_err(&i2c->dev, "No dvdd regulator found\n"); |
|
return PTR_ERR(dvdd_supply); |
|
} |
|
|
|
dvdd_supply_volt = regulator_get_voltage(dvdd_supply); |
|
if (dvdd_supply_volt <= RT9120_LVAPP_THRESUV) { |
|
dev_dbg(&i2c->dev, "dvdd low voltage design\n"); |
|
ret = regmap_update_bits(data->regmap, RT9120_REG_UVPOPT, |
|
RT9120_DVDD_UVSEL_MASK, 0); |
|
if (ret) { |
|
dev_err(&i2c->dev, "Failed to config dvdd uvsel\n"); |
|
return ret; |
|
} |
|
} |
|
|
|
pm_runtime_set_autosuspend_delay(&i2c->dev, 1000); |
|
pm_runtime_use_autosuspend(&i2c->dev); |
|
pm_runtime_set_active(&i2c->dev); |
|
pm_runtime_mark_last_busy(&i2c->dev); |
|
pm_runtime_enable(&i2c->dev); |
|
|
|
return devm_snd_soc_register_component(&i2c->dev, |
|
&rt9120_component_driver, |
|
&rt9120_dai, 1); |
|
} |
|
|
|
static void rt9120_remove(struct i2c_client *i2c) |
|
{ |
|
pm_runtime_disable(&i2c->dev); |
|
pm_runtime_set_suspended(&i2c->dev); |
|
} |
|
|
|
static int __maybe_unused rt9120_runtime_suspend(struct device *dev) |
|
{ |
|
struct rt9120_data *data = dev_get_drvdata(dev); |
|
|
|
if (data->pwdnn_gpio) { |
|
regcache_cache_only(data->regmap, true); |
|
regcache_mark_dirty(data->regmap); |
|
gpiod_set_value(data->pwdnn_gpio, 0); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int __maybe_unused rt9120_runtime_resume(struct device *dev) |
|
{ |
|
struct rt9120_data *data = dev_get_drvdata(dev); |
|
|
|
if (data->pwdnn_gpio) { |
|
gpiod_set_value(data->pwdnn_gpio, 1); |
|
msleep(RT9120_CHIPON_WAITMS); |
|
regcache_cache_only(data->regmap, false); |
|
regcache_sync(data->regmap); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static const struct dev_pm_ops rt9120_pm_ops = { |
|
SET_RUNTIME_PM_OPS(rt9120_runtime_suspend, rt9120_runtime_resume, NULL) |
|
}; |
|
|
|
static const struct of_device_id __maybe_unused rt9120_device_table[] = { |
|
{ .compatible = "richtek,rt9120", }, |
|
{ } |
|
}; |
|
MODULE_DEVICE_TABLE(of, rt9120_device_table); |
|
|
|
static struct i2c_driver rt9120_driver = { |
|
.driver = { |
|
.name = "rt9120", |
|
.of_match_table = rt9120_device_table, |
|
.pm = &rt9120_pm_ops, |
|
}, |
|
.probe_new = rt9120_probe, |
|
.remove = rt9120_remove, |
|
}; |
|
module_i2c_driver(rt9120_driver); |
|
|
|
MODULE_AUTHOR("ChiYuan Huang <[email protected]>"); |
|
MODULE_DESCRIPTION("RT9120 Audio Amplifier Driver"); |
|
MODULE_LICENSE("GPL");
|
|
|