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543 lines
17 KiB
543 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// |
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// rk817 ALSA SoC Audio driver |
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// |
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// Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd All rights reserved. |
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#include <linux/clk.h> |
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#include <linux/device.h> |
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#include <linux/delay.h> |
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#include <linux/mfd/rk808.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_gpio.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#include <sound/core.h> |
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#include <sound/pcm_params.h> |
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#include <sound/soc.h> |
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#include <sound/tlv.h> |
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struct rk817_codec_priv { |
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struct snd_soc_component *component; |
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struct rk808 *rk808; |
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struct clk *mclk; |
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unsigned int stereo_sysclk; |
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bool mic_in_differential; |
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}; |
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/* |
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* This sets the codec up with the values defined in the default implementation including the APLL |
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* from the Rockchip vendor kernel. I do not know if these values are universal despite differing |
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* from the default values defined above and taken from the datasheet, or implementation specific. |
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* I don't have another implementation to compare from the Rockchip sources. Hard-coding for now. |
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* Additionally, I do not know according to the documentation the units accepted for the clock |
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* values, so for the moment those are left unvalidated. |
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*/ |
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static int rk817_init(struct snd_soc_component *component) |
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{ |
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struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component); |
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snd_soc_component_write(component, RK817_CODEC_DDAC_POPD_DACST, 0x02); |
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snd_soc_component_write(component, RK817_CODEC_DDAC_SR_LMT0, 0x02); |
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snd_soc_component_write(component, RK817_CODEC_DADC_SR_ACL0, 0x02); |
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snd_soc_component_write(component, RK817_CODEC_DTOP_VUCTIME, 0xf4); |
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if (rk817->mic_in_differential) { |
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snd_soc_component_update_bits(component, RK817_CODEC_AMIC_CFG0, MIC_DIFF_MASK, |
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MIC_DIFF_EN); |
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} |
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return 0; |
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} |
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static int rk817_set_component_pll(struct snd_soc_component *component, |
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int pll_id, int source, unsigned int freq_in, |
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unsigned int freq_out) |
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{ |
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/* Set resistor value and charge pump current for PLL. */ |
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snd_soc_component_write(component, RK817_CODEC_APLL_CFG1, 0x58); |
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/* Set the PLL feedback clock divide value (values not documented). */ |
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snd_soc_component_write(component, RK817_CODEC_APLL_CFG2, 0x2d); |
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/* Set the PLL pre-divide value (values not documented). */ |
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snd_soc_component_write(component, RK817_CODEC_APLL_CFG3, 0x0c); |
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/* Set the PLL VCO output clock divide and PLL divided ratio of PLL High Clk (values not |
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* documented). |
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*/ |
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snd_soc_component_write(component, RK817_CODEC_APLL_CFG4, 0xa5); |
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return 0; |
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} |
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/* |
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* DDAC/DADC L/R volume setting |
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* 0db~-95db, 0.375db/step, for example: |
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* 0x00: 0dB |
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* 0xff: -95dB |
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*/ |
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static const DECLARE_TLV_DB_MINMAX(rk817_vol_tlv, -9500, 0); |
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/* |
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* PGA GAIN L/R volume setting |
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* 27db~-18db, 3db/step, for example: |
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* 0x0: -18dB |
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* 0xf: 27dB |
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*/ |
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static const DECLARE_TLV_DB_MINMAX(rk817_gain_tlv, -1800, 2700); |
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static const struct snd_kcontrol_new rk817_volume_controls[] = { |
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SOC_DOUBLE_R_RANGE_TLV("Master Playback Volume", RK817_CODEC_DDAC_VOLL, |
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RK817_CODEC_DDAC_VOLR, 0, 0x00, 0xff, 1, rk817_vol_tlv), |
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SOC_DOUBLE_R_RANGE_TLV("Master Capture Volume", RK817_CODEC_DADC_VOLL, |
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RK817_CODEC_DADC_VOLR, 0, 0x00, 0xff, 1, rk817_vol_tlv), |
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SOC_DOUBLE_TLV("Mic Capture Gain", RK817_CODEC_DMIC_PGA_GAIN, 4, 0, 0xf, 0, |
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rk817_gain_tlv), |
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}; |
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/* Since the speaker output and L headphone pin are internally the same, make audio path mutually |
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* exclusive with a mux. |
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*/ |
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static const char *dac_mux_text[] = { |
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"HP", |
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"SPK", |
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}; |
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static SOC_ENUM_SINGLE_VIRT_DECL(dac_enum, dac_mux_text); |
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static const struct snd_kcontrol_new dac_mux = |
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SOC_DAPM_ENUM("Playback Mux", dac_enum); |
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static const struct snd_soc_dapm_widget rk817_dapm_widgets[] = { |
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/* capture/playback common */ |
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SND_SOC_DAPM_SUPPLY("LDO Regulator", RK817_CODEC_AREF_RTCFG1, 6, 0, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("IBIAS Block", RK817_CODEC_AREF_RTCFG1, 2, 1, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("VAvg Buffer", RK817_CODEC_AREF_RTCFG1, 1, 1, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("PLL Power", RK817_CODEC_APLL_CFG5, 0, 1, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("I2S TX1 Transfer Start", RK817_CODEC_DI2S_RXCMD_TSD, 5, 0, NULL, 0), |
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/* capture path common */ |
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SND_SOC_DAPM_SUPPLY("ADC Clock", RK817_CODEC_DTOP_DIGEN_CLKE, 7, 0, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("I2S TX Clock", RK817_CODEC_DTOP_DIGEN_CLKE, 6, 0, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("ADC Channel Enable", RK817_CODEC_DTOP_DIGEN_CLKE, 5, 0, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("I2S TX Channel Enable", RK817_CODEC_DTOP_DIGEN_CLKE, 4, 0, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("MIC Power On", RK817_CODEC_AMIC_CFG0, 6, 1, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("I2S TX3 Transfer Start", RK817_CODEC_DI2S_TXCR3_TXCMD, 7, 0, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("I2S TX3 Right Justified", RK817_CODEC_DI2S_TXCR3_TXCMD, 3, 0, NULL, 0), |
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/* capture path L */ |
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SND_SOC_DAPM_ADC("ADC L", "Capture", RK817_CODEC_AADC_CFG0, 7, 1), |
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SND_SOC_DAPM_SUPPLY("PGA L Power On", RK817_CODEC_AMIC_CFG0, 5, 1, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("Mic Boost L1", RK817_CODEC_AMIC_CFG0, 3, 0, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("Mic Boost L2", RK817_CODEC_AMIC_CFG0, 2, 0, NULL, 0), |
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/* capture path R */ |
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SND_SOC_DAPM_ADC("ADC R", "Capture", RK817_CODEC_AADC_CFG0, 6, 1), |
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SND_SOC_DAPM_SUPPLY("PGA R Power On", RK817_CODEC_AMIC_CFG0, 4, 1, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("Mic Boost R1", RK817_CODEC_AMIC_CFG0, 3, 0, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("Mic Boost R2", RK817_CODEC_AMIC_CFG0, 3, 0, NULL, 0), |
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/* playback path common */ |
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SND_SOC_DAPM_SUPPLY("DAC Clock", RK817_CODEC_DTOP_DIGEN_CLKE, 3, 0, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("I2S RX Clock", RK817_CODEC_DTOP_DIGEN_CLKE, 2, 0, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("DAC Channel Enable", RK817_CODEC_DTOP_DIGEN_CLKE, 1, 0, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("I2S RX Channel Enable", RK817_CODEC_DTOP_DIGEN_CLKE, 0, 0, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("DAC Bias", RK817_CODEC_ADAC_CFG1, 3, 1, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("DAC Mute Off", RK817_CODEC_DDAC_MUTE_MIXCTL, 0, 1, NULL, 0), |
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/* playback path speaker */ |
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SND_SOC_DAPM_SUPPLY("Class D Mode", RK817_CODEC_DDAC_MUTE_MIXCTL, 4, 0, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("High Pass Filter", RK817_CODEC_DDAC_MUTE_MIXCTL, 7, 0, NULL, 0), |
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SND_SOC_DAPM_DAC("SPK DAC", "Playback", RK817_CODEC_ADAC_CFG1, 2, 1), |
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SND_SOC_DAPM_SUPPLY("Enable Class D", RK817_CODEC_ACLASSD_CFG1, 7, 0, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("Disable Class D Mute Ramp", RK817_CODEC_ACLASSD_CFG1, 6, 1, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("Class D Mute Rate 1", RK817_CODEC_ACLASSD_CFG1, 3, 0, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("Class D Mute Rate 2", RK817_CODEC_ACLASSD_CFG1, 2, 1, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("Class D OCPP 2", RK817_CODEC_ACLASSD_CFG2, 5, 0, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("Class D OCPP 3", RK817_CODEC_ACLASSD_CFG2, 4, 0, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("Class D OCPN 2", RK817_CODEC_ACLASSD_CFG2, 1, 0, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("Class D OCPN 3", RK817_CODEC_ACLASSD_CFG2, 0, 0, NULL, 0), |
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/* playback path headphones */ |
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SND_SOC_DAPM_SUPPLY("Headphone Charge Pump", RK817_CODEC_AHP_CP, 4, 0, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("Headphone CP Discharge LDO", RK817_CODEC_AHP_CP, 3, 1, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("Headphone OStage", RK817_CODEC_AHP_CFG0, 6, 1, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("Headphone Pre Amp", RK817_CODEC_AHP_CFG0, 5, 1, NULL, 0), |
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SND_SOC_DAPM_DAC("DAC L", "Playback", RK817_CODEC_ADAC_CFG1, 1, 1), |
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SND_SOC_DAPM_DAC("DAC R", "Playback", RK817_CODEC_ADAC_CFG1, 0, 1), |
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/* Mux for input/output path selection */ |
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SND_SOC_DAPM_MUX("Playback Mux", SND_SOC_NOPM, 1, 0, &dac_mux), |
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/* Pins for Simple Card Bindings */ |
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SND_SOC_DAPM_INPUT("MICL"), |
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SND_SOC_DAPM_INPUT("MICR"), |
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SND_SOC_DAPM_OUTPUT("HPOL"), |
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SND_SOC_DAPM_OUTPUT("HPOR"), |
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SND_SOC_DAPM_OUTPUT("SPKO"), |
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}; |
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static const struct snd_soc_dapm_route rk817_dapm_routes[] = { |
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/* capture path */ |
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/* left mic */ |
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{"ADC L", NULL, "LDO Regulator"}, |
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{"ADC L", NULL, "IBIAS Block"}, |
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{"ADC L", NULL, "VAvg Buffer"}, |
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{"ADC L", NULL, "PLL Power"}, |
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{"ADC L", NULL, "ADC Clock"}, |
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{"ADC L", NULL, "I2S TX Clock"}, |
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{"ADC L", NULL, "ADC Channel Enable"}, |
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{"ADC L", NULL, "I2S TX Channel Enable"}, |
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{"ADC L", NULL, "I2S TX1 Transfer Start"}, |
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{"MICL", NULL, "MIC Power On"}, |
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{"MICL", NULL, "PGA L Power On"}, |
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{"MICL", NULL, "Mic Boost L1"}, |
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{"MICL", NULL, "Mic Boost L2"}, |
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{"MICL", NULL, "I2S TX3 Transfer Start"}, |
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{"MICL", NULL, "I2S TX3 Right Justified"}, |
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{"ADC L", NULL, "MICL"}, |
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/* right mic */ |
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{"ADC R", NULL, "LDO Regulator"}, |
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{"ADC R", NULL, "IBIAS Block"}, |
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{"ADC R", NULL, "VAvg Buffer"}, |
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{"ADC R", NULL, "PLL Power"}, |
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{"ADC R", NULL, "ADC Clock"}, |
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{"ADC R", NULL, "I2S TX Clock"}, |
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{"ADC R", NULL, "ADC Channel Enable"}, |
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{"ADC R", NULL, "I2S TX Channel Enable"}, |
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{"ADC R", NULL, "I2S TX1 Transfer Start"}, |
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{"MICR", NULL, "MIC Power On"}, |
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{"MICR", NULL, "PGA R Power On"}, |
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{"MICR", NULL, "Mic Boost R1"}, |
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{"MICR", NULL, "Mic Boost R2"}, |
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{"MICR", NULL, "I2S TX3 Transfer Start"}, |
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{"MICR", NULL, "I2S TX3 Right Justified"}, |
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{"ADC R", NULL, "MICR"}, |
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/* playback path */ |
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/* speaker path */ |
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{"SPK DAC", NULL, "LDO Regulator"}, |
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{"SPK DAC", NULL, "IBIAS Block"}, |
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{"SPK DAC", NULL, "VAvg Buffer"}, |
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{"SPK DAC", NULL, "PLL Power"}, |
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{"SPK DAC", NULL, "I2S TX1 Transfer Start"}, |
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{"SPK DAC", NULL, "DAC Clock"}, |
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{"SPK DAC", NULL, "I2S RX Clock"}, |
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{"SPK DAC", NULL, "DAC Channel Enable"}, |
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{"SPK DAC", NULL, "I2S RX Channel Enable"}, |
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{"SPK DAC", NULL, "Class D Mode"}, |
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{"SPK DAC", NULL, "DAC Bias"}, |
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{"SPK DAC", NULL, "DAC Mute Off"}, |
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{"SPK DAC", NULL, "Enable Class D"}, |
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{"SPK DAC", NULL, "Disable Class D Mute Ramp"}, |
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{"SPK DAC", NULL, "Class D Mute Rate 1"}, |
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{"SPK DAC", NULL, "Class D Mute Rate 2"}, |
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{"SPK DAC", NULL, "Class D OCPP 2"}, |
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{"SPK DAC", NULL, "Class D OCPP 3"}, |
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{"SPK DAC", NULL, "Class D OCPN 2"}, |
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{"SPK DAC", NULL, "Class D OCPN 3"}, |
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{"SPK DAC", NULL, "High Pass Filter"}, |
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/* headphone path L */ |
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{"DAC L", NULL, "LDO Regulator"}, |
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{"DAC L", NULL, "IBIAS Block"}, |
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{"DAC L", NULL, "VAvg Buffer"}, |
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{"DAC L", NULL, "PLL Power"}, |
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{"DAC L", NULL, "I2S TX1 Transfer Start"}, |
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{"DAC L", NULL, "DAC Clock"}, |
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{"DAC L", NULL, "I2S RX Clock"}, |
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{"DAC L", NULL, "DAC Channel Enable"}, |
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{"DAC L", NULL, "I2S RX Channel Enable"}, |
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{"DAC L", NULL, "DAC Bias"}, |
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{"DAC L", NULL, "DAC Mute Off"}, |
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{"DAC L", NULL, "Headphone Charge Pump"}, |
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{"DAC L", NULL, "Headphone CP Discharge LDO"}, |
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{"DAC L", NULL, "Headphone OStage"}, |
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{"DAC L", NULL, "Headphone Pre Amp"}, |
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/* headphone path R */ |
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{"DAC R", NULL, "LDO Regulator"}, |
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{"DAC R", NULL, "IBIAS Block"}, |
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{"DAC R", NULL, "VAvg Buffer"}, |
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{"DAC R", NULL, "PLL Power"}, |
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{"DAC R", NULL, "I2S TX1 Transfer Start"}, |
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{"DAC R", NULL, "DAC Clock"}, |
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{"DAC R", NULL, "I2S RX Clock"}, |
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{"DAC R", NULL, "DAC Channel Enable"}, |
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{"DAC R", NULL, "I2S RX Channel Enable"}, |
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{"DAC R", NULL, "DAC Bias"}, |
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{"DAC R", NULL, "DAC Mute Off"}, |
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{"DAC R", NULL, "Headphone Charge Pump"}, |
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{"DAC R", NULL, "Headphone CP Discharge LDO"}, |
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{"DAC R", NULL, "Headphone OStage"}, |
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{"DAC R", NULL, "Headphone Pre Amp"}, |
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/* mux path for output selection */ |
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{"Playback Mux", "HP", "DAC L"}, |
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{"Playback Mux", "HP", "DAC R"}, |
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{"Playback Mux", "SPK", "SPK DAC"}, |
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{"SPKO", NULL, "Playback Mux"}, |
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{"HPOL", NULL, "Playback Mux"}, |
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{"HPOR", NULL, "Playback Mux"}, |
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}; |
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static int rk817_set_dai_sysclk(struct snd_soc_dai *codec_dai, |
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int clk_id, unsigned int freq, int dir) |
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{ |
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struct snd_soc_component *component = codec_dai->component; |
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struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component); |
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rk817->stereo_sysclk = freq; |
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return 0; |
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} |
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static int rk817_set_dai_fmt(struct snd_soc_dai *codec_dai, |
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unsigned int fmt) |
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{ |
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struct snd_soc_component *component = codec_dai->component; |
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unsigned int i2s_mst = 0; |
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
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case SND_SOC_DAIFMT_CBS_CFS: |
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i2s_mst |= RK817_I2S_MODE_SLV; |
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break; |
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case SND_SOC_DAIFMT_CBM_CFM: |
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i2s_mst |= RK817_I2S_MODE_MST; |
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break; |
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default: |
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dev_err(component->dev, "%s : set master mask failed!\n", __func__); |
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return -EINVAL; |
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} |
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snd_soc_component_update_bits(component, RK817_CODEC_DI2S_CKM, |
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RK817_I2S_MODE_MASK, i2s_mst); |
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return 0; |
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} |
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static int rk817_hw_params(struct snd_pcm_substream *substream, |
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struct snd_pcm_hw_params *params, |
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struct snd_soc_dai *dai) |
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{ |
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struct snd_soc_component *component = dai->component; |
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switch (params_format(params)) { |
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case SNDRV_PCM_FORMAT_S16_LE: |
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snd_soc_component_write(component, RK817_CODEC_DI2S_RXCR2, |
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VDW_RX_16BITS); |
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snd_soc_component_write(component, RK817_CODEC_DI2S_TXCR2, |
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VDW_TX_16BITS); |
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break; |
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case SNDRV_PCM_FORMAT_S24_LE: |
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case SNDRV_PCM_FORMAT_S32_LE: |
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snd_soc_component_write(component, RK817_CODEC_DI2S_RXCR2, |
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VDW_RX_24BITS); |
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snd_soc_component_write(component, RK817_CODEC_DI2S_TXCR2, |
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VDW_TX_24BITS); |
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break; |
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default: |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static int rk817_digital_mute(struct snd_soc_dai *dai, int mute, int stream) |
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{ |
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struct snd_soc_component *component = dai->component; |
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if (mute) |
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snd_soc_component_update_bits(component, |
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RK817_CODEC_DDAC_MUTE_MIXCTL, |
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DACMT_MASK, DACMT_ENABLE); |
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else |
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snd_soc_component_update_bits(component, |
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RK817_CODEC_DDAC_MUTE_MIXCTL, |
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DACMT_MASK, DACMT_DISABLE); |
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return 0; |
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} |
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#define RK817_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\ |
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SNDRV_PCM_RATE_16000 | \ |
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SNDRV_PCM_RATE_32000 | \ |
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SNDRV_PCM_RATE_44100 | \ |
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SNDRV_PCM_RATE_48000 | \ |
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SNDRV_PCM_RATE_96000) |
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#define RK817_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\ |
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SNDRV_PCM_RATE_16000 | \ |
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SNDRV_PCM_RATE_32000 | \ |
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SNDRV_PCM_RATE_44100 | \ |
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SNDRV_PCM_RATE_48000 | \ |
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SNDRV_PCM_RATE_96000) |
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#define RK817_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ |
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SNDRV_PCM_FMTBIT_S20_3LE |\ |
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SNDRV_PCM_FMTBIT_S24_LE |\ |
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SNDRV_PCM_FMTBIT_S32_LE) |
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static const struct snd_soc_dai_ops rk817_dai_ops = { |
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.hw_params = rk817_hw_params, |
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.set_fmt = rk817_set_dai_fmt, |
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.set_sysclk = rk817_set_dai_sysclk, |
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.mute_stream = rk817_digital_mute, |
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.no_capture_mute = 1, |
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}; |
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static struct snd_soc_dai_driver rk817_dai[] = { |
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{ |
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.name = "rk817-hifi", |
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.playback = { |
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.stream_name = "Playback", |
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.channels_min = 2, |
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.channels_max = 8, |
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.rates = RK817_PLAYBACK_RATES, |
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.formats = RK817_FORMATS, |
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}, |
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.capture = { |
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.stream_name = "Capture", |
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.channels_min = 1, |
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.channels_max = 2, |
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.rates = RK817_CAPTURE_RATES, |
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.formats = RK817_FORMATS, |
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}, |
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.ops = &rk817_dai_ops, |
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}, |
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}; |
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static int rk817_probe(struct snd_soc_component *component) |
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{ |
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struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component); |
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struct rk808 *rk808 = dev_get_drvdata(component->dev->parent); |
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|
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snd_soc_component_init_regmap(component, rk808->regmap); |
|
rk817->component = component; |
|
|
|
snd_soc_component_write(component, RK817_CODEC_DTOP_LPT_SRST, 0x40); |
|
|
|
rk817_init(component); |
|
|
|
/* setting initial pll values so that we can continue to leverage simple-audio-card. |
|
* The values aren't important since no parameters are used. |
|
*/ |
|
|
|
snd_soc_component_set_pll(component, 0, 0, 0, 0); |
|
|
|
return 0; |
|
} |
|
|
|
static void rk817_remove(struct snd_soc_component *component) |
|
{ |
|
snd_soc_component_exit_regmap(component); |
|
} |
|
|
|
static const struct snd_soc_component_driver soc_codec_dev_rk817 = { |
|
.probe = rk817_probe, |
|
.remove = rk817_remove, |
|
.idle_bias_on = 1, |
|
.use_pmdown_time = 1, |
|
.endianness = 1, |
|
.controls = rk817_volume_controls, |
|
.num_controls = ARRAY_SIZE(rk817_volume_controls), |
|
.dapm_routes = rk817_dapm_routes, |
|
.num_dapm_routes = ARRAY_SIZE(rk817_dapm_routes), |
|
.dapm_widgets = rk817_dapm_widgets, |
|
.num_dapm_widgets = ARRAY_SIZE(rk817_dapm_widgets), |
|
.set_pll = rk817_set_component_pll, |
|
}; |
|
|
|
static void rk817_codec_parse_dt_property(struct device *dev, |
|
struct rk817_codec_priv *rk817) |
|
{ |
|
struct device_node *node; |
|
|
|
node = of_get_child_by_name(dev->parent->of_node, "codec"); |
|
if (!node) { |
|
dev_dbg(dev, "%s() Can not get child: codec\n", |
|
__func__); |
|
} |
|
|
|
rk817->mic_in_differential = |
|
of_property_read_bool(node, "rockchip,mic-in-differential"); |
|
|
|
of_node_put(node); |
|
} |
|
|
|
static int rk817_platform_probe(struct platform_device *pdev) |
|
{ |
|
struct rk808 *rk808 = dev_get_drvdata(pdev->dev.parent); |
|
struct rk817_codec_priv *rk817_codec_data; |
|
int ret; |
|
|
|
rk817_codec_data = devm_kzalloc(&pdev->dev, |
|
sizeof(struct rk817_codec_priv), |
|
GFP_KERNEL); |
|
if (!rk817_codec_data) |
|
return -ENOMEM; |
|
|
|
platform_set_drvdata(pdev, rk817_codec_data); |
|
|
|
rk817_codec_data->rk808 = rk808; |
|
|
|
rk817_codec_parse_dt_property(&pdev->dev, rk817_codec_data); |
|
|
|
rk817_codec_data->mclk = devm_clk_get(pdev->dev.parent, "mclk"); |
|
if (IS_ERR(rk817_codec_data->mclk)) { |
|
dev_dbg(&pdev->dev, "Unable to get mclk\n"); |
|
ret = -ENXIO; |
|
goto err_; |
|
} |
|
|
|
ret = clk_prepare_enable(rk817_codec_data->mclk); |
|
if (ret < 0) { |
|
dev_err(&pdev->dev, "%s() clock prepare error %d\n", |
|
__func__, ret); |
|
goto err_; |
|
} |
|
|
|
ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_rk817, |
|
rk817_dai, ARRAY_SIZE(rk817_dai)); |
|
if (ret < 0) { |
|
dev_err(&pdev->dev, "%s() register codec error %d\n", |
|
__func__, ret); |
|
goto err_clk; |
|
} |
|
|
|
return 0; |
|
|
|
err_clk: |
|
clk_disable_unprepare(rk817_codec_data->mclk); |
|
err_: |
|
return ret; |
|
} |
|
|
|
static int rk817_platform_remove(struct platform_device *pdev) |
|
{ |
|
struct rk817_codec_priv *rk817 = platform_get_drvdata(pdev); |
|
|
|
clk_disable_unprepare(rk817->mclk); |
|
|
|
return 0; |
|
} |
|
|
|
static struct platform_driver rk817_codec_driver = { |
|
.driver = { |
|
.name = "rk817-codec", |
|
}, |
|
.probe = rk817_platform_probe, |
|
.remove = rk817_platform_remove, |
|
}; |
|
|
|
module_platform_driver(rk817_codec_driver); |
|
|
|
MODULE_DESCRIPTION("ASoC RK817 codec driver"); |
|
MODULE_AUTHOR("binyuan <[email protected]>"); |
|
MODULE_LICENSE("GPL v2"); |
|
MODULE_ALIAS("platform:rk817-codec");
|
|
|