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882 lines
24 KiB
882 lines
24 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* ADAV80X Audio Codec driver supporting ADAV801, ADAV803 |
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* |
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* Copyright 2011 Analog Devices Inc. |
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* Author: Yi Li <[email protected]> |
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* Author: Lars-Peter Clausen <[email protected]> |
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*/ |
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/regmap.h> |
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#include <linux/slab.h> |
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#include <sound/pcm.h> |
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#include <sound/pcm_params.h> |
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#include <sound/soc.h> |
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#include <sound/tlv.h> |
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#include "adav80x.h" |
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#define ADAV80X_PLAYBACK_CTRL 0x04 |
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#define ADAV80X_AUX_IN_CTRL 0x05 |
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#define ADAV80X_REC_CTRL 0x06 |
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#define ADAV80X_AUX_OUT_CTRL 0x07 |
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#define ADAV80X_DPATH_CTRL1 0x62 |
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#define ADAV80X_DPATH_CTRL2 0x63 |
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#define ADAV80X_DAC_CTRL1 0x64 |
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#define ADAV80X_DAC_CTRL2 0x65 |
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#define ADAV80X_DAC_CTRL3 0x66 |
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#define ADAV80X_DAC_L_VOL 0x68 |
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#define ADAV80X_DAC_R_VOL 0x69 |
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#define ADAV80X_PGA_L_VOL 0x6c |
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#define ADAV80X_PGA_R_VOL 0x6d |
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#define ADAV80X_ADC_CTRL1 0x6e |
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#define ADAV80X_ADC_CTRL2 0x6f |
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#define ADAV80X_ADC_L_VOL 0x70 |
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#define ADAV80X_ADC_R_VOL 0x71 |
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#define ADAV80X_PLL_CTRL1 0x74 |
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#define ADAV80X_PLL_CTRL2 0x75 |
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#define ADAV80X_ICLK_CTRL1 0x76 |
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#define ADAV80X_ICLK_CTRL2 0x77 |
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#define ADAV80X_PLL_CLK_SRC 0x78 |
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#define ADAV80X_PLL_OUTE 0x7a |
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#define ADAV80X_PLL_CLK_SRC_PLL_XIN(pll) 0x00 |
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#define ADAV80X_PLL_CLK_SRC_PLL_MCLKI(pll) (0x40 << (pll)) |
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#define ADAV80X_PLL_CLK_SRC_PLL_MASK(pll) (0x40 << (pll)) |
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#define ADAV80X_ICLK_CTRL1_DAC_SRC(src) ((src) << 5) |
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#define ADAV80X_ICLK_CTRL1_ADC_SRC(src) ((src) << 2) |
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#define ADAV80X_ICLK_CTRL1_ICLK2_SRC(src) (src) |
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#define ADAV80X_ICLK_CTRL2_ICLK1_SRC(src) ((src) << 3) |
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#define ADAV80X_PLL_CTRL1_PLLDIV 0x10 |
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#define ADAV80X_PLL_CTRL1_PLLPD(pll) (0x04 << (pll)) |
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#define ADAV80X_PLL_CTRL1_XTLPD 0x02 |
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#define ADAV80X_PLL_CTRL2_FIELD(pll, x) ((x) << ((pll) * 4)) |
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#define ADAV80X_PLL_CTRL2_FS_48(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x00) |
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#define ADAV80X_PLL_CTRL2_FS_32(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x08) |
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#define ADAV80X_PLL_CTRL2_FS_44(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x0c) |
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#define ADAV80X_PLL_CTRL2_SEL(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x02) |
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#define ADAV80X_PLL_CTRL2_DOUB(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x01) |
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#define ADAV80X_PLL_CTRL2_PLL_MASK(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x0f) |
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#define ADAV80X_ADC_CTRL1_MODULATOR_MASK 0x80 |
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#define ADAV80X_ADC_CTRL1_MODULATOR_128FS 0x00 |
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#define ADAV80X_ADC_CTRL1_MODULATOR_64FS 0x80 |
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#define ADAV80X_DAC_CTRL1_PD 0x80 |
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#define ADAV80X_DAC_CTRL2_DIV1 0x00 |
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#define ADAV80X_DAC_CTRL2_DIV1_5 0x10 |
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#define ADAV80X_DAC_CTRL2_DIV2 0x20 |
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#define ADAV80X_DAC_CTRL2_DIV3 0x30 |
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#define ADAV80X_DAC_CTRL2_DIV_MASK 0x30 |
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#define ADAV80X_DAC_CTRL2_INTERPOL_256FS 0x00 |
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#define ADAV80X_DAC_CTRL2_INTERPOL_128FS 0x40 |
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#define ADAV80X_DAC_CTRL2_INTERPOL_64FS 0x80 |
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#define ADAV80X_DAC_CTRL2_INTERPOL_MASK 0xc0 |
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#define ADAV80X_DAC_CTRL2_DEEMPH_NONE 0x00 |
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#define ADAV80X_DAC_CTRL2_DEEMPH_44 0x01 |
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#define ADAV80X_DAC_CTRL2_DEEMPH_32 0x02 |
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#define ADAV80X_DAC_CTRL2_DEEMPH_48 0x03 |
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#define ADAV80X_DAC_CTRL2_DEEMPH_MASK 0x01 |
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#define ADAV80X_CAPTURE_MODE_MASTER 0x20 |
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#define ADAV80X_CAPTURE_WORD_LEN24 0x00 |
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#define ADAV80X_CAPTURE_WORD_LEN20 0x04 |
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#define ADAV80X_CAPTRUE_WORD_LEN18 0x08 |
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#define ADAV80X_CAPTURE_WORD_LEN16 0x0c |
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#define ADAV80X_CAPTURE_WORD_LEN_MASK 0x0c |
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#define ADAV80X_CAPTURE_MODE_LEFT_J 0x00 |
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#define ADAV80X_CAPTURE_MODE_I2S 0x01 |
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#define ADAV80X_CAPTURE_MODE_RIGHT_J 0x03 |
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#define ADAV80X_CAPTURE_MODE_MASK 0x03 |
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#define ADAV80X_PLAYBACK_MODE_MASTER 0x10 |
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#define ADAV80X_PLAYBACK_MODE_LEFT_J 0x00 |
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#define ADAV80X_PLAYBACK_MODE_I2S 0x01 |
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#define ADAV80X_PLAYBACK_MODE_RIGHT_J_24 0x04 |
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#define ADAV80X_PLAYBACK_MODE_RIGHT_J_20 0x05 |
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#define ADAV80X_PLAYBACK_MODE_RIGHT_J_18 0x06 |
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#define ADAV80X_PLAYBACK_MODE_RIGHT_J_16 0x07 |
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#define ADAV80X_PLAYBACK_MODE_MASK 0x07 |
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#define ADAV80X_PLL_OUTE_SYSCLKPD(x) BIT(2 - (x)) |
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static const struct reg_default adav80x_reg_defaults[] = { |
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{ ADAV80X_PLAYBACK_CTRL, 0x01 }, |
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{ ADAV80X_AUX_IN_CTRL, 0x01 }, |
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{ ADAV80X_REC_CTRL, 0x02 }, |
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{ ADAV80X_AUX_OUT_CTRL, 0x01 }, |
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{ ADAV80X_DPATH_CTRL1, 0xc0 }, |
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{ ADAV80X_DPATH_CTRL2, 0x11 }, |
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{ ADAV80X_DAC_CTRL1, 0x00 }, |
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{ ADAV80X_DAC_CTRL2, 0x00 }, |
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{ ADAV80X_DAC_CTRL3, 0x00 }, |
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{ ADAV80X_DAC_L_VOL, 0xff }, |
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{ ADAV80X_DAC_R_VOL, 0xff }, |
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{ ADAV80X_PGA_L_VOL, 0x00 }, |
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{ ADAV80X_PGA_R_VOL, 0x00 }, |
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{ ADAV80X_ADC_CTRL1, 0x00 }, |
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{ ADAV80X_ADC_CTRL2, 0x00 }, |
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{ ADAV80X_ADC_L_VOL, 0xff }, |
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{ ADAV80X_ADC_R_VOL, 0xff }, |
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{ ADAV80X_PLL_CTRL1, 0x00 }, |
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{ ADAV80X_PLL_CTRL2, 0x00 }, |
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{ ADAV80X_ICLK_CTRL1, 0x00 }, |
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{ ADAV80X_ICLK_CTRL2, 0x00 }, |
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{ ADAV80X_PLL_CLK_SRC, 0x00 }, |
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{ ADAV80X_PLL_OUTE, 0x00 }, |
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}; |
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struct adav80x { |
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struct regmap *regmap; |
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enum adav80x_clk_src clk_src; |
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unsigned int sysclk; |
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enum adav80x_pll_src pll_src; |
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unsigned int dai_fmt[2]; |
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unsigned int rate; |
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bool deemph; |
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bool sysclk_pd[3]; |
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}; |
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static const char *adav80x_mux_text[] = { |
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"ADC", |
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"Playback", |
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"Aux Playback", |
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}; |
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static const unsigned int adav80x_mux_values[] = { |
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0, 2, 3, |
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}; |
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#define ADAV80X_MUX_ENUM_DECL(name, reg, shift) \ |
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SOC_VALUE_ENUM_DOUBLE_DECL(name, reg, shift, 7, \ |
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ARRAY_SIZE(adav80x_mux_text), adav80x_mux_text, \ |
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adav80x_mux_values) |
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static ADAV80X_MUX_ENUM_DECL(adav80x_aux_capture_enum, ADAV80X_DPATH_CTRL1, 0); |
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static ADAV80X_MUX_ENUM_DECL(adav80x_capture_enum, ADAV80X_DPATH_CTRL1, 3); |
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static ADAV80X_MUX_ENUM_DECL(adav80x_dac_enum, ADAV80X_DPATH_CTRL2, 3); |
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static const struct snd_kcontrol_new adav80x_aux_capture_mux_ctrl = |
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SOC_DAPM_ENUM("Route", adav80x_aux_capture_enum); |
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static const struct snd_kcontrol_new adav80x_capture_mux_ctrl = |
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SOC_DAPM_ENUM("Route", adav80x_capture_enum); |
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static const struct snd_kcontrol_new adav80x_dac_mux_ctrl = |
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SOC_DAPM_ENUM("Route", adav80x_dac_enum); |
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#define ADAV80X_MUX(name, ctrl) \ |
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SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, 0, 0, ctrl) |
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static const struct snd_soc_dapm_widget adav80x_dapm_widgets[] = { |
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SND_SOC_DAPM_DAC("DAC", NULL, ADAV80X_DAC_CTRL1, 7, 1), |
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SND_SOC_DAPM_ADC("ADC", NULL, ADAV80X_ADC_CTRL1, 5, 1), |
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SND_SOC_DAPM_PGA("Right PGA", ADAV80X_ADC_CTRL1, 0, 1, NULL, 0), |
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SND_SOC_DAPM_PGA("Left PGA", ADAV80X_ADC_CTRL1, 1, 1, NULL, 0), |
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SND_SOC_DAPM_AIF_OUT("AIFOUT", "HiFi Capture", 0, SND_SOC_NOPM, 0, 0), |
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SND_SOC_DAPM_AIF_IN("AIFIN", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0), |
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SND_SOC_DAPM_AIF_OUT("AIFAUXOUT", "Aux Capture", 0, SND_SOC_NOPM, 0, 0), |
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SND_SOC_DAPM_AIF_IN("AIFAUXIN", "Aux Playback", 0, SND_SOC_NOPM, 0, 0), |
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ADAV80X_MUX("Aux Capture Select", &adav80x_aux_capture_mux_ctrl), |
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ADAV80X_MUX("Capture Select", &adav80x_capture_mux_ctrl), |
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ADAV80X_MUX("DAC Select", &adav80x_dac_mux_ctrl), |
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SND_SOC_DAPM_INPUT("VINR"), |
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SND_SOC_DAPM_INPUT("VINL"), |
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SND_SOC_DAPM_OUTPUT("VOUTR"), |
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SND_SOC_DAPM_OUTPUT("VOUTL"), |
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SND_SOC_DAPM_SUPPLY("SYSCLK", SND_SOC_NOPM, 0, 0, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("PLL1", ADAV80X_PLL_CTRL1, 2, 1, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("PLL2", ADAV80X_PLL_CTRL1, 3, 1, NULL, 0), |
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SND_SOC_DAPM_SUPPLY("OSC", ADAV80X_PLL_CTRL1, 1, 1, NULL, 0), |
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}; |
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static int adav80x_dapm_sysclk_check(struct snd_soc_dapm_widget *source, |
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struct snd_soc_dapm_widget *sink) |
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{ |
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struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); |
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struct adav80x *adav80x = snd_soc_component_get_drvdata(component); |
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const char *clk; |
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switch (adav80x->clk_src) { |
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case ADAV80X_CLK_PLL1: |
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clk = "PLL1"; |
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break; |
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case ADAV80X_CLK_PLL2: |
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clk = "PLL2"; |
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break; |
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case ADAV80X_CLK_XTAL: |
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clk = "OSC"; |
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break; |
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default: |
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return 0; |
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} |
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return strcmp(source->name, clk) == 0; |
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} |
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static int adav80x_dapm_pll_check(struct snd_soc_dapm_widget *source, |
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struct snd_soc_dapm_widget *sink) |
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{ |
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struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); |
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struct adav80x *adav80x = snd_soc_component_get_drvdata(component); |
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return adav80x->pll_src == ADAV80X_PLL_SRC_XTAL; |
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} |
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static const struct snd_soc_dapm_route adav80x_dapm_routes[] = { |
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{ "DAC Select", "ADC", "ADC" }, |
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{ "DAC Select", "Playback", "AIFIN" }, |
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{ "DAC Select", "Aux Playback", "AIFAUXIN" }, |
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{ "DAC", NULL, "DAC Select" }, |
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{ "Capture Select", "ADC", "ADC" }, |
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{ "Capture Select", "Playback", "AIFIN" }, |
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{ "Capture Select", "Aux Playback", "AIFAUXIN" }, |
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{ "AIFOUT", NULL, "Capture Select" }, |
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{ "Aux Capture Select", "ADC", "ADC" }, |
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{ "Aux Capture Select", "Playback", "AIFIN" }, |
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{ "Aux Capture Select", "Aux Playback", "AIFAUXIN" }, |
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{ "AIFAUXOUT", NULL, "Aux Capture Select" }, |
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{ "VOUTR", NULL, "DAC" }, |
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{ "VOUTL", NULL, "DAC" }, |
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{ "Left PGA", NULL, "VINL" }, |
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{ "Right PGA", NULL, "VINR" }, |
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{ "ADC", NULL, "Left PGA" }, |
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{ "ADC", NULL, "Right PGA" }, |
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{ "SYSCLK", NULL, "PLL1", adav80x_dapm_sysclk_check }, |
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{ "SYSCLK", NULL, "PLL2", adav80x_dapm_sysclk_check }, |
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{ "SYSCLK", NULL, "OSC", adav80x_dapm_sysclk_check }, |
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{ "PLL1", NULL, "OSC", adav80x_dapm_pll_check }, |
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{ "PLL2", NULL, "OSC", adav80x_dapm_pll_check }, |
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{ "ADC", NULL, "SYSCLK" }, |
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{ "DAC", NULL, "SYSCLK" }, |
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{ "AIFOUT", NULL, "SYSCLK" }, |
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{ "AIFAUXOUT", NULL, "SYSCLK" }, |
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{ "AIFIN", NULL, "SYSCLK" }, |
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{ "AIFAUXIN", NULL, "SYSCLK" }, |
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}; |
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static int adav80x_set_deemph(struct snd_soc_component *component) |
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{ |
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struct adav80x *adav80x = snd_soc_component_get_drvdata(component); |
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unsigned int val; |
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if (adav80x->deemph) { |
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switch (adav80x->rate) { |
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case 32000: |
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val = ADAV80X_DAC_CTRL2_DEEMPH_32; |
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break; |
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case 44100: |
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val = ADAV80X_DAC_CTRL2_DEEMPH_44; |
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break; |
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case 48000: |
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case 64000: |
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case 88200: |
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case 96000: |
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val = ADAV80X_DAC_CTRL2_DEEMPH_48; |
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break; |
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default: |
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val = ADAV80X_DAC_CTRL2_DEEMPH_NONE; |
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break; |
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} |
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} else { |
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val = ADAV80X_DAC_CTRL2_DEEMPH_NONE; |
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} |
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return regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL2, |
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ADAV80X_DAC_CTRL2_DEEMPH_MASK, val); |
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} |
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static int adav80x_put_deemph(struct snd_kcontrol *kcontrol, |
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struct snd_ctl_elem_value *ucontrol) |
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{ |
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struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
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struct adav80x *adav80x = snd_soc_component_get_drvdata(component); |
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unsigned int deemph = ucontrol->value.integer.value[0]; |
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if (deemph > 1) |
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return -EINVAL; |
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adav80x->deemph = deemph; |
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return adav80x_set_deemph(component); |
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} |
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static int adav80x_get_deemph(struct snd_kcontrol *kcontrol, |
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struct snd_ctl_elem_value *ucontrol) |
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{ |
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struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
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struct adav80x *adav80x = snd_soc_component_get_drvdata(component); |
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ucontrol->value.integer.value[0] = adav80x->deemph; |
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return 0; |
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}; |
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static const DECLARE_TLV_DB_SCALE(adav80x_inpga_tlv, 0, 50, 0); |
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static const DECLARE_TLV_DB_MINMAX(adav80x_digital_tlv, -9563, 0); |
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static const struct snd_kcontrol_new adav80x_controls[] = { |
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SOC_DOUBLE_R_TLV("Master Playback Volume", ADAV80X_DAC_L_VOL, |
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ADAV80X_DAC_R_VOL, 0, 0xff, 0, adav80x_digital_tlv), |
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SOC_DOUBLE_R_TLV("Master Capture Volume", ADAV80X_ADC_L_VOL, |
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ADAV80X_ADC_R_VOL, 0, 0xff, 0, adav80x_digital_tlv), |
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SOC_DOUBLE_R_TLV("PGA Capture Volume", ADAV80X_PGA_L_VOL, |
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ADAV80X_PGA_R_VOL, 0, 0x30, 0, adav80x_inpga_tlv), |
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SOC_DOUBLE("Master Playback Switch", ADAV80X_DAC_CTRL1, 0, 1, 1, 0), |
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SOC_DOUBLE("Master Capture Switch", ADAV80X_ADC_CTRL1, 2, 3, 1, 1), |
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SOC_SINGLE("ADC High Pass Filter Switch", ADAV80X_ADC_CTRL1, 6, 1, 0), |
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SOC_SINGLE_BOOL_EXT("Playback De-emphasis Switch", 0, |
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adav80x_get_deemph, adav80x_put_deemph), |
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}; |
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static unsigned int adav80x_port_ctrl_regs[2][2] = { |
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{ ADAV80X_REC_CTRL, ADAV80X_PLAYBACK_CTRL, }, |
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{ ADAV80X_AUX_OUT_CTRL, ADAV80X_AUX_IN_CTRL }, |
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}; |
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static int adav80x_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
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{ |
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struct snd_soc_component *component = dai->component; |
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struct adav80x *adav80x = snd_soc_component_get_drvdata(component); |
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unsigned int capture = 0x00; |
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unsigned int playback = 0x00; |
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switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { |
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case SND_SOC_DAIFMT_CBP_CFP: |
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capture |= ADAV80X_CAPTURE_MODE_MASTER; |
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playback |= ADAV80X_PLAYBACK_MODE_MASTER; |
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break; |
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case SND_SOC_DAIFMT_CBC_CFC: |
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break; |
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default: |
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return -EINVAL; |
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} |
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
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case SND_SOC_DAIFMT_I2S: |
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capture |= ADAV80X_CAPTURE_MODE_I2S; |
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playback |= ADAV80X_PLAYBACK_MODE_I2S; |
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break; |
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case SND_SOC_DAIFMT_LEFT_J: |
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capture |= ADAV80X_CAPTURE_MODE_LEFT_J; |
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playback |= ADAV80X_PLAYBACK_MODE_LEFT_J; |
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break; |
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case SND_SOC_DAIFMT_RIGHT_J: |
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capture |= ADAV80X_CAPTURE_MODE_RIGHT_J; |
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playback |= ADAV80X_PLAYBACK_MODE_RIGHT_J_24; |
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break; |
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default: |
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return -EINVAL; |
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} |
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
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case SND_SOC_DAIFMT_NB_NF: |
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break; |
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default: |
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return -EINVAL; |
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} |
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regmap_update_bits(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][0], |
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ADAV80X_CAPTURE_MODE_MASK | ADAV80X_CAPTURE_MODE_MASTER, |
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capture); |
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regmap_write(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][1], |
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playback); |
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adav80x->dai_fmt[dai->id] = fmt & SND_SOC_DAIFMT_FORMAT_MASK; |
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return 0; |
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} |
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static int adav80x_set_adc_clock(struct snd_soc_component *component, |
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unsigned int sample_rate) |
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{ |
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struct adav80x *adav80x = snd_soc_component_get_drvdata(component); |
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unsigned int val; |
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if (sample_rate <= 48000) |
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val = ADAV80X_ADC_CTRL1_MODULATOR_128FS; |
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else |
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val = ADAV80X_ADC_CTRL1_MODULATOR_64FS; |
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regmap_update_bits(adav80x->regmap, ADAV80X_ADC_CTRL1, |
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ADAV80X_ADC_CTRL1_MODULATOR_MASK, val); |
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return 0; |
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} |
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|
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static int adav80x_set_dac_clock(struct snd_soc_component *component, |
|
unsigned int sample_rate) |
|
{ |
|
struct adav80x *adav80x = snd_soc_component_get_drvdata(component); |
|
unsigned int val; |
|
|
|
if (sample_rate <= 48000) |
|
val = ADAV80X_DAC_CTRL2_DIV1 | ADAV80X_DAC_CTRL2_INTERPOL_256FS; |
|
else |
|
val = ADAV80X_DAC_CTRL2_DIV2 | ADAV80X_DAC_CTRL2_INTERPOL_128FS; |
|
|
|
regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL2, |
|
ADAV80X_DAC_CTRL2_DIV_MASK | ADAV80X_DAC_CTRL2_INTERPOL_MASK, |
|
val); |
|
|
|
return 0; |
|
} |
|
|
|
static int adav80x_set_capture_pcm_format(struct snd_soc_component *component, |
|
struct snd_soc_dai *dai, struct snd_pcm_hw_params *params) |
|
{ |
|
struct adav80x *adav80x = snd_soc_component_get_drvdata(component); |
|
unsigned int val; |
|
|
|
switch (params_width(params)) { |
|
case 16: |
|
val = ADAV80X_CAPTURE_WORD_LEN16; |
|
break; |
|
case 18: |
|
val = ADAV80X_CAPTRUE_WORD_LEN18; |
|
break; |
|
case 20: |
|
val = ADAV80X_CAPTURE_WORD_LEN20; |
|
break; |
|
case 24: |
|
val = ADAV80X_CAPTURE_WORD_LEN24; |
|
break; |
|
default: |
|
return -EINVAL; |
|
} |
|
|
|
regmap_update_bits(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][0], |
|
ADAV80X_CAPTURE_WORD_LEN_MASK, val); |
|
|
|
return 0; |
|
} |
|
|
|
static int adav80x_set_playback_pcm_format(struct snd_soc_component *component, |
|
struct snd_soc_dai *dai, struct snd_pcm_hw_params *params) |
|
{ |
|
struct adav80x *adav80x = snd_soc_component_get_drvdata(component); |
|
unsigned int val; |
|
|
|
if (adav80x->dai_fmt[dai->id] != SND_SOC_DAIFMT_RIGHT_J) |
|
return 0; |
|
|
|
switch (params_width(params)) { |
|
case 16: |
|
val = ADAV80X_PLAYBACK_MODE_RIGHT_J_16; |
|
break; |
|
case 18: |
|
val = ADAV80X_PLAYBACK_MODE_RIGHT_J_18; |
|
break; |
|
case 20: |
|
val = ADAV80X_PLAYBACK_MODE_RIGHT_J_20; |
|
break; |
|
case 24: |
|
val = ADAV80X_PLAYBACK_MODE_RIGHT_J_24; |
|
break; |
|
default: |
|
return -EINVAL; |
|
} |
|
|
|
regmap_update_bits(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][1], |
|
ADAV80X_PLAYBACK_MODE_MASK, val); |
|
|
|
return 0; |
|
} |
|
|
|
static int adav80x_hw_params(struct snd_pcm_substream *substream, |
|
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) |
|
{ |
|
struct snd_soc_component *component = dai->component; |
|
struct adav80x *adav80x = snd_soc_component_get_drvdata(component); |
|
unsigned int rate = params_rate(params); |
|
|
|
if (rate * 256 != adav80x->sysclk) |
|
return -EINVAL; |
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
|
adav80x_set_playback_pcm_format(component, dai, params); |
|
adav80x_set_dac_clock(component, rate); |
|
} else { |
|
adav80x_set_capture_pcm_format(component, dai, params); |
|
adav80x_set_adc_clock(component, rate); |
|
} |
|
adav80x->rate = rate; |
|
adav80x_set_deemph(component); |
|
|
|
return 0; |
|
} |
|
|
|
static int adav80x_set_sysclk(struct snd_soc_component *component, |
|
int clk_id, int source, |
|
unsigned int freq, int dir) |
|
{ |
|
struct adav80x *adav80x = snd_soc_component_get_drvdata(component); |
|
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); |
|
|
|
if (dir == SND_SOC_CLOCK_IN) { |
|
switch (clk_id) { |
|
case ADAV80X_CLK_XIN: |
|
case ADAV80X_CLK_XTAL: |
|
case ADAV80X_CLK_MCLKI: |
|
case ADAV80X_CLK_PLL1: |
|
case ADAV80X_CLK_PLL2: |
|
break; |
|
default: |
|
return -EINVAL; |
|
} |
|
|
|
adav80x->sysclk = freq; |
|
|
|
if (adav80x->clk_src != clk_id) { |
|
unsigned int iclk_ctrl1, iclk_ctrl2; |
|
|
|
adav80x->clk_src = clk_id; |
|
if (clk_id == ADAV80X_CLK_XTAL) |
|
clk_id = ADAV80X_CLK_XIN; |
|
|
|
iclk_ctrl1 = ADAV80X_ICLK_CTRL1_DAC_SRC(clk_id) | |
|
ADAV80X_ICLK_CTRL1_ADC_SRC(clk_id) | |
|
ADAV80X_ICLK_CTRL1_ICLK2_SRC(clk_id); |
|
iclk_ctrl2 = ADAV80X_ICLK_CTRL2_ICLK1_SRC(clk_id); |
|
|
|
regmap_write(adav80x->regmap, ADAV80X_ICLK_CTRL1, |
|
iclk_ctrl1); |
|
regmap_write(adav80x->regmap, ADAV80X_ICLK_CTRL2, |
|
iclk_ctrl2); |
|
|
|
snd_soc_dapm_sync(dapm); |
|
} |
|
} else { |
|
unsigned int mask; |
|
|
|
switch (clk_id) { |
|
case ADAV80X_CLK_SYSCLK1: |
|
case ADAV80X_CLK_SYSCLK2: |
|
case ADAV80X_CLK_SYSCLK3: |
|
break; |
|
default: |
|
return -EINVAL; |
|
} |
|
|
|
clk_id -= ADAV80X_CLK_SYSCLK1; |
|
mask = ADAV80X_PLL_OUTE_SYSCLKPD(clk_id); |
|
|
|
if (freq == 0) { |
|
regmap_update_bits(adav80x->regmap, ADAV80X_PLL_OUTE, |
|
mask, mask); |
|
adav80x->sysclk_pd[clk_id] = true; |
|
} else { |
|
regmap_update_bits(adav80x->regmap, ADAV80X_PLL_OUTE, |
|
mask, 0); |
|
adav80x->sysclk_pd[clk_id] = false; |
|
} |
|
|
|
snd_soc_dapm_mutex_lock(dapm); |
|
|
|
if (adav80x->sysclk_pd[0]) |
|
snd_soc_dapm_disable_pin_unlocked(dapm, "PLL1"); |
|
else |
|
snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL1"); |
|
|
|
if (adav80x->sysclk_pd[1] || adav80x->sysclk_pd[2]) |
|
snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2"); |
|
else |
|
snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2"); |
|
|
|
snd_soc_dapm_sync_unlocked(dapm); |
|
|
|
snd_soc_dapm_mutex_unlock(dapm); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int adav80x_set_pll(struct snd_soc_component *component, int pll_id, |
|
int source, unsigned int freq_in, unsigned int freq_out) |
|
{ |
|
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); |
|
struct adav80x *adav80x = snd_soc_component_get_drvdata(component); |
|
unsigned int pll_ctrl1 = 0; |
|
unsigned int pll_ctrl2 = 0; |
|
unsigned int pll_src; |
|
|
|
switch (source) { |
|
case ADAV80X_PLL_SRC_XTAL: |
|
case ADAV80X_PLL_SRC_XIN: |
|
case ADAV80X_PLL_SRC_MCLKI: |
|
break; |
|
default: |
|
return -EINVAL; |
|
} |
|
|
|
if (!freq_out) |
|
return 0; |
|
|
|
switch (freq_in) { |
|
case 27000000: |
|
break; |
|
case 54000000: |
|
if (source == ADAV80X_PLL_SRC_XIN) { |
|
pll_ctrl1 |= ADAV80X_PLL_CTRL1_PLLDIV; |
|
break; |
|
} |
|
fallthrough; |
|
default: |
|
return -EINVAL; |
|
} |
|
|
|
if (freq_out > 12288000) { |
|
pll_ctrl2 |= ADAV80X_PLL_CTRL2_DOUB(pll_id); |
|
freq_out /= 2; |
|
} |
|
|
|
/* freq_out = sample_rate * 256 */ |
|
switch (freq_out) { |
|
case 8192000: |
|
pll_ctrl2 |= ADAV80X_PLL_CTRL2_FS_32(pll_id); |
|
break; |
|
case 11289600: |
|
pll_ctrl2 |= ADAV80X_PLL_CTRL2_FS_44(pll_id); |
|
break; |
|
case 12288000: |
|
pll_ctrl2 |= ADAV80X_PLL_CTRL2_FS_48(pll_id); |
|
break; |
|
default: |
|
return -EINVAL; |
|
} |
|
|
|
regmap_update_bits(adav80x->regmap, ADAV80X_PLL_CTRL1, |
|
ADAV80X_PLL_CTRL1_PLLDIV, pll_ctrl1); |
|
regmap_update_bits(adav80x->regmap, ADAV80X_PLL_CTRL2, |
|
ADAV80X_PLL_CTRL2_PLL_MASK(pll_id), pll_ctrl2); |
|
|
|
if (source != adav80x->pll_src) { |
|
if (source == ADAV80X_PLL_SRC_MCLKI) |
|
pll_src = ADAV80X_PLL_CLK_SRC_PLL_MCLKI(pll_id); |
|
else |
|
pll_src = ADAV80X_PLL_CLK_SRC_PLL_XIN(pll_id); |
|
|
|
regmap_update_bits(adav80x->regmap, ADAV80X_PLL_CLK_SRC, |
|
ADAV80X_PLL_CLK_SRC_PLL_MASK(pll_id), pll_src); |
|
|
|
adav80x->pll_src = source; |
|
|
|
snd_soc_dapm_sync(dapm); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int adav80x_set_bias_level(struct snd_soc_component *component, |
|
enum snd_soc_bias_level level) |
|
{ |
|
struct adav80x *adav80x = snd_soc_component_get_drvdata(component); |
|
unsigned int mask = ADAV80X_DAC_CTRL1_PD; |
|
|
|
switch (level) { |
|
case SND_SOC_BIAS_ON: |
|
break; |
|
case SND_SOC_BIAS_PREPARE: |
|
break; |
|
case SND_SOC_BIAS_STANDBY: |
|
regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL1, mask, |
|
0x00); |
|
break; |
|
case SND_SOC_BIAS_OFF: |
|
regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL1, mask, |
|
mask); |
|
break; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
/* Enforce the same sample rate on all audio interfaces */ |
|
static int adav80x_dai_startup(struct snd_pcm_substream *substream, |
|
struct snd_soc_dai *dai) |
|
{ |
|
struct snd_soc_component *component = dai->component; |
|
struct adav80x *adav80x = snd_soc_component_get_drvdata(component); |
|
|
|
if (!snd_soc_component_active(component) || !adav80x->rate) |
|
return 0; |
|
|
|
return snd_pcm_hw_constraint_single(substream->runtime, |
|
SNDRV_PCM_HW_PARAM_RATE, adav80x->rate); |
|
} |
|
|
|
static void adav80x_dai_shutdown(struct snd_pcm_substream *substream, |
|
struct snd_soc_dai *dai) |
|
{ |
|
struct snd_soc_component *component = dai->component; |
|
struct adav80x *adav80x = snd_soc_component_get_drvdata(component); |
|
|
|
if (!snd_soc_component_active(component)) |
|
adav80x->rate = 0; |
|
} |
|
|
|
static const struct snd_soc_dai_ops adav80x_dai_ops = { |
|
.set_fmt = adav80x_set_dai_fmt, |
|
.hw_params = adav80x_hw_params, |
|
.startup = adav80x_dai_startup, |
|
.shutdown = adav80x_dai_shutdown, |
|
}; |
|
|
|
#define ADAV80X_PLAYBACK_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ |
|
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | \ |
|
SNDRV_PCM_RATE_96000) |
|
|
|
#define ADAV80X_CAPTURE_RATES (SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000) |
|
|
|
#define ADAV80X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \ |
|
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE) |
|
|
|
static struct snd_soc_dai_driver adav80x_dais[] = { |
|
{ |
|
.name = "adav80x-hifi", |
|
.id = 0, |
|
.playback = { |
|
.stream_name = "HiFi Playback", |
|
.channels_min = 2, |
|
.channels_max = 2, |
|
.rates = ADAV80X_PLAYBACK_RATES, |
|
.formats = ADAV80X_FORMATS, |
|
}, |
|
.capture = { |
|
.stream_name = "HiFi Capture", |
|
.channels_min = 2, |
|
.channels_max = 2, |
|
.rates = ADAV80X_CAPTURE_RATES, |
|
.formats = ADAV80X_FORMATS, |
|
}, |
|
.ops = &adav80x_dai_ops, |
|
}, |
|
{ |
|
.name = "adav80x-aux", |
|
.id = 1, |
|
.playback = { |
|
.stream_name = "Aux Playback", |
|
.channels_min = 2, |
|
.channels_max = 2, |
|
.rates = ADAV80X_PLAYBACK_RATES, |
|
.formats = ADAV80X_FORMATS, |
|
}, |
|
.capture = { |
|
.stream_name = "Aux Capture", |
|
.channels_min = 2, |
|
.channels_max = 2, |
|
.rates = ADAV80X_CAPTURE_RATES, |
|
.formats = ADAV80X_FORMATS, |
|
}, |
|
.ops = &adav80x_dai_ops, |
|
}, |
|
}; |
|
|
|
static int adav80x_probe(struct snd_soc_component *component) |
|
{ |
|
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); |
|
struct adav80x *adav80x = snd_soc_component_get_drvdata(component); |
|
|
|
/* Force PLLs on for SYSCLK output */ |
|
snd_soc_dapm_force_enable_pin(dapm, "PLL1"); |
|
snd_soc_dapm_force_enable_pin(dapm, "PLL2"); |
|
|
|
/* Power down S/PDIF receiver, since it is currently not supported */ |
|
regmap_write(adav80x->regmap, ADAV80X_PLL_OUTE, 0x20); |
|
/* Disable DAC zero flag */ |
|
regmap_write(adav80x->regmap, ADAV80X_DAC_CTRL3, 0x6); |
|
|
|
return 0; |
|
} |
|
|
|
static int adav80x_resume(struct snd_soc_component *component) |
|
{ |
|
struct adav80x *adav80x = snd_soc_component_get_drvdata(component); |
|
|
|
regcache_sync(adav80x->regmap); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct snd_soc_component_driver adav80x_component_driver = { |
|
.probe = adav80x_probe, |
|
.resume = adav80x_resume, |
|
.set_bias_level = adav80x_set_bias_level, |
|
.set_pll = adav80x_set_pll, |
|
.set_sysclk = adav80x_set_sysclk, |
|
.controls = adav80x_controls, |
|
.num_controls = ARRAY_SIZE(adav80x_controls), |
|
.dapm_widgets = adav80x_dapm_widgets, |
|
.num_dapm_widgets = ARRAY_SIZE(adav80x_dapm_widgets), |
|
.dapm_routes = adav80x_dapm_routes, |
|
.num_dapm_routes = ARRAY_SIZE(adav80x_dapm_routes), |
|
.suspend_bias_off = 1, |
|
.idle_bias_on = 1, |
|
.use_pmdown_time = 1, |
|
.endianness = 1, |
|
}; |
|
|
|
int adav80x_bus_probe(struct device *dev, struct regmap *regmap) |
|
{ |
|
struct adav80x *adav80x; |
|
|
|
if (IS_ERR(regmap)) |
|
return PTR_ERR(regmap); |
|
|
|
adav80x = devm_kzalloc(dev, sizeof(*adav80x), GFP_KERNEL); |
|
if (!adav80x) |
|
return -ENOMEM; |
|
|
|
dev_set_drvdata(dev, adav80x); |
|
adav80x->regmap = regmap; |
|
|
|
return devm_snd_soc_register_component(dev, &adav80x_component_driver, |
|
adav80x_dais, ARRAY_SIZE(adav80x_dais)); |
|
} |
|
EXPORT_SYMBOL_GPL(adav80x_bus_probe); |
|
|
|
const struct regmap_config adav80x_regmap_config = { |
|
.val_bits = 8, |
|
.pad_bits = 1, |
|
.reg_bits = 7, |
|
|
|
.max_register = ADAV80X_PLL_OUTE, |
|
|
|
.cache_type = REGCACHE_RBTREE, |
|
.reg_defaults = adav80x_reg_defaults, |
|
.num_reg_defaults = ARRAY_SIZE(adav80x_reg_defaults), |
|
}; |
|
EXPORT_SYMBOL_GPL(adav80x_regmap_config); |
|
|
|
MODULE_DESCRIPTION("ASoC ADAV80x driver"); |
|
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>"); |
|
MODULE_AUTHOR("Yi Li <[email protected]>>"); |
|
MODULE_LICENSE("GPL");
|
|
|