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194 lines
3.9 KiB
194 lines
3.9 KiB
/* |
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* Copyright (c) Facebook, Inc. |
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* All rights reserved. |
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* |
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* This source code is licensed under both the BSD-style license (found in the |
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* LICENSE file in the root directory of this source tree) and the GPLv2 (found |
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* in the COPYING file in the root directory of this source tree). |
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* You may select, at your option, one of the above-listed licenses. |
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*/ |
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#ifndef ZSTD_COMMON_CPU_H |
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#define ZSTD_COMMON_CPU_H |
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/* |
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* Implementation taken from folly/CpuId.h |
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* https://github.com/facebook/folly/blob/master/folly/CpuId.h |
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*/ |
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#include "mem.h" |
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typedef struct { |
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U32 f1c; |
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U32 f1d; |
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U32 f7b; |
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U32 f7c; |
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} ZSTD_cpuid_t; |
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MEM_STATIC ZSTD_cpuid_t ZSTD_cpuid(void) { |
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U32 f1c = 0; |
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U32 f1d = 0; |
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U32 f7b = 0; |
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U32 f7c = 0; |
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#if defined(__i386__) && defined(__PIC__) && !defined(__clang__) && defined(__GNUC__) |
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/* The following block like the normal cpuid branch below, but gcc |
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* reserves ebx for use of its pic register so we must specially |
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* handle the save and restore to avoid clobbering the register |
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*/ |
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U32 n; |
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__asm__( |
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"pushl %%ebx\n\t" |
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"cpuid\n\t" |
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"popl %%ebx\n\t" |
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: "=a"(n) |
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: "a"(0) |
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: "ecx", "edx"); |
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if (n >= 1) { |
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U32 f1a; |
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__asm__( |
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"pushl %%ebx\n\t" |
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"cpuid\n\t" |
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"popl %%ebx\n\t" |
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: "=a"(f1a), "=c"(f1c), "=d"(f1d) |
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: "a"(1)); |
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} |
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if (n >= 7) { |
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__asm__( |
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"pushl %%ebx\n\t" |
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"cpuid\n\t" |
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"movl %%ebx, %%eax\n\t" |
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"popl %%ebx" |
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: "=a"(f7b), "=c"(f7c) |
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: "a"(7), "c"(0) |
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: "edx"); |
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} |
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#elif defined(__x86_64__) || defined(_M_X64) || defined(__i386__) |
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U32 n; |
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__asm__("cpuid" : "=a"(n) : "a"(0) : "ebx", "ecx", "edx"); |
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if (n >= 1) { |
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U32 f1a; |
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__asm__("cpuid" : "=a"(f1a), "=c"(f1c), "=d"(f1d) : "a"(1) : "ebx"); |
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} |
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if (n >= 7) { |
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U32 f7a; |
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__asm__("cpuid" |
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: "=a"(f7a), "=b"(f7b), "=c"(f7c) |
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: "a"(7), "c"(0) |
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: "edx"); |
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} |
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#endif |
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{ |
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ZSTD_cpuid_t cpuid; |
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cpuid.f1c = f1c; |
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cpuid.f1d = f1d; |
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cpuid.f7b = f7b; |
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cpuid.f7c = f7c; |
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return cpuid; |
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} |
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} |
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#define X(name, r, bit) \ |
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MEM_STATIC int ZSTD_cpuid_##name(ZSTD_cpuid_t const cpuid) { \ |
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return ((cpuid.r) & (1U << bit)) != 0; \ |
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} |
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/* cpuid(1): Processor Info and Feature Bits. */ |
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#define C(name, bit) X(name, f1c, bit) |
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C(sse3, 0) |
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C(pclmuldq, 1) |
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C(dtes64, 2) |
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C(monitor, 3) |
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C(dscpl, 4) |
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C(vmx, 5) |
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C(smx, 6) |
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C(eist, 7) |
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C(tm2, 8) |
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C(ssse3, 9) |
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C(cnxtid, 10) |
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C(fma, 12) |
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C(cx16, 13) |
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C(xtpr, 14) |
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C(pdcm, 15) |
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C(pcid, 17) |
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C(dca, 18) |
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C(sse41, 19) |
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C(sse42, 20) |
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C(x2apic, 21) |
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C(movbe, 22) |
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C(popcnt, 23) |
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C(tscdeadline, 24) |
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C(aes, 25) |
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C(xsave, 26) |
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C(osxsave, 27) |
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C(avx, 28) |
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C(f16c, 29) |
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C(rdrand, 30) |
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#undef C |
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#define D(name, bit) X(name, f1d, bit) |
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D(fpu, 0) |
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D(vme, 1) |
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D(de, 2) |
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D(pse, 3) |
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D(tsc, 4) |
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D(msr, 5) |
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D(pae, 6) |
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D(mce, 7) |
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D(cx8, 8) |
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D(apic, 9) |
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D(sep, 11) |
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D(mtrr, 12) |
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D(pge, 13) |
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D(mca, 14) |
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D(cmov, 15) |
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D(pat, 16) |
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D(pse36, 17) |
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D(psn, 18) |
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D(clfsh, 19) |
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D(ds, 21) |
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D(acpi, 22) |
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D(mmx, 23) |
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D(fxsr, 24) |
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D(sse, 25) |
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D(sse2, 26) |
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D(ss, 27) |
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D(htt, 28) |
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D(tm, 29) |
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D(pbe, 31) |
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#undef D |
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/* cpuid(7): Extended Features. */ |
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#define B(name, bit) X(name, f7b, bit) |
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B(bmi1, 3) |
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B(hle, 4) |
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B(avx2, 5) |
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B(smep, 7) |
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B(bmi2, 8) |
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B(erms, 9) |
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B(invpcid, 10) |
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B(rtm, 11) |
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B(mpx, 14) |
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B(avx512f, 16) |
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B(avx512dq, 17) |
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B(rdseed, 18) |
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B(adx, 19) |
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B(smap, 20) |
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B(avx512ifma, 21) |
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B(pcommit, 22) |
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B(clflushopt, 23) |
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B(clwb, 24) |
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B(avx512pf, 26) |
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B(avx512er, 27) |
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B(avx512cd, 28) |
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B(sha, 29) |
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B(avx512bw, 30) |
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B(avx512vl, 31) |
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#undef B |
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#define C(name, bit) X(name, f7c, bit) |
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C(prefetchwt1, 0) |
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C(avx512vbmi, 1) |
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#undef C |
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#undef X |
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#endif /* ZSTD_COMMON_CPU_H */
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