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836 lines
19 KiB
836 lines
19 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright (C) 2017 NXP Semiconductors |
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* Copyright (C) 2017 Bin Meng <[email protected]> |
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*/ |
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|
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#include <common.h> |
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#include <dm.h> |
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#include <errno.h> |
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#include <memalign.h> |
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#include <pci.h> |
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#include <dm/device-internal.h> |
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#include "nvme.h" |
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|
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#define NVME_Q_DEPTH 2 |
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#define NVME_AQ_DEPTH 2 |
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#define NVME_SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
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#define NVME_CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) |
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#define ADMIN_TIMEOUT 60 |
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#define IO_TIMEOUT 30 |
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#define MAX_PRP_POOL 512 |
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|
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enum nvme_queue_id { |
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NVME_ADMIN_Q, |
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NVME_IO_Q, |
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NVME_Q_NUM, |
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}; |
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|
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/* |
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* An NVM Express queue. Each device has at least two (one for admin |
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* commands and one for I/O commands). |
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*/ |
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struct nvme_queue { |
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struct nvme_dev *dev; |
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struct nvme_command *sq_cmds; |
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struct nvme_completion *cqes; |
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wait_queue_head_t sq_full; |
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u32 __iomem *q_db; |
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u16 q_depth; |
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s16 cq_vector; |
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u16 sq_head; |
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u16 sq_tail; |
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u16 cq_head; |
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u16 qid; |
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u8 cq_phase; |
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u8 cqe_seen; |
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unsigned long cmdid_data[]; |
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}; |
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|
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static int nvme_wait_ready(struct nvme_dev *dev, bool enabled) |
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{ |
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u32 bit = enabled ? NVME_CSTS_RDY : 0; |
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int timeout; |
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ulong start; |
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|
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/* Timeout field in the CAP register is in 500 millisecond units */ |
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timeout = NVME_CAP_TIMEOUT(dev->cap) * 500; |
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|
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start = get_timer(0); |
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while (get_timer(start) < timeout) { |
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if ((readl(&dev->bar->csts) & NVME_CSTS_RDY) == bit) |
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return 0; |
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} |
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|
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return -ETIME; |
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} |
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|
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static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, |
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int total_len, u64 dma_addr) |
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{ |
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u32 page_size = dev->page_size; |
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int offset = dma_addr & (page_size - 1); |
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u64 *prp_pool; |
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int length = total_len; |
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int i, nprps; |
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length -= (page_size - offset); |
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|
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if (length <= 0) { |
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*prp2 = 0; |
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return 0; |
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} |
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|
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if (length) |
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dma_addr += (page_size - offset); |
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|
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if (length <= page_size) { |
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*prp2 = dma_addr; |
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return 0; |
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} |
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|
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nprps = DIV_ROUND_UP(length, page_size); |
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|
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if (nprps > dev->prp_entry_num) { |
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free(dev->prp_pool); |
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dev->prp_pool = malloc(nprps << 3); |
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if (!dev->prp_pool) { |
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printf("Error: malloc prp_pool fail\n"); |
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return -ENOMEM; |
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} |
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dev->prp_entry_num = nprps; |
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} |
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|
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prp_pool = dev->prp_pool; |
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i = 0; |
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while (nprps) { |
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if (i == ((page_size >> 3) - 1)) { |
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*(prp_pool + i) = cpu_to_le64((ulong)prp_pool + |
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page_size); |
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i = 0; |
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prp_pool += page_size; |
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} |
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*(prp_pool + i++) = cpu_to_le64(dma_addr); |
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dma_addr += page_size; |
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nprps--; |
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} |
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*prp2 = (ulong)dev->prp_pool; |
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|
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return 0; |
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} |
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|
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static __le16 nvme_get_cmd_id(void) |
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{ |
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static unsigned short cmdid; |
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|
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return cpu_to_le16((cmdid < USHRT_MAX) ? cmdid++ : 0); |
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} |
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|
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static u16 nvme_read_completion_status(struct nvme_queue *nvmeq, u16 index) |
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{ |
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u64 start = (ulong)&nvmeq->cqes[index]; |
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u64 stop = start + sizeof(struct nvme_completion); |
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|
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invalidate_dcache_range(start, stop); |
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|
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return le16_to_cpu(readw(&(nvmeq->cqes[index].status))); |
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} |
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|
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/** |
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* nvme_submit_cmd() - copy a command into a queue and ring the doorbell |
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* |
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* @nvmeq: The queue to use |
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* @cmd: The command to send |
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*/ |
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static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) |
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{ |
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u16 tail = nvmeq->sq_tail; |
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|
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memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); |
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flush_dcache_range((ulong)&nvmeq->sq_cmds[tail], |
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(ulong)&nvmeq->sq_cmds[tail] + sizeof(*cmd)); |
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|
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if (++tail == nvmeq->q_depth) |
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tail = 0; |
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writel(tail, nvmeq->q_db); |
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nvmeq->sq_tail = tail; |
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} |
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|
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static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq, |
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struct nvme_command *cmd, |
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u32 *result, unsigned timeout) |
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{ |
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u16 head = nvmeq->cq_head; |
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u16 phase = nvmeq->cq_phase; |
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u16 status; |
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ulong start_time; |
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ulong timeout_us = timeout * 100000; |
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|
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cmd->common.command_id = nvme_get_cmd_id(); |
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nvme_submit_cmd(nvmeq, cmd); |
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|
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start_time = timer_get_us(); |
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|
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for (;;) { |
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status = nvme_read_completion_status(nvmeq, head); |
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if ((status & 0x01) == phase) |
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break; |
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if (timeout_us > 0 && (timer_get_us() - start_time) |
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>= timeout_us) |
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return -ETIMEDOUT; |
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} |
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|
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status >>= 1; |
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if (status) { |
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printf("ERROR: status = %x, phase = %d, head = %d\n", |
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status, phase, head); |
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status = 0; |
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if (++head == nvmeq->q_depth) { |
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head = 0; |
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phase = !phase; |
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} |
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writel(head, nvmeq->q_db + nvmeq->dev->db_stride); |
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nvmeq->cq_head = head; |
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nvmeq->cq_phase = phase; |
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|
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return -EIO; |
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} |
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|
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if (result) |
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*result = le32_to_cpu(readl(&(nvmeq->cqes[head].result))); |
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|
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if (++head == nvmeq->q_depth) { |
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head = 0; |
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phase = !phase; |
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} |
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writel(head, nvmeq->q_db + nvmeq->dev->db_stride); |
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nvmeq->cq_head = head; |
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nvmeq->cq_phase = phase; |
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|
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return status; |
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} |
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|
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static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd, |
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u32 *result) |
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{ |
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return nvme_submit_sync_cmd(dev->queues[NVME_ADMIN_Q], cmd, |
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result, ADMIN_TIMEOUT); |
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} |
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|
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static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, |
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int qid, int depth) |
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{ |
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struct nvme_queue *nvmeq = malloc(sizeof(*nvmeq)); |
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if (!nvmeq) |
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return NULL; |
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memset(nvmeq, 0, sizeof(*nvmeq)); |
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|
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nvmeq->cqes = (void *)memalign(4096, NVME_CQ_SIZE(depth)); |
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if (!nvmeq->cqes) |
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goto free_nvmeq; |
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memset((void *)nvmeq->cqes, 0, NVME_CQ_SIZE(depth)); |
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|
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nvmeq->sq_cmds = (void *)memalign(4096, NVME_SQ_SIZE(depth)); |
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if (!nvmeq->sq_cmds) |
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goto free_queue; |
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memset((void *)nvmeq->sq_cmds, 0, NVME_SQ_SIZE(depth)); |
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|
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nvmeq->dev = dev; |
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|
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nvmeq->cq_head = 0; |
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nvmeq->cq_phase = 1; |
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nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
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nvmeq->q_depth = depth; |
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nvmeq->qid = qid; |
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dev->queue_count++; |
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dev->queues[qid] = nvmeq; |
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|
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return nvmeq; |
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|
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free_queue: |
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free((void *)nvmeq->cqes); |
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free_nvmeq: |
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free(nvmeq); |
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|
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return NULL; |
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} |
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|
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static int nvme_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
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{ |
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struct nvme_command c; |
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|
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memset(&c, 0, sizeof(c)); |
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c.delete_queue.opcode = opcode; |
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c.delete_queue.qid = cpu_to_le16(id); |
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|
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return nvme_submit_admin_cmd(dev, &c, NULL); |
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} |
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static int nvme_delete_sq(struct nvme_dev *dev, u16 sqid) |
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{ |
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return nvme_delete_queue(dev, nvme_admin_delete_sq, sqid); |
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} |
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static int nvme_delete_cq(struct nvme_dev *dev, u16 cqid) |
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{ |
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return nvme_delete_queue(dev, nvme_admin_delete_cq, cqid); |
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} |
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static int nvme_enable_ctrl(struct nvme_dev *dev) |
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{ |
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dev->ctrl_config &= ~NVME_CC_SHN_MASK; |
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dev->ctrl_config |= NVME_CC_ENABLE; |
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writel(cpu_to_le32(dev->ctrl_config), &dev->bar->cc); |
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|
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return nvme_wait_ready(dev, true); |
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} |
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static int nvme_disable_ctrl(struct nvme_dev *dev) |
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{ |
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dev->ctrl_config &= ~NVME_CC_SHN_MASK; |
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dev->ctrl_config &= ~NVME_CC_ENABLE; |
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writel(cpu_to_le32(dev->ctrl_config), &dev->bar->cc); |
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|
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return nvme_wait_ready(dev, false); |
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} |
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static void nvme_free_queue(struct nvme_queue *nvmeq) |
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{ |
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free((void *)nvmeq->cqes); |
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free(nvmeq->sq_cmds); |
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free(nvmeq); |
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} |
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static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
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{ |
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int i; |
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for (i = dev->queue_count - 1; i >= lowest; i--) { |
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struct nvme_queue *nvmeq = dev->queues[i]; |
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dev->queue_count--; |
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dev->queues[i] = NULL; |
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nvme_free_queue(nvmeq); |
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} |
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} |
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static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
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{ |
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struct nvme_dev *dev = nvmeq->dev; |
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nvmeq->sq_tail = 0; |
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nvmeq->cq_head = 0; |
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nvmeq->cq_phase = 1; |
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nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
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memset((void *)nvmeq->cqes, 0, NVME_CQ_SIZE(nvmeq->q_depth)); |
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flush_dcache_range((ulong)nvmeq->cqes, |
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(ulong)nvmeq->cqes + NVME_CQ_SIZE(nvmeq->q_depth)); |
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dev->online_queues++; |
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} |
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|
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static int nvme_configure_admin_queue(struct nvme_dev *dev) |
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{ |
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int result; |
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u32 aqa; |
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u64 cap = dev->cap; |
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struct nvme_queue *nvmeq; |
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/* most architectures use 4KB as the page size */ |
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unsigned page_shift = 12; |
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unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12; |
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unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12; |
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|
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if (page_shift < dev_page_min) { |
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debug("Device minimum page size (%u) too large for host (%u)\n", |
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1 << dev_page_min, 1 << page_shift); |
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return -ENODEV; |
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} |
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|
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if (page_shift > dev_page_max) { |
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debug("Device maximum page size (%u) smaller than host (%u)\n", |
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1 << dev_page_max, 1 << page_shift); |
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page_shift = dev_page_max; |
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} |
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|
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result = nvme_disable_ctrl(dev); |
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if (result < 0) |
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return result; |
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|
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nvmeq = dev->queues[NVME_ADMIN_Q]; |
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if (!nvmeq) { |
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nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); |
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if (!nvmeq) |
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return -ENOMEM; |
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} |
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|
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aqa = nvmeq->q_depth - 1; |
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aqa |= aqa << 16; |
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aqa |= aqa << 16; |
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|
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dev->page_size = 1 << page_shift; |
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|
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dev->ctrl_config = NVME_CC_CSS_NVM; |
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dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT; |
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dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE; |
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dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES; |
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|
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writel(aqa, &dev->bar->aqa); |
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nvme_writeq((ulong)nvmeq->sq_cmds, &dev->bar->asq); |
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nvme_writeq((ulong)nvmeq->cqes, &dev->bar->acq); |
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|
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result = nvme_enable_ctrl(dev); |
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if (result) |
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goto free_nvmeq; |
|
|
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nvmeq->cq_vector = 0; |
|
|
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nvme_init_queue(dev->queues[NVME_ADMIN_Q], 0); |
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|
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return result; |
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|
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free_nvmeq: |
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nvme_free_queues(dev, 0); |
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|
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return result; |
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} |
|
|
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static int nvme_alloc_cq(struct nvme_dev *dev, u16 qid, |
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struct nvme_queue *nvmeq) |
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{ |
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struct nvme_command c; |
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int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; |
|
|
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memset(&c, 0, sizeof(c)); |
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c.create_cq.opcode = nvme_admin_create_cq; |
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c.create_cq.prp1 = cpu_to_le64((ulong)nvmeq->cqes); |
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c.create_cq.cqid = cpu_to_le16(qid); |
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c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); |
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c.create_cq.cq_flags = cpu_to_le16(flags); |
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c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); |
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|
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return nvme_submit_admin_cmd(dev, &c, NULL); |
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} |
|
|
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static int nvme_alloc_sq(struct nvme_dev *dev, u16 qid, |
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struct nvme_queue *nvmeq) |
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{ |
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struct nvme_command c; |
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int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; |
|
|
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memset(&c, 0, sizeof(c)); |
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c.create_sq.opcode = nvme_admin_create_sq; |
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c.create_sq.prp1 = cpu_to_le64((ulong)nvmeq->sq_cmds); |
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c.create_sq.sqid = cpu_to_le16(qid); |
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c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); |
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c.create_sq.sq_flags = cpu_to_le16(flags); |
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c.create_sq.cqid = cpu_to_le16(qid); |
|
|
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return nvme_submit_admin_cmd(dev, &c, NULL); |
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} |
|
|
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int nvme_identify(struct nvme_dev *dev, unsigned nsid, |
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unsigned cns, dma_addr_t dma_addr) |
|
{ |
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struct nvme_command c; |
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u32 page_size = dev->page_size; |
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int offset = dma_addr & (page_size - 1); |
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int length = sizeof(struct nvme_id_ctrl); |
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int ret; |
|
|
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memset(&c, 0, sizeof(c)); |
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c.identify.opcode = nvme_admin_identify; |
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c.identify.nsid = cpu_to_le32(nsid); |
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c.identify.prp1 = cpu_to_le64(dma_addr); |
|
|
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length -= (page_size - offset); |
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if (length <= 0) { |
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c.identify.prp2 = 0; |
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} else { |
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dma_addr += (page_size - offset); |
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c.identify.prp2 = cpu_to_le64(dma_addr); |
|
} |
|
|
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c.identify.cns = cpu_to_le32(cns); |
|
|
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ret = nvme_submit_admin_cmd(dev, &c, NULL); |
|
if (!ret) |
|
invalidate_dcache_range(dma_addr, |
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dma_addr + sizeof(struct nvme_id_ctrl)); |
|
|
|
return ret; |
|
} |
|
|
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int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, |
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dma_addr_t dma_addr, u32 *result) |
|
{ |
|
struct nvme_command c; |
|
|
|
memset(&c, 0, sizeof(c)); |
|
c.features.opcode = nvme_admin_get_features; |
|
c.features.nsid = cpu_to_le32(nsid); |
|
c.features.prp1 = cpu_to_le64(dma_addr); |
|
c.features.fid = cpu_to_le32(fid); |
|
|
|
/* |
|
* TODO: add cache invalidate operation when the size of |
|
* the DMA buffer is known |
|
*/ |
|
|
|
return nvme_submit_admin_cmd(dev, &c, result); |
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} |
|
|
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int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, |
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dma_addr_t dma_addr, u32 *result) |
|
{ |
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struct nvme_command c; |
|
|
|
memset(&c, 0, sizeof(c)); |
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c.features.opcode = nvme_admin_set_features; |
|
c.features.prp1 = cpu_to_le64(dma_addr); |
|
c.features.fid = cpu_to_le32(fid); |
|
c.features.dword11 = cpu_to_le32(dword11); |
|
|
|
/* |
|
* TODO: add cache flush operation when the size of |
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* the DMA buffer is known |
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*/ |
|
|
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return nvme_submit_admin_cmd(dev, &c, result); |
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} |
|
|
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static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) |
|
{ |
|
struct nvme_dev *dev = nvmeq->dev; |
|
int result; |
|
|
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nvmeq->cq_vector = qid - 1; |
|
result = nvme_alloc_cq(dev, qid, nvmeq); |
|
if (result < 0) |
|
goto release_cq; |
|
|
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result = nvme_alloc_sq(dev, qid, nvmeq); |
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if (result < 0) |
|
goto release_sq; |
|
|
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nvme_init_queue(nvmeq, qid); |
|
|
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return result; |
|
|
|
release_sq: |
|
nvme_delete_sq(dev, qid); |
|
release_cq: |
|
nvme_delete_cq(dev, qid); |
|
|
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return result; |
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} |
|
|
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static int nvme_set_queue_count(struct nvme_dev *dev, int count) |
|
{ |
|
int status; |
|
u32 result; |
|
u32 q_count = (count - 1) | ((count - 1) << 16); |
|
|
|
status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, |
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q_count, 0, &result); |
|
|
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if (status < 0) |
|
return status; |
|
if (status > 1) |
|
return 0; |
|
|
|
return min(result & 0xffff, result >> 16) + 1; |
|
} |
|
|
|
static void nvme_create_io_queues(struct nvme_dev *dev) |
|
{ |
|
unsigned int i; |
|
|
|
for (i = dev->queue_count; i <= dev->max_qid; i++) |
|
if (!nvme_alloc_queue(dev, i, dev->q_depth)) |
|
break; |
|
|
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for (i = dev->online_queues; i <= dev->queue_count - 1; i++) |
|
if (nvme_create_queue(dev->queues[i], i)) |
|
break; |
|
} |
|
|
|
static int nvme_setup_io_queues(struct nvme_dev *dev) |
|
{ |
|
int nr_io_queues; |
|
int result; |
|
|
|
nr_io_queues = 1; |
|
result = nvme_set_queue_count(dev, nr_io_queues); |
|
if (result <= 0) |
|
return result; |
|
|
|
dev->max_qid = nr_io_queues; |
|
|
|
/* Free previously allocated queues */ |
|
nvme_free_queues(dev, nr_io_queues + 1); |
|
nvme_create_io_queues(dev); |
|
|
|
return 0; |
|
} |
|
|
|
static int nvme_get_info_from_identify(struct nvme_dev *dev) |
|
{ |
|
ALLOC_CACHE_ALIGN_BUFFER(char, buf, sizeof(struct nvme_id_ctrl)); |
|
struct nvme_id_ctrl *ctrl = (struct nvme_id_ctrl *)buf; |
|
int ret; |
|
int shift = NVME_CAP_MPSMIN(dev->cap) + 12; |
|
|
|
ret = nvme_identify(dev, 0, 1, (dma_addr_t)ctrl); |
|
if (ret) |
|
return -EIO; |
|
|
|
dev->nn = le32_to_cpu(ctrl->nn); |
|
dev->vwc = ctrl->vwc; |
|
memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn)); |
|
memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn)); |
|
memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr)); |
|
if (ctrl->mdts) |
|
dev->max_transfer_shift = (ctrl->mdts + shift); |
|
else { |
|
/* |
|
* Maximum Data Transfer Size (MDTS) field indicates the maximum |
|
* data transfer size between the host and the controller. The |
|
* host should not submit a command that exceeds this transfer |
|
* size. The value is in units of the minimum memory page size |
|
* and is reported as a power of two (2^n). |
|
* |
|
* The spec also says: a value of 0h indicates no restrictions |
|
* on transfer size. But in nvme_blk_read/write() below we have |
|
* the following algorithm for maximum number of logic blocks |
|
* per transfer: |
|
* |
|
* u16 lbas = 1 << (dev->max_transfer_shift - ns->lba_shift); |
|
* |
|
* In order for lbas not to overflow, the maximum number is 15 |
|
* which means dev->max_transfer_shift = 15 + 9 (ns->lba_shift). |
|
* Let's use 20 which provides 1MB size. |
|
*/ |
|
dev->max_transfer_shift = 20; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
int nvme_scan_namespace(void) |
|
{ |
|
struct uclass *uc; |
|
struct udevice *dev; |
|
int ret; |
|
|
|
ret = uclass_get(UCLASS_NVME, &uc); |
|
if (ret) |
|
return ret; |
|
|
|
uclass_foreach_dev(dev, uc) { |
|
ret = device_probe(dev); |
|
if (ret) |
|
return ret; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int nvme_blk_probe(struct udevice *udev) |
|
{ |
|
struct nvme_dev *ndev = dev_get_priv(udev->parent); |
|
struct blk_desc *desc = dev_get_uclass_platdata(udev); |
|
struct nvme_ns *ns = dev_get_priv(udev); |
|
u8 flbas; |
|
ALLOC_CACHE_ALIGN_BUFFER(char, buf, sizeof(struct nvme_id_ns)); |
|
struct nvme_id_ns *id = (struct nvme_id_ns *)buf; |
|
struct pci_child_platdata *pplat; |
|
|
|
memset(ns, 0, sizeof(*ns)); |
|
ns->dev = ndev; |
|
/* extract the namespace id from the block device name */ |
|
ns->ns_id = trailing_strtol(udev->name) + 1; |
|
if (nvme_identify(ndev, ns->ns_id, 0, (dma_addr_t)id)) |
|
return -EIO; |
|
|
|
flbas = id->flbas & NVME_NS_FLBAS_LBA_MASK; |
|
ns->flbas = flbas; |
|
ns->lba_shift = id->lbaf[flbas].ds; |
|
ns->mode_select_num_blocks = le64_to_cpu(id->nsze); |
|
ns->mode_select_block_len = 1 << ns->lba_shift; |
|
list_add(&ns->list, &ndev->namespaces); |
|
|
|
desc->lba = ns->mode_select_num_blocks; |
|
desc->log2blksz = ns->lba_shift; |
|
desc->blksz = 1 << ns->lba_shift; |
|
desc->bdev = udev; |
|
pplat = dev_get_parent_platdata(udev->parent); |
|
sprintf(desc->vendor, "0x%.4x", pplat->vendor); |
|
memcpy(desc->product, ndev->serial, sizeof(ndev->serial)); |
|
memcpy(desc->revision, ndev->firmware_rev, sizeof(ndev->firmware_rev)); |
|
part_init(desc); |
|
|
|
return 0; |
|
} |
|
|
|
static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr, |
|
lbaint_t blkcnt, void *buffer, bool read) |
|
{ |
|
struct nvme_ns *ns = dev_get_priv(udev); |
|
struct nvme_dev *dev = ns->dev; |
|
struct nvme_command c; |
|
struct blk_desc *desc = dev_get_uclass_platdata(udev); |
|
int status; |
|
u64 prp2; |
|
u64 total_len = blkcnt << desc->log2blksz; |
|
u64 temp_len = total_len; |
|
|
|
u64 slba = blknr; |
|
u16 lbas = 1 << (dev->max_transfer_shift - ns->lba_shift); |
|
u64 total_lbas = blkcnt; |
|
|
|
if (!read) |
|
flush_dcache_range((unsigned long)buffer, |
|
(unsigned long)buffer + total_len); |
|
|
|
c.rw.opcode = read ? nvme_cmd_read : nvme_cmd_write; |
|
c.rw.flags = 0; |
|
c.rw.nsid = cpu_to_le32(ns->ns_id); |
|
c.rw.control = 0; |
|
c.rw.dsmgmt = 0; |
|
c.rw.reftag = 0; |
|
c.rw.apptag = 0; |
|
c.rw.appmask = 0; |
|
c.rw.metadata = 0; |
|
|
|
while (total_lbas) { |
|
if (total_lbas < lbas) { |
|
lbas = (u16)total_lbas; |
|
total_lbas = 0; |
|
} else { |
|
total_lbas -= lbas; |
|
} |
|
|
|
if (nvme_setup_prps(dev, &prp2, |
|
lbas << ns->lba_shift, (ulong)buffer)) |
|
return -EIO; |
|
c.rw.slba = cpu_to_le64(slba); |
|
slba += lbas; |
|
c.rw.length = cpu_to_le16(lbas - 1); |
|
c.rw.prp1 = cpu_to_le64((ulong)buffer); |
|
c.rw.prp2 = cpu_to_le64(prp2); |
|
status = nvme_submit_sync_cmd(dev->queues[NVME_IO_Q], |
|
&c, NULL, IO_TIMEOUT); |
|
if (status) |
|
break; |
|
temp_len -= (u32)lbas << ns->lba_shift; |
|
buffer += lbas << ns->lba_shift; |
|
} |
|
|
|
if (read) |
|
invalidate_dcache_range((unsigned long)buffer, |
|
(unsigned long)buffer + total_len); |
|
|
|
return (total_len - temp_len) >> desc->log2blksz; |
|
} |
|
|
|
static ulong nvme_blk_read(struct udevice *udev, lbaint_t blknr, |
|
lbaint_t blkcnt, void *buffer) |
|
{ |
|
return nvme_blk_rw(udev, blknr, blkcnt, buffer, true); |
|
} |
|
|
|
static ulong nvme_blk_write(struct udevice *udev, lbaint_t blknr, |
|
lbaint_t blkcnt, const void *buffer) |
|
{ |
|
return nvme_blk_rw(udev, blknr, blkcnt, (void *)buffer, false); |
|
} |
|
|
|
static const struct blk_ops nvme_blk_ops = { |
|
.read = nvme_blk_read, |
|
.write = nvme_blk_write, |
|
}; |
|
|
|
U_BOOT_DRIVER(nvme_blk) = { |
|
.name = "nvme-blk", |
|
.id = UCLASS_BLK, |
|
.probe = nvme_blk_probe, |
|
.ops = &nvme_blk_ops, |
|
.priv_auto_alloc_size = sizeof(struct nvme_ns), |
|
}; |
|
|
|
static int nvme_bind(struct udevice *udev) |
|
{ |
|
static int ndev_num; |
|
char name[20]; |
|
|
|
sprintf(name, "nvme#%d", ndev_num++); |
|
|
|
return device_set_name(udev, name); |
|
} |
|
|
|
static int nvme_probe(struct udevice *udev) |
|
{ |
|
int ret; |
|
struct nvme_dev *ndev = dev_get_priv(udev); |
|
|
|
ndev->instance = trailing_strtol(udev->name); |
|
|
|
INIT_LIST_HEAD(&ndev->namespaces); |
|
ndev->bar = dm_pci_map_bar(udev, PCI_BASE_ADDRESS_0, |
|
PCI_REGION_MEM); |
|
if (readl(&ndev->bar->csts) == -1) { |
|
ret = -ENODEV; |
|
printf("Error: %s: Out of memory!\n", udev->name); |
|
goto free_nvme; |
|
} |
|
|
|
ndev->queues = malloc(NVME_Q_NUM * sizeof(struct nvme_queue *)); |
|
if (!ndev->queues) { |
|
ret = -ENOMEM; |
|
printf("Error: %s: Out of memory!\n", udev->name); |
|
goto free_nvme; |
|
} |
|
memset(ndev->queues, 0, NVME_Q_NUM * sizeof(struct nvme_queue *)); |
|
|
|
ndev->prp_pool = malloc(MAX_PRP_POOL); |
|
if (!ndev->prp_pool) { |
|
ret = -ENOMEM; |
|
printf("Error: %s: Out of memory!\n", udev->name); |
|
goto free_nvme; |
|
} |
|
ndev->prp_entry_num = MAX_PRP_POOL >> 3; |
|
|
|
ndev->cap = nvme_readq(&ndev->bar->cap); |
|
ndev->q_depth = min_t(int, NVME_CAP_MQES(ndev->cap) + 1, NVME_Q_DEPTH); |
|
ndev->db_stride = 1 << NVME_CAP_STRIDE(ndev->cap); |
|
ndev->dbs = ((void __iomem *)ndev->bar) + 4096; |
|
|
|
ret = nvme_configure_admin_queue(ndev); |
|
if (ret) |
|
goto free_queue; |
|
|
|
ret = nvme_setup_io_queues(ndev); |
|
if (ret) |
|
goto free_queue; |
|
|
|
nvme_get_info_from_identify(ndev); |
|
|
|
return 0; |
|
|
|
free_queue: |
|
free((void *)ndev->queues); |
|
free_nvme: |
|
return ret; |
|
} |
|
|
|
U_BOOT_DRIVER(nvme) = { |
|
.name = "nvme", |
|
.id = UCLASS_NVME, |
|
.bind = nvme_bind, |
|
.probe = nvme_probe, |
|
.priv_auto_alloc_size = sizeof(struct nvme_dev), |
|
}; |
|
|
|
struct pci_device_id nvme_supported[] = { |
|
{ PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, ~0) }, |
|
{} |
|
}; |
|
|
|
U_BOOT_PCI_DEVICE(nvme, nvme_supported);
|
|
|