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746 lines
18 KiB
746 lines
18 KiB
// SPDX-License-Identifier: GPL-2.0 |
|
/* |
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* MMCIF driver. |
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* |
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* Copyright (C) 2011 Renesas Solutions Corp. |
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*/ |
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|
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#include <config.h> |
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#include <common.h> |
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#include <watchdog.h> |
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#include <command.h> |
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#include <mmc.h> |
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#include <clk.h> |
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#include <dm.h> |
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#include <malloc.h> |
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#include <linux/errno.h> |
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#include <linux/compat.h> |
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#include <linux/io.h> |
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#include <linux/sizes.h> |
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#include "sh_mmcif.h" |
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|
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#define DRIVER_NAME "sh_mmcif" |
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|
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static int sh_mmcif_intr(void *dev_id) |
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{ |
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struct sh_mmcif_host *host = dev_id; |
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u32 state = 0; |
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|
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state = sh_mmcif_read(&host->regs->ce_int); |
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state &= sh_mmcif_read(&host->regs->ce_int_mask); |
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|
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if (state & INT_RBSYE) { |
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sh_mmcif_write(~(INT_RBSYE | INT_CRSPE), &host->regs->ce_int); |
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sh_mmcif_bitclr(MASK_MRBSYE, &host->regs->ce_int_mask); |
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goto end; |
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} else if (state & INT_CRSPE) { |
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sh_mmcif_write(~INT_CRSPE, &host->regs->ce_int); |
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sh_mmcif_bitclr(MASK_MCRSPE, &host->regs->ce_int_mask); |
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/* one more interrupt (INT_RBSYE) */ |
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if (sh_mmcif_read(&host->regs->ce_cmd_set) & CMD_SET_RBSY) |
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return -EAGAIN; |
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goto end; |
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} else if (state & INT_BUFREN) { |
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sh_mmcif_write(~INT_BUFREN, &host->regs->ce_int); |
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sh_mmcif_bitclr(MASK_MBUFREN, &host->regs->ce_int_mask); |
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goto end; |
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} else if (state & INT_BUFWEN) { |
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sh_mmcif_write(~INT_BUFWEN, &host->regs->ce_int); |
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sh_mmcif_bitclr(MASK_MBUFWEN, &host->regs->ce_int_mask); |
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goto end; |
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} else if (state & INT_CMD12DRE) { |
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sh_mmcif_write(~(INT_CMD12DRE | INT_CMD12RBE | INT_CMD12CRE | |
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INT_BUFRE), &host->regs->ce_int); |
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sh_mmcif_bitclr(MASK_MCMD12DRE, &host->regs->ce_int_mask); |
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goto end; |
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} else if (state & INT_BUFRE) { |
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sh_mmcif_write(~INT_BUFRE, &host->regs->ce_int); |
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sh_mmcif_bitclr(MASK_MBUFRE, &host->regs->ce_int_mask); |
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goto end; |
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} else if (state & INT_DTRANE) { |
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sh_mmcif_write(~INT_DTRANE, &host->regs->ce_int); |
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sh_mmcif_bitclr(MASK_MDTRANE, &host->regs->ce_int_mask); |
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goto end; |
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} else if (state & INT_CMD12RBE) { |
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sh_mmcif_write(~(INT_CMD12RBE | INT_CMD12CRE), |
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&host->regs->ce_int); |
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sh_mmcif_bitclr(MASK_MCMD12RBE, &host->regs->ce_int_mask); |
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goto end; |
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} else if (state & INT_ERR_STS) { |
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/* err interrupts */ |
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sh_mmcif_write(~state, &host->regs->ce_int); |
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sh_mmcif_bitclr(state, &host->regs->ce_int_mask); |
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goto err; |
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} else |
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return -EAGAIN; |
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|
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err: |
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host->sd_error = 1; |
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debug("%s: int err state = %08x\n", DRIVER_NAME, state); |
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end: |
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host->wait_int = 1; |
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return 0; |
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} |
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static int mmcif_wait_interrupt_flag(struct sh_mmcif_host *host) |
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{ |
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int timeout = 10000000; |
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|
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while (1) { |
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timeout--; |
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if (timeout < 0) { |
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printf("timeout\n"); |
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return 0; |
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} |
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|
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if (!sh_mmcif_intr(host)) |
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break; |
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|
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udelay(1); /* 1 usec */ |
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} |
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|
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return 1; /* Return value: NOT 0 = complete waiting */ |
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} |
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static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) |
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{ |
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sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); |
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sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); |
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|
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if (!clk) |
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return; |
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|
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if (clk == CLKDEV_EMMC_DATA) |
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sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); |
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else |
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sh_mmcif_bitset((fls(DIV_ROUND_UP(host->clk, |
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clk) - 1) - 1) << 16, |
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&host->regs->ce_clk_ctrl); |
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sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); |
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} |
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|
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static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) |
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{ |
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u32 tmp; |
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|
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tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | |
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CLK_CLEAR); |
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|
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sh_mmcif_write(SOFT_RST_ON, &host->regs->ce_version); |
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sh_mmcif_write(SOFT_RST_OFF, &host->regs->ce_version); |
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sh_mmcif_bitset(tmp | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29, |
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&host->regs->ce_clk_ctrl); |
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/* byte swap on */ |
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sh_mmcif_bitset(BUF_ACC_ATYP, &host->regs->ce_buf_acc); |
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} |
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|
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static int sh_mmcif_error_manage(struct sh_mmcif_host *host) |
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{ |
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u32 state1, state2; |
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int ret, timeout = 10000000; |
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|
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host->sd_error = 0; |
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host->wait_int = 0; |
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|
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state1 = sh_mmcif_read(&host->regs->ce_host_sts1); |
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state2 = sh_mmcif_read(&host->regs->ce_host_sts2); |
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debug("%s: ERR HOST_STS1 = %08x\n", \ |
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DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts1)); |
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debug("%s: ERR HOST_STS2 = %08x\n", \ |
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DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts2)); |
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|
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if (state1 & STS1_CMDSEQ) { |
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debug("%s: Forced end of command sequence\n", DRIVER_NAME); |
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sh_mmcif_bitset(CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl); |
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sh_mmcif_bitset(~CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl); |
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while (1) { |
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timeout--; |
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if (timeout < 0) { |
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printf(DRIVER_NAME": Forceed end of " \ |
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"command sequence timeout err\n"); |
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return -EILSEQ; |
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} |
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if (!(sh_mmcif_read(&host->regs->ce_host_sts1) |
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& STS1_CMDSEQ)) |
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break; |
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} |
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sh_mmcif_sync_reset(host); |
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return -EILSEQ; |
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} |
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|
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if (state2 & STS2_CRC_ERR) |
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ret = -EILSEQ; |
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else if (state2 & STS2_TIMEOUT_ERR) |
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ret = -ETIMEDOUT; |
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else |
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ret = -EILSEQ; |
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return ret; |
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} |
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|
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static int sh_mmcif_single_read(struct sh_mmcif_host *host, |
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struct mmc_data *data) |
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{ |
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long time; |
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u32 blocksize, i; |
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unsigned long *p = (unsigned long *)data->dest; |
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|
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if ((unsigned long)p & 0x00000001) { |
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printf("%s: The data pointer is unaligned.", __func__); |
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return -EIO; |
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} |
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host->wait_int = 0; |
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|
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/* buf read enable */ |
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sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask); |
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time = mmcif_wait_interrupt_flag(host); |
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if (time == 0 || host->sd_error != 0) |
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return sh_mmcif_error_manage(host); |
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host->wait_int = 0; |
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blocksize = (BLOCK_SIZE_MASK & |
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sh_mmcif_read(&host->regs->ce_block_set)) + 3; |
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for (i = 0; i < blocksize / 4; i++) |
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*p++ = sh_mmcif_read(&host->regs->ce_data); |
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|
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/* buffer read end */ |
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sh_mmcif_bitset(MASK_MBUFRE, &host->regs->ce_int_mask); |
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time = mmcif_wait_interrupt_flag(host); |
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if (time == 0 || host->sd_error != 0) |
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return sh_mmcif_error_manage(host); |
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|
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host->wait_int = 0; |
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return 0; |
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} |
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|
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static int sh_mmcif_multi_read(struct sh_mmcif_host *host, |
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struct mmc_data *data) |
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{ |
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long time; |
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u32 blocksize, i, j; |
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unsigned long *p = (unsigned long *)data->dest; |
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|
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if ((unsigned long)p & 0x00000001) { |
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printf("%s: The data pointer is unaligned.", __func__); |
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return -EIO; |
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} |
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host->wait_int = 0; |
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blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set); |
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for (j = 0; j < data->blocks; j++) { |
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sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask); |
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time = mmcif_wait_interrupt_flag(host); |
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if (time == 0 || host->sd_error != 0) |
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return sh_mmcif_error_manage(host); |
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host->wait_int = 0; |
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for (i = 0; i < blocksize / 4; i++) |
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*p++ = sh_mmcif_read(&host->regs->ce_data); |
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|
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WATCHDOG_RESET(); |
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} |
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return 0; |
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} |
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static int sh_mmcif_single_write(struct sh_mmcif_host *host, |
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struct mmc_data *data) |
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{ |
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long time; |
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u32 blocksize, i; |
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const unsigned long *p = (unsigned long *)data->dest; |
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|
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if ((unsigned long)p & 0x00000001) { |
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printf("%s: The data pointer is unaligned.", __func__); |
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return -EIO; |
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} |
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host->wait_int = 0; |
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sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask); |
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time = mmcif_wait_interrupt_flag(host); |
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if (time == 0 || host->sd_error != 0) |
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return sh_mmcif_error_manage(host); |
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host->wait_int = 0; |
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blocksize = (BLOCK_SIZE_MASK & |
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sh_mmcif_read(&host->regs->ce_block_set)) + 3; |
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for (i = 0; i < blocksize / 4; i++) |
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sh_mmcif_write(*p++, &host->regs->ce_data); |
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/* buffer write end */ |
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sh_mmcif_bitset(MASK_MDTRANE, &host->regs->ce_int_mask); |
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time = mmcif_wait_interrupt_flag(host); |
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if (time == 0 || host->sd_error != 0) |
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return sh_mmcif_error_manage(host); |
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host->wait_int = 0; |
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return 0; |
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} |
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static int sh_mmcif_multi_write(struct sh_mmcif_host *host, |
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struct mmc_data *data) |
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{ |
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long time; |
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u32 i, j, blocksize; |
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const unsigned long *p = (unsigned long *)data->dest; |
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if ((unsigned long)p & 0x00000001) { |
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printf("%s: The data pointer is unaligned.", __func__); |
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return -EIO; |
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} |
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host->wait_int = 0; |
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blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set); |
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for (j = 0; j < data->blocks; j++) { |
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sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask); |
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time = mmcif_wait_interrupt_flag(host); |
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if (time == 0 || host->sd_error != 0) |
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return sh_mmcif_error_manage(host); |
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host->wait_int = 0; |
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for (i = 0; i < blocksize / 4; i++) |
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sh_mmcif_write(*p++, &host->regs->ce_data); |
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|
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WATCHDOG_RESET(); |
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} |
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return 0; |
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} |
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static void sh_mmcif_get_response(struct sh_mmcif_host *host, |
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struct mmc_cmd *cmd) |
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{ |
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if (cmd->resp_type & MMC_RSP_136) { |
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cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp3); |
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cmd->response[1] = sh_mmcif_read(&host->regs->ce_resp2); |
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cmd->response[2] = sh_mmcif_read(&host->regs->ce_resp1); |
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cmd->response[3] = sh_mmcif_read(&host->regs->ce_resp0); |
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debug(" RESP %08x, %08x, %08x, %08x\n", cmd->response[0], |
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cmd->response[1], cmd->response[2], cmd->response[3]); |
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} else { |
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cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp0); |
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} |
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} |
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|
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static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, |
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struct mmc_cmd *cmd) |
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{ |
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cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp_cmd12); |
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} |
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|
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static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, |
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struct mmc_data *data, struct mmc_cmd *cmd) |
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{ |
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u32 tmp = 0; |
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u32 opc = cmd->cmdidx; |
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|
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/* Response Type check */ |
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switch (cmd->resp_type) { |
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case MMC_RSP_NONE: |
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tmp |= CMD_SET_RTYP_NO; |
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break; |
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case MMC_RSP_R1: |
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case MMC_RSP_R1b: |
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case MMC_RSP_R3: |
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tmp |= CMD_SET_RTYP_6B; |
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break; |
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case MMC_RSP_R2: |
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tmp |= CMD_SET_RTYP_17B; |
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break; |
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default: |
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printf(DRIVER_NAME": Not support type response.\n"); |
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break; |
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} |
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|
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/* RBSY */ |
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if (opc == MMC_CMD_SWITCH) |
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tmp |= CMD_SET_RBSY; |
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|
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/* WDAT / DATW */ |
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if (host->data) { |
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tmp |= CMD_SET_WDAT; |
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switch (host->bus_width) { |
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case MMC_BUS_WIDTH_1: |
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tmp |= CMD_SET_DATW_1; |
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break; |
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case MMC_BUS_WIDTH_4: |
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tmp |= CMD_SET_DATW_4; |
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break; |
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case MMC_BUS_WIDTH_8: |
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tmp |= CMD_SET_DATW_8; |
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break; |
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default: |
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printf(DRIVER_NAME": Not support bus width.\n"); |
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break; |
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} |
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} |
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/* DWEN */ |
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if (opc == MMC_CMD_WRITE_SINGLE_BLOCK || |
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opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) |
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tmp |= CMD_SET_DWEN; |
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/* CMLTE/CMD12EN */ |
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if (opc == MMC_CMD_READ_MULTIPLE_BLOCK || |
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opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) { |
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tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; |
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sh_mmcif_bitset(data->blocks << 16, &host->regs->ce_block_set); |
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} |
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/* RIDXC[1:0] check bits */ |
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if (opc == MMC_CMD_SEND_OP_COND || opc == MMC_CMD_ALL_SEND_CID || |
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opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID) |
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tmp |= CMD_SET_RIDXC_BITS; |
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/* RCRC7C[1:0] check bits */ |
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if (opc == MMC_CMD_SEND_OP_COND) |
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tmp |= CMD_SET_CRC7C_BITS; |
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/* RCRC7C[1:0] internal CRC7 */ |
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if (opc == MMC_CMD_ALL_SEND_CID || |
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opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID) |
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tmp |= CMD_SET_CRC7C_INTERNAL; |
|
|
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return opc = ((opc << 24) | tmp); |
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} |
|
|
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static u32 sh_mmcif_data_trans(struct sh_mmcif_host *host, |
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struct mmc_data *data, u16 opc) |
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{ |
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u32 ret; |
|
|
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switch (opc) { |
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case MMC_CMD_READ_MULTIPLE_BLOCK: |
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ret = sh_mmcif_multi_read(host, data); |
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break; |
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case MMC_CMD_WRITE_MULTIPLE_BLOCK: |
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ret = sh_mmcif_multi_write(host, data); |
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break; |
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case MMC_CMD_WRITE_SINGLE_BLOCK: |
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ret = sh_mmcif_single_write(host, data); |
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break; |
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case MMC_CMD_READ_SINGLE_BLOCK: |
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case MMC_CMD_SEND_EXT_CSD: |
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ret = sh_mmcif_single_read(host, data); |
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break; |
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default: |
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printf(DRIVER_NAME": NOT SUPPORT CMD = d'%08d\n", opc); |
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ret = -EINVAL; |
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break; |
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} |
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return ret; |
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} |
|
|
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static int sh_mmcif_start_cmd(struct sh_mmcif_host *host, |
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struct mmc_data *data, struct mmc_cmd *cmd) |
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{ |
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long time; |
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int ret = 0, mask = 0; |
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u32 opc = cmd->cmdidx; |
|
|
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if (opc == MMC_CMD_STOP_TRANSMISSION) { |
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/* MMCIF sends the STOP command automatically */ |
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if (host->last_cmd == MMC_CMD_READ_MULTIPLE_BLOCK) |
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sh_mmcif_bitset(MASK_MCMD12DRE, |
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&host->regs->ce_int_mask); |
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else |
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sh_mmcif_bitset(MASK_MCMD12RBE, |
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&host->regs->ce_int_mask); |
|
|
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time = mmcif_wait_interrupt_flag(host); |
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if (time == 0 || host->sd_error != 0) |
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return sh_mmcif_error_manage(host); |
|
|
|
sh_mmcif_get_cmd12response(host, cmd); |
|
return 0; |
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} |
|
if (opc == MMC_CMD_SWITCH) |
|
mask = MASK_MRBSYE; |
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else |
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mask = MASK_MCRSPE; |
|
|
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mask |= MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | |
|
MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | |
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MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | |
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MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO; |
|
|
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if (host->data) { |
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sh_mmcif_write(0, &host->regs->ce_block_set); |
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sh_mmcif_write(data->blocksize, &host->regs->ce_block_set); |
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} |
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opc = sh_mmcif_set_cmd(host, data, cmd); |
|
|
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sh_mmcif_write(INT_START_MAGIC, &host->regs->ce_int); |
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sh_mmcif_write(mask, &host->regs->ce_int_mask); |
|
|
|
debug("CMD%d ARG:%08x\n", cmd->cmdidx, cmd->cmdarg); |
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/* set arg */ |
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sh_mmcif_write(cmd->cmdarg, &host->regs->ce_arg); |
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host->wait_int = 0; |
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/* set cmd */ |
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sh_mmcif_write(opc, &host->regs->ce_cmd_set); |
|
|
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time = mmcif_wait_interrupt_flag(host); |
|
if (time == 0) |
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return sh_mmcif_error_manage(host); |
|
|
|
if (host->sd_error) { |
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switch (cmd->cmdidx) { |
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case MMC_CMD_ALL_SEND_CID: |
|
case MMC_CMD_SELECT_CARD: |
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case MMC_CMD_APP_CMD: |
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ret = -ETIMEDOUT; |
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break; |
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default: |
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printf(DRIVER_NAME": Cmd(d'%d) err\n", cmd->cmdidx); |
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ret = sh_mmcif_error_manage(host); |
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break; |
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} |
|
host->sd_error = 0; |
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host->wait_int = 0; |
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return ret; |
|
} |
|
|
|
/* if no response */ |
|
if (!(opc & 0x00C00000)) |
|
return 0; |
|
|
|
if (host->wait_int == 1) { |
|
sh_mmcif_get_response(host, cmd); |
|
host->wait_int = 0; |
|
} |
|
if (host->data) |
|
ret = sh_mmcif_data_trans(host, data, cmd->cmdidx); |
|
host->last_cmd = cmd->cmdidx; |
|
|
|
return ret; |
|
} |
|
|
|
static int sh_mmcif_send_cmd_common(struct sh_mmcif_host *host, |
|
struct mmc_cmd *cmd, struct mmc_data *data) |
|
{ |
|
int ret; |
|
|
|
WATCHDOG_RESET(); |
|
|
|
switch (cmd->cmdidx) { |
|
case MMC_CMD_APP_CMD: |
|
return -ETIMEDOUT; |
|
case MMC_CMD_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */ |
|
if (data) |
|
/* ext_csd */ |
|
break; |
|
else |
|
/* send_if_cond cmd (not support) */ |
|
return -ETIMEDOUT; |
|
default: |
|
break; |
|
} |
|
host->sd_error = 0; |
|
host->data = data; |
|
ret = sh_mmcif_start_cmd(host, data, cmd); |
|
host->data = NULL; |
|
|
|
return ret; |
|
} |
|
|
|
static int sh_mmcif_set_ios_common(struct sh_mmcif_host *host, struct mmc *mmc) |
|
{ |
|
if (mmc->clock) |
|
sh_mmcif_clock_control(host, mmc->clock); |
|
|
|
if (mmc->bus_width == 8) |
|
host->bus_width = MMC_BUS_WIDTH_8; |
|
else if (mmc->bus_width == 4) |
|
host->bus_width = MMC_BUS_WIDTH_4; |
|
else |
|
host->bus_width = MMC_BUS_WIDTH_1; |
|
|
|
debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width); |
|
|
|
return 0; |
|
} |
|
|
|
static int sh_mmcif_initialize_common(struct sh_mmcif_host *host) |
|
{ |
|
sh_mmcif_sync_reset(host); |
|
sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask); |
|
return 0; |
|
} |
|
|
|
#ifndef CONFIG_DM_MMC |
|
static void *mmc_priv(struct mmc *mmc) |
|
{ |
|
return (void *)mmc->priv; |
|
} |
|
|
|
static int sh_mmcif_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, |
|
struct mmc_data *data) |
|
{ |
|
struct sh_mmcif_host *host = mmc_priv(mmc); |
|
|
|
return sh_mmcif_send_cmd_common(host, cmd, data); |
|
} |
|
|
|
static int sh_mmcif_set_ios(struct mmc *mmc) |
|
{ |
|
struct sh_mmcif_host *host = mmc_priv(mmc); |
|
|
|
return sh_mmcif_set_ios_common(host, mmc); |
|
} |
|
|
|
static int sh_mmcif_initialize(struct mmc *mmc) |
|
{ |
|
struct sh_mmcif_host *host = mmc_priv(mmc); |
|
|
|
return sh_mmcif_initialize_common(host); |
|
} |
|
|
|
static const struct mmc_ops sh_mmcif_ops = { |
|
.send_cmd = sh_mmcif_send_cmd, |
|
.set_ios = sh_mmcif_set_ios, |
|
.init = sh_mmcif_initialize, |
|
}; |
|
|
|
static struct mmc_config sh_mmcif_cfg = { |
|
.name = DRIVER_NAME, |
|
.ops = &sh_mmcif_ops, |
|
.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT | |
|
MMC_MODE_8BIT, |
|
.voltages = MMC_VDD_32_33 | MMC_VDD_33_34, |
|
.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, |
|
}; |
|
|
|
int mmcif_mmc_init(void) |
|
{ |
|
struct mmc *mmc; |
|
struct sh_mmcif_host *host = NULL; |
|
|
|
host = malloc(sizeof(struct sh_mmcif_host)); |
|
if (!host) |
|
return -ENOMEM; |
|
memset(host, 0, sizeof(*host)); |
|
|
|
host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR; |
|
host->clk = CONFIG_SH_MMCIF_CLK; |
|
|
|
sh_mmcif_cfg.f_min = MMC_CLK_DIV_MIN(host->clk); |
|
sh_mmcif_cfg.f_max = MMC_CLK_DIV_MAX(host->clk); |
|
|
|
mmc = mmc_create(&sh_mmcif_cfg, host); |
|
if (mmc == NULL) { |
|
free(host); |
|
return -ENOMEM; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
#else |
|
struct sh_mmcif_plat { |
|
struct mmc_config cfg; |
|
struct mmc mmc; |
|
}; |
|
|
|
int sh_mmcif_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, |
|
struct mmc_data *data) |
|
{ |
|
struct sh_mmcif_host *host = dev_get_priv(dev); |
|
|
|
return sh_mmcif_send_cmd_common(host, cmd, data); |
|
} |
|
|
|
int sh_mmcif_dm_set_ios(struct udevice *dev) |
|
{ |
|
struct sh_mmcif_host *host = dev_get_priv(dev); |
|
struct mmc *mmc = mmc_get_mmc_dev(dev); |
|
|
|
return sh_mmcif_set_ios_common(host, mmc); |
|
} |
|
|
|
static const struct dm_mmc_ops sh_mmcif_dm_ops = { |
|
.send_cmd = sh_mmcif_dm_send_cmd, |
|
.set_ios = sh_mmcif_dm_set_ios, |
|
}; |
|
|
|
static int sh_mmcif_dm_bind(struct udevice *dev) |
|
{ |
|
struct sh_mmcif_plat *plat = dev_get_platdata(dev); |
|
|
|
return mmc_bind(dev, &plat->mmc, &plat->cfg); |
|
} |
|
|
|
static int sh_mmcif_dm_probe(struct udevice *dev) |
|
{ |
|
struct sh_mmcif_plat *plat = dev_get_platdata(dev); |
|
struct sh_mmcif_host *host = dev_get_priv(dev); |
|
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); |
|
struct clk sh_mmcif_clk; |
|
fdt_addr_t base; |
|
int ret; |
|
|
|
base = devfdt_get_addr(dev); |
|
if (base == FDT_ADDR_T_NONE) |
|
return -EINVAL; |
|
|
|
host->regs = (struct sh_mmcif_regs *)devm_ioremap(dev, base, SZ_2K); |
|
if (!host->regs) |
|
return -ENOMEM; |
|
|
|
ret = clk_get_by_index(dev, 0, &sh_mmcif_clk); |
|
if (ret) { |
|
debug("failed to get clock, ret=%d\n", ret); |
|
return ret; |
|
} |
|
|
|
ret = clk_enable(&sh_mmcif_clk); |
|
if (ret) { |
|
debug("failed to enable clock, ret=%d\n", ret); |
|
return ret; |
|
} |
|
|
|
host->clk = clk_get_rate(&sh_mmcif_clk); |
|
|
|
plat->cfg.name = dev->name; |
|
plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; |
|
|
|
switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width", |
|
1)) { |
|
case 8: |
|
plat->cfg.host_caps |= MMC_MODE_8BIT; |
|
break; |
|
case 4: |
|
plat->cfg.host_caps |= MMC_MODE_4BIT; |
|
break; |
|
case 1: |
|
break; |
|
default: |
|
dev_err(dev, "Invalid \"bus-width\" value\n"); |
|
return -EINVAL; |
|
} |
|
|
|
sh_mmcif_initialize_common(host); |
|
|
|
plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34; |
|
plat->cfg.f_min = MMC_CLK_DIV_MIN(host->clk); |
|
plat->cfg.f_max = MMC_CLK_DIV_MAX(host->clk); |
|
plat->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; |
|
|
|
upriv->mmc = &plat->mmc; |
|
|
|
return 0; |
|
} |
|
|
|
static const struct udevice_id sh_mmcif_sd_match[] = { |
|
{ .compatible = "renesas,sh-mmcif" }, |
|
{ /* sentinel */ } |
|
}; |
|
|
|
U_BOOT_DRIVER(sh_mmcif_mmc) = { |
|
.name = "sh-mmcif", |
|
.id = UCLASS_MMC, |
|
.of_match = sh_mmcif_sd_match, |
|
.bind = sh_mmcif_dm_bind, |
|
.probe = sh_mmcif_dm_probe, |
|
.priv_auto_alloc_size = sizeof(struct sh_mmcif_host), |
|
.platdata_auto_alloc_size = sizeof(struct sh_mmcif_plat), |
|
.ops = &sh_mmcif_dm_ops, |
|
}; |
|
#endif
|
|
|