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451 lines
11 KiB
451 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* (C) Copyright 2013 ADVANSEE |
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* Benoît Thébaudeau <[email protected]> |
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* |
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* Based on Dirk Behme's |
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* https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c, |
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* which is based on Freescale's |
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* http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6, |
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* which is: |
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* Copyright (C) 2011 Freescale Semiconductor, Inc. |
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*/ |
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#include <common.h> |
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#include <fuse.h> |
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#include <linux/errno.h> |
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#include <asm/io.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/imx-regs.h> |
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#include <asm/mach-imx/sys_proto.h> |
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#define BO_CTRL_WR_UNLOCK 16 |
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#define BM_CTRL_WR_UNLOCK 0xffff0000 |
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#define BV_CTRL_WR_UNLOCK_KEY 0x3e77 |
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#define BM_CTRL_ERROR 0x00000200 |
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#define BM_CTRL_BUSY 0x00000100 |
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#define BO_CTRL_ADDR 0 |
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#ifdef CONFIG_MX7 |
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#define BM_CTRL_ADDR 0x0000000f |
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#define BM_CTRL_RELOAD 0x00000400 |
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#elif defined(CONFIG_MX7ULP) |
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#define BM_CTRL_ADDR 0x000000FF |
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#define BM_CTRL_RELOAD 0x00000400 |
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#define BM_OUT_STATUS_DED 0x00000400 |
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#define BM_OUT_STATUS_LOCKED 0x00000800 |
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#define BM_OUT_STATUS_PROGFAIL 0x00001000 |
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#elif defined(CONFIG_MX8M) |
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#define BM_CTRL_ADDR 0x000000ff |
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#else |
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#define BM_CTRL_ADDR 0x0000007f |
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#endif |
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#ifdef CONFIG_MX7 |
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#define BO_TIMING_FSOURCE 12 |
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#define BM_TIMING_FSOURCE 0x0007f000 |
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#define BV_TIMING_FSOURCE_NS 1001 |
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#define BO_TIMING_PROG 0 |
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#define BM_TIMING_PROG 0x00000fff |
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#define BV_TIMING_PROG_US 10 |
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#else |
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#define BO_TIMING_STROBE_READ 16 |
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#define BM_TIMING_STROBE_READ 0x003f0000 |
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#define BV_TIMING_STROBE_READ_NS 37 |
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#define BO_TIMING_RELAX 12 |
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#define BM_TIMING_RELAX 0x0000f000 |
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#define BV_TIMING_RELAX_NS 17 |
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#define BO_TIMING_STROBE_PROG 0 |
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#define BM_TIMING_STROBE_PROG 0x00000fff |
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#define BV_TIMING_STROBE_PROG_US 10 |
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#endif |
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#define BM_READ_CTRL_READ_FUSE 0x00000001 |
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#define BF(value, field) (((value) << BO_##field) & BM_##field) |
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#define WRITE_POSTAMBLE_US 2 |
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#if defined(CONFIG_MX6) || defined(CONFIG_VF610) |
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#define FUSE_BANK_SIZE 0x80 |
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#ifdef CONFIG_MX6SL |
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#define FUSE_BANKS 8 |
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#elif defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL) |
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#define FUSE_BANKS 9 |
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#else |
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#define FUSE_BANKS 16 |
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#endif |
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#elif defined CONFIG_MX7 |
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#define FUSE_BANK_SIZE 0x40 |
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#define FUSE_BANKS 16 |
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#elif defined(CONFIG_MX7ULP) |
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#define FUSE_BANK_SIZE 0x80 |
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#define FUSE_BANKS 31 |
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#elif defined(CONFIG_MX8M) |
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#define FUSE_BANK_SIZE 0x40 |
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#define FUSE_BANKS 64 |
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#else |
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#error "Unsupported architecture\n" |
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#endif |
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#if defined(CONFIG_MX6) |
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/* |
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* There is a hole in shadow registers address map of size 0x100 |
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* between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX, |
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* iMX6UL, i.MX6ULL and i.MX6SLL. |
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* Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses, |
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* we should account for this hole in address space. |
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* |
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* Similar hole exists between bank 14 and bank 15 of size |
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* 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX. |
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* Note: iMX6SL has only 0-7 banks and there is no hole. |
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* Note: iMX6UL doesn't have this one. |
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* |
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* This function is to covert user input to physical bank index. |
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* Only needed when read fuse, because we use register offset, so |
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* need to calculate real register offset. |
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* When write, no need to consider hole, always use the bank/word |
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* index from fuse map. |
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*/ |
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u32 fuse_bank_physical(int index) |
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{ |
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u32 phy_index; |
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if (is_mx6sl() || is_mx7ulp()) { |
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phy_index = index; |
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} else if (is_mx6ul() || is_mx6ull() || is_mx6sll()) { |
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if ((is_mx6ull() || is_mx6sll()) && index == 8) |
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index = 7; |
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if (index >= 6) |
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phy_index = fuse_bank_physical(5) + (index - 6) + 3; |
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else |
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phy_index = index; |
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} else { |
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if (index >= 15) |
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phy_index = fuse_bank_physical(14) + (index - 15) + 2; |
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else if (index >= 6) |
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phy_index = fuse_bank_physical(5) + (index - 6) + 3; |
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else |
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phy_index = index; |
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} |
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return phy_index; |
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} |
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u32 fuse_word_physical(u32 bank, u32 word_index) |
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{ |
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if (is_mx6ull() || is_mx6sll()) { |
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if (bank == 8) |
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word_index = word_index + 4; |
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} |
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return word_index; |
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} |
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#else |
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u32 fuse_bank_physical(int index) |
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{ |
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return index; |
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} |
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u32 fuse_word_physical(u32 bank, u32 word_index) |
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{ |
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return word_index; |
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} |
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#endif |
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static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us) |
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{ |
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while (readl(®s->ctrl) & BM_CTRL_BUSY) |
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udelay(delay_us); |
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} |
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static void clear_error(struct ocotp_regs *regs) |
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{ |
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writel(BM_CTRL_ERROR, ®s->ctrl_clr); |
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} |
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static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word, |
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int assert, const char *caller) |
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{ |
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*regs = (struct ocotp_regs *)OCOTP_BASE_ADDR; |
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if (bank >= FUSE_BANKS || |
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word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 || |
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!assert) { |
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printf("mxc_ocotp %s(): Invalid argument\n", caller); |
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return -EINVAL; |
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} |
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if (is_mx6ull() || is_mx6sll()) { |
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if ((bank == 7 || bank == 8) && |
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word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 3) { |
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printf("mxc_ocotp %s(): Invalid argument\n", caller); |
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return -EINVAL; |
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} |
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} |
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enable_ocotp_clk(1); |
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wait_busy(*regs, 1); |
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clear_error(*regs); |
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return 0; |
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} |
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static int finish_access(struct ocotp_regs *regs, const char *caller) |
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{ |
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u32 err; |
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err = !!(readl(®s->ctrl) & BM_CTRL_ERROR); |
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clear_error(regs); |
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#ifdef CONFIG_MX7ULP |
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/* Need to power down the OTP memory */ |
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writel(1, ®s->pdn); |
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#endif |
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if (err) { |
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printf("mxc_ocotp %s(): Access protect error\n", caller); |
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return -EIO; |
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} |
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return 0; |
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} |
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static int prepare_read(struct ocotp_regs **regs, u32 bank, u32 word, u32 *val, |
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const char *caller) |
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{ |
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return prepare_access(regs, bank, word, val != NULL, caller); |
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} |
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int fuse_read(u32 bank, u32 word, u32 *val) |
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{ |
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struct ocotp_regs *regs; |
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int ret; |
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u32 phy_bank; |
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u32 phy_word; |
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ret = prepare_read(®s, bank, word, val, __func__); |
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if (ret) |
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return ret; |
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phy_bank = fuse_bank_physical(bank); |
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phy_word = fuse_word_physical(bank, word); |
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*val = readl(®s->bank[phy_bank].fuse_regs[phy_word << 2]); |
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#ifdef CONFIG_MX7ULP |
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if (readl(®s->out_status) & BM_OUT_STATUS_DED) { |
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writel(BM_OUT_STATUS_DED, ®s->out_status_clr); |
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printf("mxc_ocotp %s(): fuse read wrong\n", __func__); |
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return -EIO; |
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} |
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#endif |
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return finish_access(regs, __func__); |
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} |
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#ifdef CONFIG_MX7 |
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static void set_timing(struct ocotp_regs *regs) |
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{ |
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u32 ipg_clk; |
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u32 fsource, prog; |
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u32 timing; |
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ipg_clk = mxc_get_clock(MXC_IPG_CLK); |
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fsource = DIV_ROUND_UP((ipg_clk / 1000) * BV_TIMING_FSOURCE_NS, |
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+ 1000000) + 1; |
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prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_PROG_US, 1000000) + 1; |
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timing = BF(fsource, TIMING_FSOURCE) | BF(prog, TIMING_PROG); |
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clrsetbits_le32(®s->timing, BM_TIMING_FSOURCE | BM_TIMING_PROG, |
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timing); |
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} |
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#elif defined(CONFIG_MX7ULP) |
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static void set_timing(struct ocotp_regs *regs) |
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{ |
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/* No timing set for MX7ULP */ |
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} |
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#else |
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static void set_timing(struct ocotp_regs *regs) |
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{ |
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u32 ipg_clk; |
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u32 relax, strobe_read, strobe_prog; |
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u32 timing; |
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ipg_clk = mxc_get_clock(MXC_IPG_CLK); |
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relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1; |
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strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS, |
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1000000000) + 2 * (relax + 1) - 1; |
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strobe_prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_STROBE_PROG_US, |
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1000000) + 2 * (relax + 1) - 1; |
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timing = BF(strobe_read, TIMING_STROBE_READ) | |
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BF(relax, TIMING_RELAX) | |
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BF(strobe_prog, TIMING_STROBE_PROG); |
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clrsetbits_le32(®s->timing, BM_TIMING_STROBE_READ | BM_TIMING_RELAX | |
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BM_TIMING_STROBE_PROG, timing); |
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} |
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#endif |
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static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word, |
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int write) |
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{ |
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u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0; |
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#ifdef CONFIG_MX7 |
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u32 addr = bank; |
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#elif defined CONFIG_MX8M |
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u32 addr = bank << 2 | word; |
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#else |
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u32 addr; |
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/* Bank 7 and Bank 8 only supports 4 words each for i.MX6ULL */ |
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if ((is_mx6ull() || is_mx6sll()) && (bank > 7)) { |
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bank = bank - 1; |
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word += 4; |
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} |
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addr = bank << 3 | word; |
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#endif |
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set_timing(regs); |
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clrsetbits_le32(®s->ctrl, BM_CTRL_WR_UNLOCK | BM_CTRL_ADDR, |
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BF(wr_unlock, CTRL_WR_UNLOCK) | |
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BF(addr, CTRL_ADDR)); |
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} |
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int fuse_sense(u32 bank, u32 word, u32 *val) |
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{ |
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struct ocotp_regs *regs; |
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int ret; |
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ret = prepare_read(®s, bank, word, val, __func__); |
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if (ret) |
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return ret; |
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setup_direct_access(regs, bank, word, false); |
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writel(BM_READ_CTRL_READ_FUSE, ®s->read_ctrl); |
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wait_busy(regs, 1); |
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#ifdef CONFIG_MX7 |
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*val = readl((®s->read_fuse_data0) + (word << 2)); |
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#else |
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*val = readl(®s->read_fuse_data); |
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#endif |
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#ifdef CONFIG_MX7ULP |
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if (readl(®s->out_status) & BM_OUT_STATUS_DED) { |
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writel(BM_OUT_STATUS_DED, ®s->out_status_clr); |
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printf("mxc_ocotp %s(): fuse read wrong\n", __func__); |
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return -EIO; |
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} |
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#endif |
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return finish_access(regs, __func__); |
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} |
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static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word, |
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const char *caller) |
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{ |
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#ifdef CONFIG_MX7ULP |
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u32 val; |
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int ret; |
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/* Only bank 0 and 1 are redundancy mode, others are ECC mode */ |
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if (bank != 0 && bank != 1) { |
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ret = fuse_sense(bank, word, &val); |
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if (ret) |
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return ret; |
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if (val != 0) { |
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printf("mxc_ocotp: The word has been programmed, no more write\n"); |
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return -EPERM; |
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} |
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} |
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#endif |
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return prepare_access(regs, bank, word, true, caller); |
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} |
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int fuse_prog(u32 bank, u32 word, u32 val) |
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{ |
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struct ocotp_regs *regs; |
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int ret; |
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ret = prepare_write(®s, bank, word, __func__); |
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if (ret) |
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return ret; |
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setup_direct_access(regs, bank, word, true); |
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#ifdef CONFIG_MX7 |
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switch (word) { |
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case 0: |
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writel(0, ®s->data1); |
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writel(0, ®s->data2); |
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writel(0, ®s->data3); |
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writel(val, ®s->data0); |
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break; |
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case 1: |
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writel(val, ®s->data1); |
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writel(0, ®s->data2); |
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writel(0, ®s->data3); |
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writel(0, ®s->data0); |
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break; |
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case 2: |
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writel(0, ®s->data1); |
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writel(val, ®s->data2); |
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writel(0, ®s->data3); |
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writel(0, ®s->data0); |
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break; |
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case 3: |
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writel(0, ®s->data1); |
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writel(0, ®s->data2); |
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writel(val, ®s->data3); |
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writel(0, ®s->data0); |
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break; |
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} |
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wait_busy(regs, BV_TIMING_PROG_US); |
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#else |
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writel(val, ®s->data); |
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wait_busy(regs, BV_TIMING_STROBE_PROG_US); |
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#endif |
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udelay(WRITE_POSTAMBLE_US); |
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#ifdef CONFIG_MX7ULP |
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if (readl(®s->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) { |
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writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), ®s->out_status_clr); |
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printf("mxc_ocotp %s(): fuse write is failed\n", __func__); |
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return -EIO; |
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} |
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#endif |
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return finish_access(regs, __func__); |
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} |
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int fuse_override(u32 bank, u32 word, u32 val) |
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{ |
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struct ocotp_regs *regs; |
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int ret; |
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u32 phy_bank; |
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u32 phy_word; |
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ret = prepare_write(®s, bank, word, __func__); |
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if (ret) |
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return ret; |
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phy_bank = fuse_bank_physical(bank); |
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phy_word = fuse_word_physical(bank, word); |
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writel(val, ®s->bank[phy_bank].fuse_regs[phy_word << 2]); |
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#ifdef CONFIG_MX7ULP |
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if (readl(®s->out_status) & (BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED)) { |
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writel((BM_OUT_STATUS_PROGFAIL | BM_OUT_STATUS_LOCKED), ®s->out_status_clr); |
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printf("mxc_ocotp %s(): fuse write is failed\n", __func__); |
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return -EIO; |
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} |
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#endif |
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return finish_access(regs, __func__); |
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}
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