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278 lines
7.2 KiB
278 lines
7.2 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Renesas RCar Gen2 CPG MSSR driver |
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* |
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* Copyright (C) 2017 Marek Vasut <[email protected]> |
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* |
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* Based on the following driver from Linux kernel: |
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* r8a7796 Clock Pulse Generator / Module Standby and Software Reset |
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* |
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* Copyright (C) 2016 Glider bvba |
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*/ |
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#include <common.h> |
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#include <clk-uclass.h> |
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#include <dm.h> |
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#include <errno.h> |
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#include <asm/io.h> |
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#include <dt-bindings/clock/renesas-cpg-mssr.h> |
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#include "renesas-cpg-mssr.h" |
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#include "rcar-gen2-cpg.h" |
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#define CPG_RST_MODEMR 0x0060 |
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#define CPG_PLL0CR 0x00d8 |
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#define CPG_SDCKCR 0x0074 |
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struct clk_div_table { |
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u8 val; |
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u8 div; |
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}; |
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/* SDHI divisors */ |
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static const struct clk_div_table cpg_sdh_div_table[] = { |
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{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, |
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{ 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 }, |
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{ 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 }, |
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}; |
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static const struct clk_div_table cpg_sd01_div_table[] = { |
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{ 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 }, |
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{ 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 }, |
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{ 0, 0 }, |
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}; |
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static u8 gen2_clk_get_sdh_div(const struct clk_div_table *table, u8 div) |
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{ |
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while ((*table++).val) { |
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if ((*table).div == div) |
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return div; |
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} |
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return 0xff; |
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} |
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static int gen2_clk_enable(struct clk *clk) |
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{ |
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struct gen2_clk_priv *priv = dev_get_priv(clk->dev); |
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return renesas_clk_endisable(clk, priv->base, true); |
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} |
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static int gen2_clk_disable(struct clk *clk) |
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{ |
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struct gen2_clk_priv *priv = dev_get_priv(clk->dev); |
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return renesas_clk_endisable(clk, priv->base, false); |
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} |
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static ulong gen2_clk_get_rate(struct clk *clk) |
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{ |
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struct gen2_clk_priv *priv = dev_get_priv(clk->dev); |
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struct cpg_mssr_info *info = priv->info; |
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struct clk parent; |
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const struct cpg_core_clk *core; |
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const struct rcar_gen2_cpg_pll_config *pll_config = |
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priv->cpg_pll_config; |
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u32 value, mult, div, rate = 0; |
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int ret; |
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debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id); |
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ret = renesas_clk_get_parent(clk, info, &parent); |
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if (ret) { |
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printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret); |
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return ret; |
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} |
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if (renesas_clk_is_mod(clk)) { |
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rate = gen2_clk_get_rate(&parent); |
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debug("%s[%i] MOD clk: parent=%lu => rate=%u\n", |
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__func__, __LINE__, parent.id, rate); |
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return rate; |
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} |
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ret = renesas_clk_get_core(clk, info, &core); |
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if (ret) |
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return ret; |
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switch (core->type) { |
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case CLK_TYPE_IN: |
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if (core->id == info->clk_extal_id) { |
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rate = clk_get_rate(&priv->clk_extal); |
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debug("%s[%i] EXTAL clk: rate=%u\n", |
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__func__, __LINE__, rate); |
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return rate; |
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} |
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if (core->id == info->clk_extal_usb_id) { |
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rate = clk_get_rate(&priv->clk_extal_usb); |
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debug("%s[%i] EXTALR clk: rate=%u\n", |
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__func__, __LINE__, rate); |
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return rate; |
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} |
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return -EINVAL; |
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case CLK_TYPE_FF: |
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rate = (gen2_clk_get_rate(&parent) * core->mult) / core->div; |
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debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n", |
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__func__, __LINE__, |
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core->parent, core->mult, core->div, rate); |
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return rate; |
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case CLK_TYPE_DIV6P1: /* DIV6 Clock with 1 parent clock */ |
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value = (readl(priv->base + core->offset) & 0x3f) + 1; |
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rate = gen2_clk_get_rate(&parent) / value; |
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debug("%s[%i] DIV6P1 clk: parent=%i div=%i => rate=%u\n", |
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__func__, __LINE__, |
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core->parent, value, rate); |
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return rate; |
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case CLK_TYPE_GEN2_MAIN: |
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rate = gen2_clk_get_rate(&parent) / pll_config->extal_div; |
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debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%u\n", |
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__func__, __LINE__, |
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core->parent, pll_config->extal_div, rate); |
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return rate; |
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case CLK_TYPE_GEN2_PLL0: |
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/* |
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* PLL0 is a configurable multiplier clock except on R-Car |
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* V2H/E2. Register the PLL0 clock as a fixed factor clock for |
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* now as there's no generic multiplier clock implementation and |
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* we currently have no need to change the multiplier value. |
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*/ |
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mult = pll_config->pll0_mult; |
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if (!mult) { |
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value = readl(priv->base + CPG_PLL0CR); |
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mult = (((value >> 24) & 0x7f) + 1) * 2; |
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} |
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rate = (gen2_clk_get_rate(&parent) * mult) / info->pll0_div; |
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debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%u\n", |
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__func__, __LINE__, core->parent, mult, rate); |
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return rate; |
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case CLK_TYPE_GEN2_PLL1: |
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rate = (gen2_clk_get_rate(&parent) * pll_config->pll1_mult) / 2; |
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debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%u\n", |
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__func__, __LINE__, |
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core->parent, pll_config->pll1_mult, rate); |
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return rate; |
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case CLK_TYPE_GEN2_PLL3: |
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rate = gen2_clk_get_rate(&parent) * pll_config->pll3_mult; |
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debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%u\n", |
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__func__, __LINE__, |
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core->parent, pll_config->pll3_mult, rate); |
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return rate; |
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case CLK_TYPE_GEN2_SDH: |
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value = (readl(priv->base + CPG_SDCKCR) >> 8) & 0xf; |
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div = gen2_clk_get_sdh_div(cpg_sdh_div_table, value); |
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rate = gen2_clk_get_rate(&parent) / div; |
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debug("%s[%i] SDH clk: parent=%i div=%i => rate=%u\n", |
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__func__, __LINE__, |
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core->parent, div, rate); |
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return rate; |
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case CLK_TYPE_GEN2_SD0: |
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value = (readl(priv->base + CPG_SDCKCR) >> 4) & 0xf; |
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div = gen2_clk_get_sdh_div(cpg_sd01_div_table, value); |
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rate = gen2_clk_get_rate(&parent) / div; |
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debug("%s[%i] SD0 clk: parent=%i div=%i => rate=%u\n", |
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__func__, __LINE__, |
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core->parent, div, rate); |
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return rate; |
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case CLK_TYPE_GEN2_SD1: |
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value = (readl(priv->base + CPG_SDCKCR) >> 0) & 0xf; |
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div = gen2_clk_get_sdh_div(cpg_sd01_div_table, value); |
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rate = gen2_clk_get_rate(&parent) / div; |
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debug("%s[%i] SD1 clk: parent=%i div=%i => rate=%u\n", |
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__func__, __LINE__, |
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core->parent, div, rate); |
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return rate; |
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} |
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printf("%s[%i] unknown fail\n", __func__, __LINE__); |
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return -ENOENT; |
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} |
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static ulong gen2_clk_set_rate(struct clk *clk, ulong rate) |
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{ |
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return gen2_clk_get_rate(clk); |
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} |
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static int gen2_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) |
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{ |
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if (args->args_count != 2) { |
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debug("Invaild args_count: %d\n", args->args_count); |
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return -EINVAL; |
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} |
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clk->id = (args->args[0] << 16) | args->args[1]; |
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return 0; |
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} |
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const struct clk_ops gen2_clk_ops = { |
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.enable = gen2_clk_enable, |
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.disable = gen2_clk_disable, |
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.get_rate = gen2_clk_get_rate, |
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.set_rate = gen2_clk_set_rate, |
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.of_xlate = gen2_clk_of_xlate, |
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}; |
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int gen2_clk_probe(struct udevice *dev) |
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{ |
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struct gen2_clk_priv *priv = dev_get_priv(dev); |
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struct cpg_mssr_info *info = |
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(struct cpg_mssr_info *)dev_get_driver_data(dev); |
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fdt_addr_t rst_base; |
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u32 cpg_mode; |
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int ret; |
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priv->base = (struct gen2_base *)devfdt_get_addr(dev); |
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if (!priv->base) |
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return -EINVAL; |
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priv->info = info; |
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ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, info->reset_node); |
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if (ret < 0) |
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return ret; |
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rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg"); |
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if (rst_base == FDT_ADDR_T_NONE) |
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return -EINVAL; |
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cpg_mode = readl(rst_base + CPG_RST_MODEMR); |
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priv->cpg_pll_config = |
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(struct rcar_gen2_cpg_pll_config *)info->get_pll_config(cpg_mode); |
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if (!priv->cpg_pll_config->extal_div) |
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return -EINVAL; |
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ret = clk_get_by_name(dev, "extal", &priv->clk_extal); |
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if (ret < 0) |
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return ret; |
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if (info->extal_usb_node) { |
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ret = clk_get_by_name(dev, info->extal_usb_node, |
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&priv->clk_extal_usb); |
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if (ret < 0) |
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return ret; |
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} |
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return 0; |
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} |
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int gen2_clk_remove(struct udevice *dev) |
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{ |
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struct gen2_clk_priv *priv = dev_get_priv(dev); |
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return renesas_clk_remove(priv->base, priv->info); |
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}
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