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410 lines
9.3 KiB
410 lines
9.3 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* (C) Copyright 2017 |
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* Mario Six, Guntermann & Drunck GmbH, [email protected] |
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*/ |
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#include <common.h> |
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#include <clk-uclass.h> |
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#include <dm.h> |
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#include <dm/lists.h> |
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#include <dt-bindings/clk/mpc83xx-clk.h> |
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#include <asm/arch/soc.h> |
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#include "mpc83xx_clk.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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/** |
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* struct mpc83xx_clk_priv - Private data structure for the MPC83xx clock |
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* driver |
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* @speed: Array containing the speed values of all system clocks (initialized |
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* once, then only read back) |
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*/ |
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struct mpc83xx_clk_priv { |
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u32 speed[MPC83XX_CLK_COUNT]; |
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}; |
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/** |
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* is_clk_valid() - Check if clock ID is valid for given clock device |
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* @clk: The clock device for which to check a clock ID |
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* @id: The clock ID to check |
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* |
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* Return: true if clock ID is valid for clock device, false if not |
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*/ |
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static inline bool is_clk_valid(struct udevice *clk, int id) |
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{ |
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ulong type = dev_get_driver_data(clk); |
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switch (id) { |
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case MPC83XX_CLK_MEM: |
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return true; |
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case MPC83XX_CLK_MEM_SEC: |
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return type == SOC_MPC8360; |
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case MPC83XX_CLK_ENC: |
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return (type == SOC_MPC8308) || (type == SOC_MPC8309); |
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case MPC83XX_CLK_I2C1: |
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return true; |
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case MPC83XX_CLK_TDM: |
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return type == SOC_MPC8315; |
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case MPC83XX_CLK_SDHC: |
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return mpc83xx_has_sdhc(type); |
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case MPC83XX_CLK_TSEC1: |
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case MPC83XX_CLK_TSEC2: |
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return mpc83xx_has_tsec(type); |
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case MPC83XX_CLK_USBDR: |
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return type == SOC_MPC8360; |
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case MPC83XX_CLK_USBMPH: |
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return type == SOC_MPC8349; |
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case MPC83XX_CLK_PCIEXP1: |
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return mpc83xx_has_pcie1(type); |
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case MPC83XX_CLK_PCIEXP2: |
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return mpc83xx_has_pcie2(type); |
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case MPC83XX_CLK_SATA: |
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return mpc83xx_has_sata(type); |
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case MPC83XX_CLK_DMAC: |
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return (type == SOC_MPC8308) || (type == SOC_MPC8309); |
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case MPC83XX_CLK_PCI: |
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return mpc83xx_has_pci(type); |
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case MPC83XX_CLK_CSB: |
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return true; |
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case MPC83XX_CLK_I2C2: |
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return mpc83xx_has_second_i2c(type); |
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case MPC83XX_CLK_QE: |
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case MPC83XX_CLK_BRG: |
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return mpc83xx_has_quicc_engine(type) && (type != SOC_MPC8309); |
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case MPC83XX_CLK_LCLK: |
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case MPC83XX_CLK_LBIU: |
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case MPC83XX_CLK_CORE: |
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return true; |
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} |
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return false; |
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} |
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/** |
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* init_single_clk() - Initialize a clock with a given ID |
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* @dev: The clock device for which to initialize the clock |
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* @clk: The clock ID |
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* |
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* The clock speed is read from the hardware's registers, and stored in the |
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* private data structure of the driver. From there it is only retrieved, and |
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* not set. |
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* |
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* Return: 0 if OK, -ve on error |
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*/ |
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static int init_single_clk(struct udevice *dev, int clk) |
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{ |
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struct mpc83xx_clk_priv *priv = dev_get_priv(dev); |
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
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ulong type = dev_get_driver_data(dev); |
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struct clk_mode mode; |
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ulong mask; |
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u32 csb_clk = get_csb_clk(im); |
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int ret; |
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ret = retrieve_mode(clk, type, &mode); |
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if (ret) { |
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debug("%s: Could not retrieve mode for clk %d (ret = %d)\n", |
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dev->name, clk, ret); |
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return ret; |
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} |
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if (mode.type == TYPE_INVALID) { |
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debug("%s: clock %d invalid\n", dev->name, clk); |
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return -EINVAL; |
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} |
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if (mode.type == TYPE_SCCR_STANDARD) { |
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mask = GENMASK(31 - mode.low, 31 - mode.high); |
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switch (sccr_field(im, mask)) { |
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case 0: |
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priv->speed[clk] = 0; |
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break; |
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case 1: |
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priv->speed[clk] = csb_clk; |
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break; |
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case 2: |
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priv->speed[clk] = csb_clk / 2; |
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break; |
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case 3: |
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priv->speed[clk] = csb_clk / 3; |
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break; |
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default: |
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priv->speed[clk] = 0; |
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} |
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return 0; |
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} |
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if (mode.type == TYPE_SPMR_DIRECT_MULTIPLY) { |
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mask = GENMASK(31 - mode.low, 31 - mode.high); |
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priv->speed[clk] = csb_clk * (1 + sccr_field(im, mask)); |
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return 0; |
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} |
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if (clk == MPC83XX_CLK_CSB || clk == MPC83XX_CLK_I2C2) { |
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priv->speed[clk] = csb_clk; /* i2c-2 clk is equal to csb clk */ |
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return 0; |
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} |
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if (clk == MPC83XX_CLK_QE || clk == MPC83XX_CLK_BRG) { |
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u32 pci_sync_in = get_pci_sync_in(im); |
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u32 qepmf = spmr_field(im, SPMR_CEPMF); |
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u32 qepdf = spmr_field(im, SPMR_CEPDF); |
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u32 qe_clk = (pci_sync_in * qepmf) / (1 + qepdf); |
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if (clk == MPC83XX_CLK_QE) |
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priv->speed[clk] = qe_clk; |
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else |
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priv->speed[clk] = qe_clk / 2; |
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return 0; |
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} |
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if (clk == MPC83XX_CLK_LCLK || clk == MPC83XX_CLK_LBIU) { |
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u32 lbiu_clk = csb_clk * |
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(1 + spmr_field(im, SPMR_LBIUCM)); |
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u32 clkdiv = lcrr_field(im, LCRR_CLKDIV); |
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if (clk == MPC83XX_CLK_LBIU) |
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priv->speed[clk] = lbiu_clk; |
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switch (clkdiv) { |
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case 2: |
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case 4: |
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case 8: |
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priv->speed[clk] = lbiu_clk / clkdiv; |
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break; |
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default: |
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/* unknown lcrr */ |
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priv->speed[clk] = 0; |
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} |
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return 0; |
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} |
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if (clk == MPC83XX_CLK_CORE) { |
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u8 corepll = spmr_field(im, SPMR_COREPLL); |
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u32 corecnf_tab_index = ((corepll & 0x1F) << 2) | |
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((corepll & 0x60) >> 5); |
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if (corecnf_tab_index > (ARRAY_SIZE(corecnf_tab))) { |
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debug("%s: Core configuration index %02x too high; possible wrong value", |
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dev->name, corecnf_tab_index); |
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return -EINVAL; |
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} |
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switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) { |
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case RAT_BYP: |
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case RAT_1_TO_1: |
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priv->speed[clk] = csb_clk; |
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break; |
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case RAT_1_5_TO_1: |
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priv->speed[clk] = (3 * csb_clk) / 2; |
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break; |
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case RAT_2_TO_1: |
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priv->speed[clk] = 2 * csb_clk; |
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break; |
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case RAT_2_5_TO_1: |
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priv->speed[clk] = (5 * csb_clk) / 2; |
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break; |
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case RAT_3_TO_1: |
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priv->speed[clk] = 3 * csb_clk; |
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break; |
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default: |
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/* unknown core to csb ratio */ |
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priv->speed[clk] = 0; |
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} |
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return 0; |
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} |
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/* Unknown clk value -> error */ |
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debug("%s: clock %d invalid\n", dev->name, clk); |
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return -EINVAL; |
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} |
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/** |
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* init_all_clks() - Initialize all clocks of a clock device |
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* @dev: The clock device whose clocks should be initialized |
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* |
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* Return: 0 if OK, -ve on error |
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*/ |
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static inline int init_all_clks(struct udevice *dev) |
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{ |
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int i; |
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for (i = 0; i < MPC83XX_CLK_COUNT; i++) { |
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int ret; |
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if (!is_clk_valid(dev, i)) |
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continue; |
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ret = init_single_clk(dev, i); |
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if (ret) { |
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debug("%s: Failed to initialize %s clock\n", |
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dev->name, names[i]); |
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return ret; |
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} |
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} |
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return 0; |
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} |
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static int mpc83xx_clk_request(struct clk *clock) |
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{ |
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/* Reject requests of clocks that are not available */ |
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if (is_clk_valid(clock->dev, clock->id)) |
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return 0; |
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else |
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return -ENODEV; |
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} |
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static ulong mpc83xx_clk_get_rate(struct clk *clk) |
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{ |
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struct mpc83xx_clk_priv *priv = dev_get_priv(clk->dev); |
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if (clk->id >= MPC83XX_CLK_COUNT) { |
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debug("%s: clock index %lu invalid\n", __func__, clk->id); |
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return 0; |
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} |
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return priv->speed[clk->id]; |
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} |
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int get_clocks(void) |
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{ |
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/* Empty implementation to keep the prototype in common.h happy */ |
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return 0; |
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} |
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int get_serial_clock(void) |
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{ |
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struct mpc83xx_clk_priv *priv; |
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struct udevice *clk; |
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int ret; |
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ret = uclass_first_device_err(UCLASS_CLK, &clk); |
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if (ret) { |
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debug("%s: Could not get clock device\n", __func__); |
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return ret; |
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} |
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priv = dev_get_priv(clk); |
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return priv->speed[MPC83XX_CLK_CSB]; |
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} |
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const struct clk_ops mpc83xx_clk_ops = { |
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.request = mpc83xx_clk_request, |
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.get_rate = mpc83xx_clk_get_rate, |
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}; |
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static const struct udevice_id mpc83xx_clk_match[] = { |
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{ .compatible = "fsl,mpc8308-clk", .data = SOC_MPC8308 }, |
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{ .compatible = "fsl,mpc8309-clk", .data = SOC_MPC8309 }, |
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{ .compatible = "fsl,mpc8313-clk", .data = SOC_MPC8313 }, |
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{ .compatible = "fsl,mpc8315-clk", .data = SOC_MPC8315 }, |
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{ .compatible = "fsl,mpc832x-clk", .data = SOC_MPC832X }, |
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{ .compatible = "fsl,mpc8349-clk", .data = SOC_MPC8349 }, |
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{ .compatible = "fsl,mpc8360-clk", .data = SOC_MPC8360 }, |
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{ .compatible = "fsl,mpc8379-clk", .data = SOC_MPC8379 }, |
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{ /* sentinel */ } |
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}; |
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static int mpc83xx_clk_probe(struct udevice *dev) |
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{ |
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struct mpc83xx_clk_priv *priv = dev_get_priv(dev); |
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ulong type; |
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int ret; |
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ret = init_all_clks(dev); |
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if (ret) { |
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debug("%s: Could not initialize all clocks (ret = %d)\n", |
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dev->name, ret); |
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return ret; |
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} |
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type = dev_get_driver_data(dev); |
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if (mpc83xx_has_sdhc(type)) |
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gd->arch.sdhc_clk = priv->speed[MPC83XX_CLK_SDHC]; |
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gd->arch.core_clk = priv->speed[MPC83XX_CLK_CORE]; |
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gd->arch.i2c1_clk = priv->speed[MPC83XX_CLK_I2C1]; |
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if (mpc83xx_has_second_i2c(type)) |
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gd->arch.i2c2_clk = priv->speed[MPC83XX_CLK_I2C2]; |
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gd->mem_clk = priv->speed[MPC83XX_CLK_MEM]; |
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if (mpc83xx_has_pci(type)) |
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gd->pci_clk = priv->speed[MPC83XX_CLK_PCI]; |
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gd->cpu_clk = priv->speed[MPC83XX_CLK_CORE]; |
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gd->bus_clk = priv->speed[MPC83XX_CLK_CSB]; |
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return 0; |
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} |
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static int mpc83xx_clk_bind(struct udevice *dev) |
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{ |
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int ret; |
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struct udevice *sys_child; |
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/* |
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* Since there is no corresponding device tree entry, and since the |
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* clock driver has to be present in either case, bind the sysreset |
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* driver here. |
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*/ |
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ret = device_bind_driver(dev, "mpc83xx_sysreset", "sysreset", |
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&sys_child); |
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if (ret) |
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debug("%s: No sysreset driver: ret=%d\n", |
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dev->name, ret); |
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return 0; |
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} |
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U_BOOT_DRIVER(mpc83xx_clk) = { |
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.name = "mpc83xx_clk", |
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.id = UCLASS_CLK, |
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.of_match = mpc83xx_clk_match, |
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.ops = &mpc83xx_clk_ops, |
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.probe = mpc83xx_clk_probe, |
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.priv_auto_alloc_size = sizeof(struct mpc83xx_clk_priv), |
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.bind = mpc83xx_clk_bind, |
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}; |
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static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
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{ |
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int i; |
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char buf[32]; |
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struct udevice *clk; |
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int ret; |
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struct mpc83xx_clk_priv *priv; |
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ret = uclass_first_device_err(UCLASS_CLK, &clk); |
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if (ret) { |
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debug("%s: Could not get clock device\n", __func__); |
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return ret; |
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} |
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for (i = 0; i < MPC83XX_CLK_COUNT; i++) { |
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if (!is_clk_valid(clk, i)) |
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continue; |
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priv = dev_get_priv(clk); |
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printf("%s = %s MHz\n", names[i], strmhz(buf, priv->speed[i])); |
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} |
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return 0; |
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} |
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U_BOOT_CMD(clocks, 1, 1, do_clocks, |
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"display values of SoC's clocks", |
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"" |
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);
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