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487 lines
11 KiB
487 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright (C) 2017 Weidmüller Interface GmbH & Co. KG |
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* Stefan Herbrechtsmeier <[email protected]> |
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* |
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* Copyright (C) 2013 Soren Brinkmann <[email protected]> |
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* Copyright (C) 2013 Xilinx, Inc. All rights reserved. |
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*/ |
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#include <common.h> |
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#include <clk-uclass.h> |
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#include <dm.h> |
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#include <dm/lists.h> |
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#include <errno.h> |
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#include <asm/io.h> |
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#include <asm/arch/clk.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/sys_proto.h> |
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/* Register bitfield defines */ |
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#define PLLCTRL_FBDIV_MASK 0x7f000 |
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#define PLLCTRL_FBDIV_SHIFT 12 |
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#define PLLCTRL_BPFORCE_MASK (1 << 4) |
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#define PLLCTRL_PWRDWN_MASK 2 |
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#define PLLCTRL_PWRDWN_SHIFT 1 |
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#define PLLCTRL_RESET_MASK 1 |
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#define PLLCTRL_RESET_SHIFT 0 |
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#define ZYNQ_CLK_MAXDIV 0x3f |
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#define CLK_CTRL_DIV1_SHIFT 20 |
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#define CLK_CTRL_DIV1_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT) |
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#define CLK_CTRL_DIV0_SHIFT 8 |
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#define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT) |
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#define CLK_CTRL_SRCSEL_SHIFT 4 |
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#define CLK_CTRL_SRCSEL_MASK (0x3 << CLK_CTRL_SRCSEL_SHIFT) |
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#define CLK_CTRL_DIV2X_SHIFT 26 |
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#define CLK_CTRL_DIV2X_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV2X_SHIFT) |
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#define CLK_CTRL_DIV3X_SHIFT 20 |
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#define CLK_CTRL_DIV3X_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV3X_SHIFT) |
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DECLARE_GLOBAL_DATA_PTR; |
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#ifndef CONFIG_SPL_BUILD |
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enum zynq_clk_rclk {mio_clk, emio_clk}; |
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#endif |
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struct zynq_clk_priv { |
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ulong ps_clk_freq; |
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#ifndef CONFIG_SPL_BUILD |
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struct clk gem_emio_clk[2]; |
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#endif |
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}; |
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static void *zynq_clk_get_register(enum zynq_clk id) |
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{ |
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switch (id) { |
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case armpll_clk: |
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return &slcr_base->arm_pll_ctrl; |
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case ddrpll_clk: |
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return &slcr_base->ddr_pll_ctrl; |
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case iopll_clk: |
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return &slcr_base->io_pll_ctrl; |
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case lqspi_clk: |
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return &slcr_base->lqspi_clk_ctrl; |
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case smc_clk: |
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return &slcr_base->smc_clk_ctrl; |
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case pcap_clk: |
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return &slcr_base->pcap_clk_ctrl; |
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case sdio0_clk ... sdio1_clk: |
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return &slcr_base->sdio_clk_ctrl; |
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case uart0_clk ... uart1_clk: |
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return &slcr_base->uart_clk_ctrl; |
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case spi0_clk ... spi1_clk: |
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return &slcr_base->spi_clk_ctrl; |
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#ifndef CONFIG_SPL_BUILD |
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case dci_clk: |
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return &slcr_base->dci_clk_ctrl; |
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case gem0_clk: |
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return &slcr_base->gem0_clk_ctrl; |
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case gem1_clk: |
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return &slcr_base->gem1_clk_ctrl; |
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case fclk0_clk: |
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return &slcr_base->fpga0_clk_ctrl; |
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case fclk1_clk: |
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return &slcr_base->fpga1_clk_ctrl; |
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case fclk2_clk: |
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return &slcr_base->fpga2_clk_ctrl; |
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case fclk3_clk: |
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return &slcr_base->fpga3_clk_ctrl; |
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case can0_clk ... can1_clk: |
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return &slcr_base->can_clk_ctrl; |
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case dbg_trc_clk ... dbg_apb_clk: |
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/* fall through */ |
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#endif |
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default: |
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return &slcr_base->dbg_clk_ctrl; |
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} |
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} |
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static enum zynq_clk zynq_clk_get_cpu_pll(u32 clk_ctrl) |
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{ |
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u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; |
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switch (srcsel) { |
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case 2: |
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return ddrpll_clk; |
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case 3: |
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return iopll_clk; |
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case 0 ... 1: |
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default: |
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return armpll_clk; |
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} |
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} |
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static enum zynq_clk zynq_clk_get_peripheral_pll(u32 clk_ctrl) |
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{ |
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u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; |
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switch (srcsel) { |
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case 2: |
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return armpll_clk; |
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case 3: |
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return ddrpll_clk; |
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case 0 ... 1: |
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default: |
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return iopll_clk; |
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} |
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} |
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static ulong zynq_clk_get_pll_rate(struct zynq_clk_priv *priv, enum zynq_clk id) |
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{ |
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u32 clk_ctrl, reset, pwrdwn, mul, bypass; |
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clk_ctrl = readl(zynq_clk_get_register(id)); |
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reset = (clk_ctrl & PLLCTRL_RESET_MASK) >> PLLCTRL_RESET_SHIFT; |
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pwrdwn = (clk_ctrl & PLLCTRL_PWRDWN_MASK) >> PLLCTRL_PWRDWN_SHIFT; |
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if (reset || pwrdwn) |
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return 0; |
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bypass = clk_ctrl & PLLCTRL_BPFORCE_MASK; |
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if (bypass) |
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mul = 1; |
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else |
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mul = (clk_ctrl & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT; |
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return priv->ps_clk_freq * mul; |
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} |
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#ifndef CONFIG_SPL_BUILD |
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static enum zynq_clk_rclk zynq_clk_get_gem_rclk(enum zynq_clk id) |
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{ |
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u32 clk_ctrl, srcsel; |
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if (id == gem0_clk) |
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clk_ctrl = readl(&slcr_base->gem0_rclk_ctrl); |
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else |
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clk_ctrl = readl(&slcr_base->gem1_rclk_ctrl); |
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srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; |
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if (srcsel) |
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return emio_clk; |
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else |
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return mio_clk; |
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} |
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#endif |
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static ulong zynq_clk_get_cpu_rate(struct zynq_clk_priv *priv, enum zynq_clk id) |
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{ |
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u32 clk_621, clk_ctrl, div; |
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enum zynq_clk pll; |
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clk_ctrl = readl(&slcr_base->arm_clk_ctrl); |
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div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; |
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switch (id) { |
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case cpu_1x_clk: |
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div *= 2; |
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/* fall through */ |
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case cpu_2x_clk: |
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clk_621 = readl(&slcr_base->clk_621_true) & 1; |
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div *= 2 + clk_621; |
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break; |
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case cpu_3or2x_clk: |
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div *= 2; |
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/* fall through */ |
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case cpu_6or4x_clk: |
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break; |
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default: |
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return 0; |
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} |
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pll = zynq_clk_get_cpu_pll(clk_ctrl); |
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return DIV_ROUND_CLOSEST(zynq_clk_get_pll_rate(priv, pll), div); |
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} |
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#ifndef CONFIG_SPL_BUILD |
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static ulong zynq_clk_get_ddr2x_rate(struct zynq_clk_priv *priv) |
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{ |
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u32 clk_ctrl, div; |
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clk_ctrl = readl(&slcr_base->ddr_clk_ctrl); |
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div = (clk_ctrl & CLK_CTRL_DIV2X_MASK) >> CLK_CTRL_DIV2X_SHIFT; |
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return DIV_ROUND_CLOSEST(zynq_clk_get_pll_rate(priv, ddrpll_clk), div); |
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} |
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#endif |
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static ulong zynq_clk_get_ddr3x_rate(struct zynq_clk_priv *priv) |
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{ |
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u32 clk_ctrl, div; |
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clk_ctrl = readl(&slcr_base->ddr_clk_ctrl); |
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div = (clk_ctrl & CLK_CTRL_DIV3X_MASK) >> CLK_CTRL_DIV3X_SHIFT; |
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return DIV_ROUND_CLOSEST(zynq_clk_get_pll_rate(priv, ddrpll_clk), div); |
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} |
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#ifndef CONFIG_SPL_BUILD |
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static ulong zynq_clk_get_dci_rate(struct zynq_clk_priv *priv) |
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{ |
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u32 clk_ctrl, div0, div1; |
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clk_ctrl = readl(&slcr_base->dci_clk_ctrl); |
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div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; |
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div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT; |
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return DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST( |
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zynq_clk_get_pll_rate(priv, ddrpll_clk), div0), div1); |
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} |
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#endif |
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static ulong zynq_clk_get_peripheral_rate(struct zynq_clk_priv *priv, |
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enum zynq_clk id, bool two_divs) |
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{ |
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enum zynq_clk pll; |
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u32 clk_ctrl, div0; |
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u32 div1 = 1; |
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clk_ctrl = readl(zynq_clk_get_register(id)); |
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div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; |
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if (!div0) |
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div0 = 1; |
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#ifndef CONFIG_SPL_BUILD |
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if (two_divs) { |
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div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT; |
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if (!div1) |
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div1 = 1; |
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} |
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#endif |
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pll = zynq_clk_get_peripheral_pll(clk_ctrl); |
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return |
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DIV_ROUND_CLOSEST( |
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DIV_ROUND_CLOSEST( |
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zynq_clk_get_pll_rate(priv, pll), div0), |
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div1); |
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} |
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#ifndef CONFIG_SPL_BUILD |
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static ulong zynq_clk_get_gem_rate(struct zynq_clk_priv *priv, enum zynq_clk id) |
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{ |
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struct clk *parent; |
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if (zynq_clk_get_gem_rclk(id) == mio_clk) |
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return zynq_clk_get_peripheral_rate(priv, id, true); |
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parent = &priv->gem_emio_clk[id - gem0_clk]; |
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if (parent->dev) |
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return clk_get_rate(parent); |
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debug("%s: gem%d emio rx clock source unknown\n", __func__, |
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id - gem0_clk); |
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return -ENOSYS; |
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} |
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static unsigned long zynq_clk_calc_peripheral_two_divs(ulong rate, |
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ulong pll_rate, |
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u32 *div0, u32 *div1) |
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{ |
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long new_err, best_err = (long)(~0UL >> 1); |
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ulong new_rate, best_rate = 0; |
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u32 d0, d1; |
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for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) { |
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for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) { |
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new_rate = DIV_ROUND_CLOSEST( |
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DIV_ROUND_CLOSEST(pll_rate, d0), d1); |
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new_err = abs(new_rate - rate); |
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if (new_err < best_err) { |
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*div0 = d0; |
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*div1 = d1; |
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best_err = new_err; |
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best_rate = new_rate; |
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} |
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} |
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} |
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return best_rate; |
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} |
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static ulong zynq_clk_set_peripheral_rate(struct zynq_clk_priv *priv, |
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enum zynq_clk id, ulong rate, |
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bool two_divs) |
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{ |
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enum zynq_clk pll; |
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u32 clk_ctrl, div0 = 0, div1 = 0; |
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ulong pll_rate, new_rate; |
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u32 *reg; |
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reg = zynq_clk_get_register(id); |
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clk_ctrl = readl(reg); |
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pll = zynq_clk_get_peripheral_pll(clk_ctrl); |
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pll_rate = zynq_clk_get_pll_rate(priv, pll); |
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clk_ctrl &= ~CLK_CTRL_DIV0_MASK; |
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if (two_divs) { |
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clk_ctrl &= ~CLK_CTRL_DIV1_MASK; |
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new_rate = zynq_clk_calc_peripheral_two_divs(rate, pll_rate, |
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&div0, &div1); |
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clk_ctrl |= div1 << CLK_CTRL_DIV1_SHIFT; |
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} else { |
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div0 = DIV_ROUND_CLOSEST(pll_rate, rate); |
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if (div0 > ZYNQ_CLK_MAXDIV) |
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div0 = ZYNQ_CLK_MAXDIV; |
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new_rate = DIV_ROUND_CLOSEST(rate, div0); |
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} |
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clk_ctrl |= div0 << CLK_CTRL_DIV0_SHIFT; |
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zynq_slcr_unlock(); |
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writel(clk_ctrl, reg); |
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zynq_slcr_lock(); |
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return new_rate; |
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} |
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static ulong zynq_clk_set_gem_rate(struct zynq_clk_priv *priv, enum zynq_clk id, |
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ulong rate) |
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{ |
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struct clk *parent; |
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if (zynq_clk_get_gem_rclk(id) == mio_clk) |
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return zynq_clk_set_peripheral_rate(priv, id, rate, true); |
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parent = &priv->gem_emio_clk[id - gem0_clk]; |
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if (parent->dev) |
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return clk_set_rate(parent, rate); |
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debug("%s: gem%d emio rx clock source unknown\n", __func__, |
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id - gem0_clk); |
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return -ENOSYS; |
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} |
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#endif |
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#ifndef CONFIG_SPL_BUILD |
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static ulong zynq_clk_get_rate(struct clk *clk) |
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{ |
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struct zynq_clk_priv *priv = dev_get_priv(clk->dev); |
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enum zynq_clk id = clk->id; |
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bool two_divs = false; |
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switch (id) { |
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case armpll_clk ... iopll_clk: |
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return zynq_clk_get_pll_rate(priv, id); |
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case cpu_6or4x_clk ... cpu_1x_clk: |
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return zynq_clk_get_cpu_rate(priv, id); |
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case ddr2x_clk: |
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return zynq_clk_get_ddr2x_rate(priv); |
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case ddr3x_clk: |
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return zynq_clk_get_ddr3x_rate(priv); |
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case dci_clk: |
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return zynq_clk_get_dci_rate(priv); |
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case gem0_clk ... gem1_clk: |
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return zynq_clk_get_gem_rate(priv, id); |
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case fclk0_clk ... can1_clk: |
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two_divs = true; |
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/* fall through */ |
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case dbg_trc_clk ... dbg_apb_clk: |
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case lqspi_clk ... pcap_clk: |
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case sdio0_clk ... spi1_clk: |
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return zynq_clk_get_peripheral_rate(priv, id, two_divs); |
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case dma_clk: |
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return zynq_clk_get_cpu_rate(priv, cpu_2x_clk); |
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case usb0_aper_clk ... swdt_clk: |
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return zynq_clk_get_cpu_rate(priv, cpu_1x_clk); |
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default: |
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return -ENXIO; |
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} |
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} |
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static ulong zynq_clk_set_rate(struct clk *clk, ulong rate) |
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{ |
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struct zynq_clk_priv *priv = dev_get_priv(clk->dev); |
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enum zynq_clk id = clk->id; |
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bool two_divs = false; |
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switch (id) { |
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case gem0_clk ... gem1_clk: |
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return zynq_clk_set_gem_rate(priv, id, rate); |
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case fclk0_clk ... can1_clk: |
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two_divs = true; |
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/* fall through */ |
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case lqspi_clk ... pcap_clk: |
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case sdio0_clk ... spi1_clk: |
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case dbg_trc_clk ... dbg_apb_clk: |
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return zynq_clk_set_peripheral_rate(priv, id, rate, two_divs); |
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default: |
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return -ENXIO; |
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} |
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} |
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#else |
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static ulong zynq_clk_get_rate(struct clk *clk) |
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{ |
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struct zynq_clk_priv *priv = dev_get_priv(clk->dev); |
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enum zynq_clk id = clk->id; |
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switch (id) { |
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case cpu_6or4x_clk ... cpu_1x_clk: |
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return zynq_clk_get_cpu_rate(priv, id); |
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case ddr3x_clk: |
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return zynq_clk_get_ddr3x_rate(priv); |
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case lqspi_clk ... pcap_clk: |
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case sdio0_clk ... spi1_clk: |
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return zynq_clk_get_peripheral_rate(priv, id, 0); |
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default: |
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return -ENXIO; |
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} |
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} |
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#endif |
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static struct clk_ops zynq_clk_ops = { |
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.get_rate = zynq_clk_get_rate, |
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#ifndef CONFIG_SPL_BUILD |
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.set_rate = zynq_clk_set_rate, |
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#endif |
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}; |
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static int zynq_clk_probe(struct udevice *dev) |
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{ |
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struct zynq_clk_priv *priv = dev_get_priv(dev); |
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#ifndef CONFIG_SPL_BUILD |
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unsigned int i; |
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char name[16]; |
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int ret; |
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for (i = 0; i < 2; i++) { |
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sprintf(name, "gem%d_emio_clk", i); |
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ret = clk_get_by_name(dev, name, &priv->gem_emio_clk[i]); |
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if (ret < 0 && ret != -ENODATA) { |
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dev_err(dev, "failed to get %s clock\n", name); |
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return ret; |
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} |
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} |
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#endif |
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priv->ps_clk_freq = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), |
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"ps-clk-frequency", 33333333UL); |
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return 0; |
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} |
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static const struct udevice_id zynq_clk_ids[] = { |
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{ .compatible = "xlnx,ps7-clkc"}, |
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{} |
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}; |
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U_BOOT_DRIVER(zynq_clk) = { |
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.name = "zynq_clk", |
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.id = UCLASS_CLK, |
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.of_match = zynq_clk_ids, |
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.flags = DM_FLAG_PRE_RELOC, |
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.ops = &zynq_clk_ops, |
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.priv_auto_alloc_size = sizeof(struct zynq_clk_priv), |
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.probe = zynq_clk_probe, |
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};
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