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89 lines
2.4 KiB
89 lines
2.4 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* omap_control_phy.h - Header file for the PHY part of control module. |
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* |
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com |
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* Author: Kishon Vijay Abraham I <[email protected]> |
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*/ |
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#ifndef __OMAP_CONTROL_PHY_H__ |
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#define __OMAP_CONTROL_PHY_H__ |
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enum omap_control_phy_type { |
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OMAP_CTRL_TYPE_OTGHS = 1, /* Mailbox OTGHS_CONTROL */ |
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OMAP_CTRL_TYPE_USB2, /* USB2_PHY, power down in CONTROL_DEV_CONF */ |
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OMAP_CTRL_TYPE_PIPE3, /* PIPE3 PHY, DPLL & seperate Rx/Tx power */ |
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OMAP_CTRL_TYPE_PCIE, /* RX TX control of ACSPCIE */ |
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OMAP_CTRL_TYPE_DRA7USB2, /* USB2 PHY, power and power_aux e.g. DRA7 */ |
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OMAP_CTRL_TYPE_AM437USB2, /* USB2 PHY, power e.g. AM437x */ |
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}; |
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struct omap_control_phy { |
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struct device *dev; |
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u32 __iomem *otghs_control; |
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u32 __iomem *power; |
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u32 __iomem *power_aux; |
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u32 __iomem *pcie_pcs; |
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struct clk *sys_clk; |
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enum omap_control_phy_type type; |
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}; |
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enum omap_control_usb_mode { |
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USB_MODE_UNDEFINED = 0, |
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USB_MODE_HOST, |
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USB_MODE_DEVICE, |
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USB_MODE_DISCONNECT, |
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}; |
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#define OMAP_CTRL_DEV_PHY_PD BIT(0) |
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#define OMAP_CTRL_DEV_AVALID BIT(0) |
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#define OMAP_CTRL_DEV_BVALID BIT(1) |
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#define OMAP_CTRL_DEV_VBUSVALID BIT(2) |
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#define OMAP_CTRL_DEV_SESSEND BIT(3) |
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#define OMAP_CTRL_DEV_IDDIG BIT(4) |
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#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000 |
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#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE |
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#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000 |
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#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16 |
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#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3 |
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#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0 |
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#define OMAP_CTRL_PCIE_PCS_MASK 0xff |
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#define OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT 16 |
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#define OMAP_CTRL_USB2_PHY_PD BIT(28) |
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#define AM437X_CTRL_USB2_PHY_PD BIT(0) |
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#define AM437X_CTRL_USB2_OTG_PD BIT(1) |
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#define AM437X_CTRL_USB2_OTGVDET_EN BIT(19) |
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#define AM437X_CTRL_USB2_OTGSESSEND_EN BIT(20) |
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#if IS_ENABLED(CONFIG_OMAP_CONTROL_PHY) |
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void omap_control_phy_power(struct device *dev, int on); |
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void omap_control_usb_set_mode(struct device *dev, |
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enum omap_control_usb_mode mode); |
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void omap_control_pcie_pcs(struct device *dev, u8 delay); |
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#else |
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static inline void omap_control_phy_power(struct device *dev, int on) |
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{ |
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} |
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static inline void omap_control_usb_set_mode(struct device *dev, |
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enum omap_control_usb_mode mode) |
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{ |
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} |
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static inline void omap_control_pcie_pcs(struct device *dev, u8 delay) |
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{ |
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} |
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#endif |
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#endif /* __OMAP_CONTROL_PHY_H__ */
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