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35 lines
967 B
35 lines
967 B
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* ARTPEC-6 clock controller indexes |
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* |
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* Copyright 2016 Axis Communications AB. |
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*/ |
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#ifndef DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H |
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#define DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H |
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#define ARTPEC6_CLK_CPU 0 |
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#define ARTPEC6_CLK_CPU_PERIPH 1 |
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#define ARTPEC6_CLK_NAND_CLKA 2 |
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#define ARTPEC6_CLK_NAND_CLKB 3 |
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#define ARTPEC6_CLK_ETH_ACLK 4 |
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#define ARTPEC6_CLK_DMA_ACLK 5 |
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#define ARTPEC6_CLK_PTP_REF 6 |
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#define ARTPEC6_CLK_SD_PCLK 7 |
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#define ARTPEC6_CLK_SD_IMCLK 8 |
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#define ARTPEC6_CLK_I2S_HST 9 |
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#define ARTPEC6_CLK_I2S0_CLK 10 |
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#define ARTPEC6_CLK_I2S1_CLK 11 |
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#define ARTPEC6_CLK_UART_PCLK 12 |
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#define ARTPEC6_CLK_UART_REFCLK 13 |
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#define ARTPEC6_CLK_I2C 14 |
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#define ARTPEC6_CLK_SPI_PCLK 15 |
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#define ARTPEC6_CLK_SPI_SSPCLK 16 |
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#define ARTPEC6_CLK_SYS_TIMER 17 |
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#define ARTPEC6_CLK_FRACDIV_IN 18 |
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#define ARTPEC6_CLK_DBG_PCLK 19 |
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/* This must be the highest clock index plus one. */ |
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#define ARTPEC6_CLK_NUMCLOCKS 20 |
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#endif
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