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73 lines
1.7 KiB
73 lines
1.7 KiB
/* SPDX-License-Identifier: GPL-2.0+ */ |
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/* |
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* Copyright (C) 2021 Sean Anderson <[email protected]> |
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*/ |
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#ifndef XILINX_TIMER_H |
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#define XILINX_TIMER_H |
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#include <linux/compiler.h> |
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#define TCSR0 0x00 |
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#define TLR0 0x04 |
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#define TCR0 0x08 |
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#define TCSR1 0x10 |
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#define TLR1 0x14 |
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#define TCR1 0x18 |
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#define TCSR_MDT BIT(0) |
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#define TCSR_UDT BIT(1) |
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#define TCSR_GENT BIT(2) |
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#define TCSR_CAPT BIT(3) |
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#define TCSR_ARHT BIT(4) |
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#define TCSR_LOAD BIT(5) |
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#define TCSR_ENIT BIT(6) |
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#define TCSR_ENT BIT(7) |
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#define TCSR_TINT BIT(8) |
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#define TCSR_PWMA BIT(9) |
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#define TCSR_ENALL BIT(10) |
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#define TCSR_CASC BIT(11) |
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struct clk; |
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struct device_node; |
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struct regmap; |
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/** |
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* struct xilinx_timer_priv - Private data for Xilinx AXI timer drivers |
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* @map: Regmap of the device, possibly with an offset |
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* @clk: Parent clock |
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* @max: Maximum value of the counters |
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*/ |
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struct xilinx_timer_priv { |
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struct regmap *map; |
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struct clk *clk; |
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u32 max; |
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}; |
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/** |
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* xilinx_timer_tlr_cycles() - Calculate the TLR for a period specified |
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* in clock cycles |
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* @priv: The timer's private data |
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* @tcsr: The value of the TCSR register for this counter |
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* @cycles: The number of cycles in this period |
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* |
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* Callers of this function MUST ensure that @cycles is representable as |
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* a TLR. |
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* |
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* Return: The calculated value for TLR |
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*/ |
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u32 xilinx_timer_tlr_cycles(struct xilinx_timer_priv *priv, u32 tcsr, |
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u64 cycles); |
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/** |
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* xilinx_timer_get_period() - Get the current period of a counter |
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* @priv: The timer's private data |
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* @tlr: The value of TLR for this counter |
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* @tcsr: The value of TCSR for this counter |
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* |
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* Return: The period, in ns |
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*/ |
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unsigned int xilinx_timer_get_period(struct xilinx_timer_priv *priv, |
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u32 tlr, u32 tcsr); |
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#endif /* XILINX_TIMER_H */
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