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294 lines
7.7 KiB
294 lines
7.7 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Processor capabilities determination functions. |
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* |
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited |
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*/ |
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#include <linux/init.h> |
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#include <linux/kernel.h> |
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#include <linux/ptrace.h> |
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#include <linux/smp.h> |
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#include <linux/stddef.h> |
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#include <linux/export.h> |
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#include <linux/printk.h> |
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#include <linux/uaccess.h> |
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#include <asm/cpu-features.h> |
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#include <asm/elf.h> |
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#include <asm/fpu.h> |
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#include <asm/loongarch.h> |
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#include <asm/pgtable-bits.h> |
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#include <asm/setup.h> |
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/* Hardware capabilities */ |
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unsigned int elf_hwcap __read_mostly; |
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EXPORT_SYMBOL_GPL(elf_hwcap); |
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/* |
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* Determine the FCSR mask for FPU hardware. |
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*/ |
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static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_loongarch *c) |
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{ |
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unsigned long sr, mask, fcsr, fcsr0, fcsr1; |
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fcsr = c->fpu_csr0; |
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mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM; |
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sr = read_csr_euen(); |
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enable_fpu(); |
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fcsr0 = fcsr & mask; |
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write_fcsr(LOONGARCH_FCSR0, fcsr0); |
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fcsr0 = read_fcsr(LOONGARCH_FCSR0); |
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fcsr1 = fcsr | ~mask; |
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write_fcsr(LOONGARCH_FCSR0, fcsr1); |
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fcsr1 = read_fcsr(LOONGARCH_FCSR0); |
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write_fcsr(LOONGARCH_FCSR0, fcsr); |
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write_csr_euen(sr); |
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c->fpu_mask = ~(fcsr0 ^ fcsr1) & ~mask; |
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} |
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static inline void set_elf_platform(int cpu, const char *plat) |
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{ |
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if (cpu == 0) |
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__elf_platform = plat; |
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} |
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/* MAP BASE */ |
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unsigned long vm_map_base; |
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EXPORT_SYMBOL_GPL(vm_map_base); |
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static void cpu_probe_addrbits(struct cpuinfo_loongarch *c) |
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{ |
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#ifdef __NEED_ADDRBITS_PROBE |
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c->pabits = (read_cpucfg(LOONGARCH_CPUCFG1) & CPUCFG1_PABITS) >> 4; |
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c->vabits = (read_cpucfg(LOONGARCH_CPUCFG1) & CPUCFG1_VABITS) >> 12; |
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vm_map_base = 0UL - (1UL << c->vabits); |
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#endif |
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} |
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static void set_isa(struct cpuinfo_loongarch *c, unsigned int isa) |
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{ |
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switch (isa) { |
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case LOONGARCH_CPU_ISA_LA64: |
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c->isa_level |= LOONGARCH_CPU_ISA_LA64; |
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fallthrough; |
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case LOONGARCH_CPU_ISA_LA32S: |
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c->isa_level |= LOONGARCH_CPU_ISA_LA32S; |
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fallthrough; |
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case LOONGARCH_CPU_ISA_LA32R: |
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c->isa_level |= LOONGARCH_CPU_ISA_LA32R; |
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break; |
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} |
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} |
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static void cpu_probe_common(struct cpuinfo_loongarch *c) |
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{ |
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unsigned int config; |
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unsigned long asid_mask; |
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c->options = LOONGARCH_CPU_CPUCFG | LOONGARCH_CPU_CSR | |
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LOONGARCH_CPU_TLB | LOONGARCH_CPU_VINT | LOONGARCH_CPU_WATCH; |
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elf_hwcap |= HWCAP_LOONGARCH_CRC32; |
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config = read_cpucfg(LOONGARCH_CPUCFG1); |
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if (config & CPUCFG1_UAL) { |
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c->options |= LOONGARCH_CPU_UAL; |
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elf_hwcap |= HWCAP_LOONGARCH_UAL; |
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} |
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config = read_cpucfg(LOONGARCH_CPUCFG2); |
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if (config & CPUCFG2_LAM) { |
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c->options |= LOONGARCH_CPU_LAM; |
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elf_hwcap |= HWCAP_LOONGARCH_LAM; |
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} |
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if (config & CPUCFG2_FP) { |
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c->options |= LOONGARCH_CPU_FPU; |
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elf_hwcap |= HWCAP_LOONGARCH_FPU; |
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} |
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if (config & CPUCFG2_COMPLEX) { |
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c->options |= LOONGARCH_CPU_COMPLEX; |
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elf_hwcap |= HWCAP_LOONGARCH_COMPLEX; |
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} |
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if (config & CPUCFG2_CRYPTO) { |
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c->options |= LOONGARCH_CPU_CRYPTO; |
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elf_hwcap |= HWCAP_LOONGARCH_CRYPTO; |
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} |
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if (config & CPUCFG2_LVZP) { |
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c->options |= LOONGARCH_CPU_LVZ; |
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elf_hwcap |= HWCAP_LOONGARCH_LVZ; |
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} |
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config = read_cpucfg(LOONGARCH_CPUCFG6); |
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if (config & CPUCFG6_PMP) |
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c->options |= LOONGARCH_CPU_PMP; |
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config = iocsr_read32(LOONGARCH_IOCSR_FEATURES); |
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if (config & IOCSRF_CSRIPI) |
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c->options |= LOONGARCH_CPU_CSRIPI; |
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if (config & IOCSRF_EXTIOI) |
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c->options |= LOONGARCH_CPU_EXTIOI; |
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if (config & IOCSRF_FREQSCALE) |
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c->options |= LOONGARCH_CPU_SCALEFREQ; |
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if (config & IOCSRF_FLATMODE) |
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c->options |= LOONGARCH_CPU_FLATMODE; |
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if (config & IOCSRF_EIODECODE) |
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c->options |= LOONGARCH_CPU_EIODECODE; |
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if (config & IOCSRF_VM) |
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c->options |= LOONGARCH_CPU_HYPERVISOR; |
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config = csr_read32(LOONGARCH_CSR_ASID); |
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config = (config & CSR_ASID_BIT) >> CSR_ASID_BIT_SHIFT; |
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asid_mask = GENMASK(config - 1, 0); |
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set_cpu_asid_mask(c, asid_mask); |
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config = read_csr_prcfg1(); |
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c->ksave_mask = GENMASK((config & CSR_CONF1_KSNUM) - 1, 0); |
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c->ksave_mask &= ~(EXC_KSAVE_MASK | PERCPU_KSAVE_MASK | KVM_KSAVE_MASK); |
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config = read_csr_prcfg3(); |
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switch (config & CSR_CONF3_TLBTYPE) { |
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case 0: |
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c->tlbsizemtlb = 0; |
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c->tlbsizestlbsets = 0; |
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c->tlbsizestlbways = 0; |
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c->tlbsize = 0; |
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break; |
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case 1: |
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c->tlbsizemtlb = ((config & CSR_CONF3_MTLBSIZE) >> CSR_CONF3_MTLBSIZE_SHIFT) + 1; |
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c->tlbsizestlbsets = 0; |
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c->tlbsizestlbways = 0; |
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c->tlbsize = c->tlbsizemtlb + c->tlbsizestlbsets * c->tlbsizestlbways; |
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break; |
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case 2: |
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c->tlbsizemtlb = ((config & CSR_CONF3_MTLBSIZE) >> CSR_CONF3_MTLBSIZE_SHIFT) + 1; |
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c->tlbsizestlbsets = 1 << ((config & CSR_CONF3_STLBIDX) >> CSR_CONF3_STLBIDX_SHIFT); |
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c->tlbsizestlbways = ((config & CSR_CONF3_STLBWAYS) >> CSR_CONF3_STLBWAYS_SHIFT) + 1; |
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c->tlbsize = c->tlbsizemtlb + c->tlbsizestlbsets * c->tlbsizestlbways; |
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break; |
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default: |
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pr_warn("Warning: unknown TLB type\n"); |
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} |
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} |
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#define MAX_NAME_LEN 32 |
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#define VENDOR_OFFSET 0 |
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#define CPUNAME_OFFSET 9 |
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static char cpu_full_name[MAX_NAME_LEN] = " - "; |
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static inline void cpu_probe_loongson(struct cpuinfo_loongarch *c, unsigned int cpu) |
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{ |
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uint64_t *vendor = (void *)(&cpu_full_name[VENDOR_OFFSET]); |
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uint64_t *cpuname = (void *)(&cpu_full_name[CPUNAME_OFFSET]); |
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if (!__cpu_full_name[cpu]) |
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__cpu_full_name[cpu] = cpu_full_name; |
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*vendor = iocsr_read64(LOONGARCH_IOCSR_VENDOR); |
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*cpuname = iocsr_read64(LOONGARCH_IOCSR_CPUNAME); |
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switch (c->processor_id & PRID_SERIES_MASK) { |
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case PRID_SERIES_LA132: |
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c->cputype = CPU_LOONGSON32; |
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set_isa(c, LOONGARCH_CPU_ISA_LA32S); |
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__cpu_family[cpu] = "Loongson-32bit"; |
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pr_info("32-bit Loongson Processor probed (LA132 Core)\n"); |
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break; |
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case PRID_SERIES_LA264: |
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c->cputype = CPU_LOONGSON64; |
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set_isa(c, LOONGARCH_CPU_ISA_LA64); |
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__cpu_family[cpu] = "Loongson-64bit"; |
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pr_info("64-bit Loongson Processor probed (LA264 Core)\n"); |
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break; |
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case PRID_SERIES_LA364: |
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c->cputype = CPU_LOONGSON64; |
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set_isa(c, LOONGARCH_CPU_ISA_LA64); |
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__cpu_family[cpu] = "Loongson-64bit"; |
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pr_info("64-bit Loongson Processor probed (LA364 Core)\n"); |
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break; |
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case PRID_SERIES_LA464: |
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c->cputype = CPU_LOONGSON64; |
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set_isa(c, LOONGARCH_CPU_ISA_LA64); |
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__cpu_family[cpu] = "Loongson-64bit"; |
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pr_info("64-bit Loongson Processor probed (LA464 Core)\n"); |
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break; |
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case PRID_SERIES_LA664: |
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c->cputype = CPU_LOONGSON64; |
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set_isa(c, LOONGARCH_CPU_ISA_LA64); |
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__cpu_family[cpu] = "Loongson-64bit"; |
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pr_info("64-bit Loongson Processor probed (LA664 Core)\n"); |
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break; |
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default: /* Default to 64 bit */ |
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c->cputype = CPU_LOONGSON64; |
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set_isa(c, LOONGARCH_CPU_ISA_LA64); |
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__cpu_family[cpu] = "Loongson-64bit"; |
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pr_info("64-bit Loongson Processor probed (Unknown Core)\n"); |
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} |
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} |
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#ifdef CONFIG_64BIT |
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/* For use by uaccess.h */ |
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u64 __ua_limit; |
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EXPORT_SYMBOL(__ua_limit); |
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#endif |
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const char *__cpu_family[NR_CPUS]; |
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const char *__cpu_full_name[NR_CPUS]; |
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const char *__elf_platform; |
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static void cpu_report(void) |
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{ |
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struct cpuinfo_loongarch *c = ¤t_cpu_data; |
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pr_info("CPU%d revision is: %08x (%s)\n", |
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smp_processor_id(), c->processor_id, cpu_family_string()); |
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if (c->options & LOONGARCH_CPU_FPU) |
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pr_info("FPU%d revision is: %08x\n", smp_processor_id(), c->fpu_vers); |
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} |
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void cpu_probe(void) |
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{ |
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unsigned int cpu = smp_processor_id(); |
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struct cpuinfo_loongarch *c = ¤t_cpu_data; |
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/* |
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* Set a default ELF platform, cpu probe may later |
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* overwrite it with a more precise value |
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*/ |
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set_elf_platform(cpu, "loongarch"); |
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c->cputype = CPU_UNKNOWN; |
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c->processor_id = read_cpucfg(LOONGARCH_CPUCFG0); |
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c->fpu_vers = (read_cpucfg(LOONGARCH_CPUCFG2) & CPUCFG2_FPVERS) >> 3; |
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c->fpu_csr0 = FPU_CSR_RN; |
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c->fpu_mask = FPU_CSR_RSVD; |
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cpu_probe_common(c); |
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per_cpu_trap_init(cpu); |
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switch (c->processor_id & PRID_COMP_MASK) { |
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case PRID_COMP_LOONGSON: |
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cpu_probe_loongson(c, cpu); |
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break; |
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} |
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BUG_ON(!__cpu_family[cpu]); |
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BUG_ON(c->cputype == CPU_UNKNOWN); |
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cpu_probe_addrbits(c); |
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#ifdef CONFIG_64BIT |
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if (cpu == 0) |
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__ua_limit = ~((1ull << cpu_vabits) - 1); |
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#endif |
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cpu_report(); |
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}
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