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1670 lines
42 KiB
1670 lines
42 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* arch/arm/mach-at91/pm.c |
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* AT91 Power Management |
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* |
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* Copyright (C) 2005 David Brownell |
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*/ |
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|
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#include <linux/genalloc.h> |
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#include <linux/io.h> |
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#include <linux/of_address.h> |
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#include <linux/of.h> |
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#include <linux/of_fdt.h> |
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#include <linux/of_platform.h> |
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#include <linux/parser.h> |
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#include <linux/suspend.h> |
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|
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#include <linux/clk.h> |
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#include <linux/clk/at91_pmc.h> |
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#include <linux/platform_data/atmel.h> |
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|
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#include <asm/cacheflush.h> |
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#include <asm/fncpy.h> |
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#include <asm/system_misc.h> |
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#include <asm/suspend.h> |
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|
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#include "generic.h" |
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#include "pm.h" |
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#include "sam_secure.h" |
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#define BACKUP_DDR_PHY_CALIBRATION (9) |
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/** |
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* struct at91_pm_bu - AT91 power management backup unit data structure |
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* @suspended: true if suspended to backup mode |
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* @reserved: reserved |
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* @canary: canary data for memory checking after exit from backup mode |
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* @resume: resume API |
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* @ddr_phy_calibration: DDR PHY calibration data: ZQ0CR0, first 8 words |
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* of the memory |
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*/ |
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struct at91_pm_bu { |
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int suspended; |
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unsigned long reserved; |
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phys_addr_t canary; |
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phys_addr_t resume; |
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unsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION]; |
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}; |
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|
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/** |
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* struct at91_pm_sfrbu_regs - registers mapping for SFRBU |
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* @pswbu: power switch BU control registers |
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*/ |
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struct at91_pm_sfrbu_regs { |
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struct { |
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u32 key; |
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u32 ctrl; |
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u32 state; |
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u32 softsw; |
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} pswbu; |
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}; |
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|
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/** |
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* enum at91_pm_eth_clk - Ethernet clock indexes |
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* @AT91_PM_ETH_PCLK: pclk index |
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* @AT91_PM_ETH_HCLK: hclk index |
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* @AT91_PM_ETH_MAX_CLK: max index |
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*/ |
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enum at91_pm_eth_clk { |
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AT91_PM_ETH_PCLK, |
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AT91_PM_ETH_HCLK, |
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AT91_PM_ETH_MAX_CLK, |
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}; |
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|
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/** |
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* enum at91_pm_eth - Ethernet controller indexes |
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* @AT91_PM_G_ETH: gigabit Ethernet controller index |
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* @AT91_PM_E_ETH: megabit Ethernet controller index |
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* @AT91_PM_MAX_ETH: max index |
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*/ |
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enum at91_pm_eth { |
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AT91_PM_G_ETH, |
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AT91_PM_E_ETH, |
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AT91_PM_MAX_ETH, |
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}; |
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/** |
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* struct at91_pm_quirk_eth - AT91 PM Ethernet quirks |
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* @dev: Ethernet device |
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* @np: Ethernet device node |
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* @clks: Ethernet clocks |
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* @modes: power management mode that this quirk applies to |
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* @dns_modes: do not suspend modes: stop suspending if Ethernet is configured |
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* as wakeup source but buggy and no other wakeup source is |
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* available |
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*/ |
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struct at91_pm_quirk_eth { |
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struct device *dev; |
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struct device_node *np; |
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struct clk_bulk_data clks[AT91_PM_ETH_MAX_CLK]; |
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u32 modes; |
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u32 dns_modes; |
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}; |
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|
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/** |
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* struct at91_pm_quirks - AT91 PM quirks |
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* @eth: Ethernet quirks |
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*/ |
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struct at91_pm_quirks { |
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struct at91_pm_quirk_eth eth[AT91_PM_MAX_ETH]; |
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}; |
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|
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/** |
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* struct at91_soc_pm - AT91 SoC power management data structure |
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* @config_shdwc_ws: wakeup sources configuration function for SHDWC |
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* @config_pmc_ws: wakeup srouces configuration function for PMC |
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* @ws_ids: wakup sources of_device_id array |
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* @bu: backup unit mapped data (for backup mode) |
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* @quirks: PM quirks |
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* @data: PM data to be used on last phase of suspend |
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* @sfrbu_regs: SFRBU registers mapping |
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* @memcs: memory chip select |
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*/ |
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struct at91_soc_pm { |
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int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity); |
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int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity); |
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const struct of_device_id *ws_ids; |
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struct at91_pm_bu *bu; |
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struct at91_pm_quirks quirks; |
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struct at91_pm_data data; |
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struct at91_pm_sfrbu_regs sfrbu_regs; |
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void *memcs; |
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}; |
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|
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/** |
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* enum at91_pm_iomaps - IOs that needs to be mapped for different PM modes |
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* @AT91_PM_IOMAP_SHDWC: SHDWC controller |
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* @AT91_PM_IOMAP_SFRBU: SFRBU controller |
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* @AT91_PM_IOMAP_ETHC: Ethernet controller |
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*/ |
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enum at91_pm_iomaps { |
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AT91_PM_IOMAP_SHDWC, |
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AT91_PM_IOMAP_SFRBU, |
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AT91_PM_IOMAP_ETHC, |
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}; |
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#define AT91_PM_IOMAP(name) BIT(AT91_PM_IOMAP_##name) |
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|
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static struct at91_soc_pm soc_pm = { |
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.data = { |
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.standby_mode = AT91_PM_STANDBY, |
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.suspend_mode = AT91_PM_ULP0, |
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}, |
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}; |
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|
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static const match_table_t pm_modes __initconst = { |
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{ AT91_PM_STANDBY, "standby" }, |
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{ AT91_PM_ULP0, "ulp0" }, |
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{ AT91_PM_ULP0_FAST, "ulp0-fast" }, |
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{ AT91_PM_ULP1, "ulp1" }, |
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{ AT91_PM_BACKUP, "backup" }, |
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{ -1, NULL }, |
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}; |
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#define at91_ramc_read(id, field) \ |
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__raw_readl(soc_pm.data.ramc[id] + field) |
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#define at91_ramc_write(id, field, value) \ |
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__raw_writel(value, soc_pm.data.ramc[id] + field) |
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|
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static int at91_pm_valid_state(suspend_state_t state) |
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{ |
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switch (state) { |
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case PM_SUSPEND_ON: |
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case PM_SUSPEND_STANDBY: |
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case PM_SUSPEND_MEM: |
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return 1; |
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default: |
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return 0; |
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} |
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} |
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static int canary = 0xA5A5A5A5; |
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struct wakeup_source_info { |
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unsigned int pmc_fsmr_bit; |
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unsigned int shdwc_mr_bit; |
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bool set_polarity; |
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}; |
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static const struct wakeup_source_info ws_info[] = { |
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{ .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true }, |
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{ .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) }, |
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{ .pmc_fsmr_bit = AT91_PMC_USBAL }, |
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{ .pmc_fsmr_bit = AT91_PMC_SDMMC_CD }, |
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{ .pmc_fsmr_bit = AT91_PMC_RTTAL }, |
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{ .pmc_fsmr_bit = AT91_PMC_RXLP_MCE }, |
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}; |
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static const struct of_device_id sama5d2_ws_ids[] = { |
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{ .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] }, |
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{ .compatible = "atmel,sama5d2-rtc", .data = &ws_info[1] }, |
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{ .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] }, |
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{ .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] }, |
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{ .compatible = "usb-ohci", .data = &ws_info[2] }, |
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{ .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, |
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{ .compatible = "usb-ehci", .data = &ws_info[2] }, |
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{ .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] }, |
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{ /* sentinel */ } |
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}; |
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static const struct of_device_id sam9x60_ws_ids[] = { |
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{ .compatible = "microchip,sam9x60-rtc", .data = &ws_info[1] }, |
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{ .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] }, |
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{ .compatible = "usb-ohci", .data = &ws_info[2] }, |
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{ .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, |
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{ .compatible = "usb-ehci", .data = &ws_info[2] }, |
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{ .compatible = "microchip,sam9x60-rtt", .data = &ws_info[4] }, |
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{ .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] }, |
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{ /* sentinel */ } |
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}; |
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static const struct of_device_id sama7g5_ws_ids[] = { |
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{ .compatible = "microchip,sama7g5-rtc", .data = &ws_info[1] }, |
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{ .compatible = "microchip,sama7g5-ohci", .data = &ws_info[2] }, |
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{ .compatible = "usb-ohci", .data = &ws_info[2] }, |
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{ .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, |
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{ .compatible = "usb-ehci", .data = &ws_info[2] }, |
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{ .compatible = "microchip,sama7g5-sdhci", .data = &ws_info[3] }, |
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{ .compatible = "microchip,sama7g5-rtt", .data = &ws_info[4] }, |
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{ /* sentinel */ } |
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}; |
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static int at91_pm_config_ws(unsigned int pm_mode, bool set) |
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{ |
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const struct wakeup_source_info *wsi; |
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const struct of_device_id *match; |
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struct platform_device *pdev; |
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struct device_node *np; |
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unsigned int mode = 0, polarity = 0, val = 0; |
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if (pm_mode != AT91_PM_ULP1) |
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return 0; |
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if (!soc_pm.data.pmc || !soc_pm.data.shdwc || !soc_pm.ws_ids) |
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return -EPERM; |
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if (!set) { |
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writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR); |
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return 0; |
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} |
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if (soc_pm.config_shdwc_ws) |
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soc_pm.config_shdwc_ws(soc_pm.data.shdwc, &mode, &polarity); |
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/* SHDWC.MR */ |
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val = readl(soc_pm.data.shdwc + 0x04); |
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/* Loop through defined wakeup sources. */ |
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for_each_matching_node_and_match(np, soc_pm.ws_ids, &match) { |
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pdev = of_find_device_by_node(np); |
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if (!pdev) |
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continue; |
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if (device_may_wakeup(&pdev->dev)) { |
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wsi = match->data; |
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/* Check if enabled on SHDWC. */ |
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if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit)) |
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goto put_device; |
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mode |= wsi->pmc_fsmr_bit; |
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if (wsi->set_polarity) |
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polarity |= wsi->pmc_fsmr_bit; |
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} |
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put_device: |
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put_device(&pdev->dev); |
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} |
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if (mode) { |
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if (soc_pm.config_pmc_ws) |
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soc_pm.config_pmc_ws(soc_pm.data.pmc, mode, polarity); |
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} else { |
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pr_err("AT91: PM: no ULP1 wakeup sources found!"); |
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} |
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return mode ? 0 : -EPERM; |
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} |
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static int at91_sama5d2_config_shdwc_ws(void __iomem *shdwc, u32 *mode, |
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u32 *polarity) |
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{ |
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u32 val; |
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/* SHDWC.WUIR */ |
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val = readl(shdwc + 0x0c); |
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*mode |= (val & 0x3ff); |
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*polarity |= ((val >> 16) & 0x3ff); |
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return 0; |
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} |
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static int at91_sama5d2_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity) |
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{ |
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writel(mode, pmc + AT91_PMC_FSMR); |
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writel(polarity, pmc + AT91_PMC_FSPR); |
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return 0; |
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} |
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static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity) |
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{ |
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writel(mode, pmc + AT91_PMC_FSMR); |
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return 0; |
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} |
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static bool at91_pm_eth_quirk_is_valid(struct at91_pm_quirk_eth *eth) |
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{ |
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struct platform_device *pdev; |
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|
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/* Interface NA in DT. */ |
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if (!eth->np) |
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return false; |
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|
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/* No quirks for this interface and current suspend mode. */ |
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if (!(eth->modes & BIT(soc_pm.data.mode))) |
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return false; |
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|
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if (!eth->dev) { |
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/* Driver not probed. */ |
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pdev = of_find_device_by_node(eth->np); |
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if (!pdev) |
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return false; |
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eth->dev = &pdev->dev; |
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} |
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/* No quirks if device isn't a wakeup source. */ |
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if (!device_may_wakeup(eth->dev)) { |
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put_device(eth->dev); |
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return false; |
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} |
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|
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/* put_device(eth->dev) is called at the end of suspend. */ |
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return true; |
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} |
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|
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static int at91_pm_config_quirks(bool suspend) |
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{ |
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struct at91_pm_quirk_eth *eth; |
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int i, j, ret, tmp; |
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/* |
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* Ethernet IPs who's device_node pointers are stored into |
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* soc_pm.quirks.eth[].np cannot handle WoL packets while in ULP0, ULP1 |
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* or both due to a hardware bug. If they receive WoL packets while in |
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* ULP0 or ULP1 IPs could stop working or the whole system could stop |
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* working. We cannot handle this scenario in the ethernet driver itself |
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* as the driver is common to multiple vendors and also we only know |
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* here, in this file, if we suspend to ULP0 or ULP1 mode. Thus handle |
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* these scenarios here, as quirks. |
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*/ |
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for (i = 0; i < AT91_PM_MAX_ETH; i++) { |
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eth = &soc_pm.quirks.eth[i]; |
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|
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if (!at91_pm_eth_quirk_is_valid(eth)) |
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continue; |
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|
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/* |
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* For modes in dns_modes mask the system blocks if quirk is not |
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* applied but if applied the interface doesn't act at WoL |
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* events. Thus take care to avoid suspending if this interface |
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* is the only configured wakeup source. |
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*/ |
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if (suspend && eth->dns_modes & BIT(soc_pm.data.mode)) { |
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int ws_count = 0; |
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#ifdef CONFIG_PM_SLEEP |
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struct wakeup_source *ws; |
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for_each_wakeup_source(ws) { |
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if (ws->dev == eth->dev) |
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continue; |
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ws_count++; |
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break; |
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} |
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#endif |
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/* |
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* Checking !ws is good for all platforms with issues |
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* even when both G_ETH and E_ETH are available as dns_modes |
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* is populated only on G_ETH interface. |
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*/ |
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if (!ws_count) { |
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pr_err("AT91: PM: Ethernet cannot resume from WoL!"); |
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ret = -EPERM; |
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put_device(eth->dev); |
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eth->dev = NULL; |
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/* No need to revert clock settings for this eth. */ |
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i--; |
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goto clk_unconfigure; |
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} |
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} |
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if (suspend) { |
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clk_bulk_disable_unprepare(AT91_PM_ETH_MAX_CLK, eth->clks); |
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} else { |
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ret = clk_bulk_prepare_enable(AT91_PM_ETH_MAX_CLK, |
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eth->clks); |
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if (ret) |
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goto clk_unconfigure; |
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/* |
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* Release the reference to eth->dev taken in |
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* at91_pm_eth_quirk_is_valid(). |
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*/ |
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put_device(eth->dev); |
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eth->dev = NULL; |
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} |
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} |
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return 0; |
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clk_unconfigure: |
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/* |
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* In case of resume we reach this point if clk_prepare_enable() failed. |
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* we don't want to revert the previous clk_prepare_enable() for the |
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* other IP. |
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*/ |
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for (j = i; j >= 0; j--) { |
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eth = &soc_pm.quirks.eth[j]; |
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if (suspend) { |
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if (!at91_pm_eth_quirk_is_valid(eth)) |
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continue; |
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|
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tmp = clk_bulk_prepare_enable(AT91_PM_ETH_MAX_CLK, eth->clks); |
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if (tmp) { |
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pr_err("AT91: PM: failed to enable %s clocks\n", |
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j == AT91_PM_G_ETH ? "geth" : "eth"); |
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} |
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} else { |
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/* |
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* Release the reference to eth->dev taken in |
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* at91_pm_eth_quirk_is_valid(). |
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*/ |
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put_device(eth->dev); |
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eth->dev = NULL; |
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} |
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} |
|
|
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return ret; |
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} |
|
|
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/* |
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* Called after processes are frozen, but before we shutdown devices. |
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*/ |
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static int at91_pm_begin(suspend_state_t state) |
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{ |
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int ret; |
|
|
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switch (state) { |
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case PM_SUSPEND_MEM: |
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soc_pm.data.mode = soc_pm.data.suspend_mode; |
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break; |
|
|
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case PM_SUSPEND_STANDBY: |
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soc_pm.data.mode = soc_pm.data.standby_mode; |
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break; |
|
|
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default: |
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soc_pm.data.mode = -1; |
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} |
|
|
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ret = at91_pm_config_ws(soc_pm.data.mode, true); |
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if (ret) |
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return ret; |
|
|
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if (soc_pm.data.mode == AT91_PM_BACKUP) |
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soc_pm.bu->suspended = 1; |
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else if (soc_pm.bu) |
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soc_pm.bu->suspended = 0; |
|
|
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return 0; |
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} |
|
|
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/* |
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* Verify that all the clocks are correct before entering |
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* slow-clock mode. |
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*/ |
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static int at91_pm_verify_clocks(void) |
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{ |
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unsigned long scsr; |
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int i; |
|
|
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scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR); |
|
|
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/* USB must not be using PLLB */ |
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if ((scsr & soc_pm.data.uhp_udp_mask) != 0) { |
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pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); |
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return 0; |
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} |
|
|
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/* PCK0..PCK3 must be disabled, or configured to use clk32k */ |
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for (i = 0; i < 4; i++) { |
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u32 css; |
|
|
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if ((scsr & (AT91_PMC_PCK0 << i)) == 0) |
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continue; |
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css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS; |
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if (css != AT91_PMC_CSS_SLOW) { |
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pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css); |
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return 0; |
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} |
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} |
|
|
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return 1; |
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} |
|
|
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/* |
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* Call this from platform driver suspend() to see how deeply to suspend. |
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* For example, some controllers (like OHCI) need one of the PLL clocks |
|
* in order to act as a wakeup source, and those are not available when |
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* going into slow clock mode. |
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* |
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* REVISIT: generalize as clk_will_be_available(clk)? Other platforms have |
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* the very same problem (but not using at91 main_clk), and it'd be better |
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* to add one generic API rather than lots of platform-specific ones. |
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*/ |
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int at91_suspend_entering_slow_clock(void) |
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{ |
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return (soc_pm.data.mode >= AT91_PM_ULP0); |
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} |
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EXPORT_SYMBOL(at91_suspend_entering_slow_clock); |
|
|
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static void (*at91_suspend_sram_fn)(struct at91_pm_data *); |
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extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data); |
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extern u32 at91_pm_suspend_in_sram_sz; |
|
|
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static int at91_suspend_finish(unsigned long val) |
|
{ |
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unsigned char modified_gray_code[] = { |
|
0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, 0x0c, 0x0d, |
|
0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, 0x18, 0x19, 0x1a, 0x1b, |
|
0x1e, 0x1f, 0x1c, 0x1d, 0x14, 0x15, 0x16, 0x17, 0x12, 0x13, |
|
0x10, 0x11, |
|
}; |
|
unsigned int tmp, index; |
|
int i; |
|
|
|
if (soc_pm.data.mode == AT91_PM_BACKUP && soc_pm.data.ramc_phy) { |
|
/* |
|
* Bootloader will perform DDR recalibration and will try to |
|
* restore the ZQ0SR0 with the value saved here. But the |
|
* calibration is buggy and restoring some values from ZQ0SR0 |
|
* is forbidden and risky thus we need to provide processed |
|
* values for these (modified gray code values). |
|
*/ |
|
tmp = readl(soc_pm.data.ramc_phy + DDR3PHY_ZQ0SR0); |
|
|
|
/* Store pull-down output impedance select. */ |
|
index = (tmp >> DDR3PHY_ZQ0SR0_PDO_OFF) & 0x1f; |
|
soc_pm.bu->ddr_phy_calibration[0] = modified_gray_code[index]; |
|
|
|
/* Store pull-up output impedance select. */ |
|
index = (tmp >> DDR3PHY_ZQ0SR0_PUO_OFF) & 0x1f; |
|
soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index]; |
|
|
|
/* Store pull-down on-die termination impedance select. */ |
|
index = (tmp >> DDR3PHY_ZQ0SR0_PDODT_OFF) & 0x1f; |
|
soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index]; |
|
|
|
/* Store pull-up on-die termination impedance select. */ |
|
index = (tmp >> DDR3PHY_ZQ0SRO_PUODT_OFF) & 0x1f; |
|
soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index]; |
|
|
|
/* |
|
* The 1st 8 words of memory might get corrupted in the process |
|
* of DDR PHY recalibration; it is saved here in securam and it |
|
* will be restored later, after recalibration, by bootloader |
|
*/ |
|
for (i = 1; i < BACKUP_DDR_PHY_CALIBRATION; i++) |
|
soc_pm.bu->ddr_phy_calibration[i] = |
|
*((unsigned int *)soc_pm.memcs + (i - 1)); |
|
} |
|
|
|
flush_cache_all(); |
|
outer_disable(); |
|
|
|
at91_suspend_sram_fn(&soc_pm.data); |
|
|
|
return 0; |
|
} |
|
|
|
static void at91_pm_switch_ba_to_vbat(void) |
|
{ |
|
unsigned int offset = offsetof(struct at91_pm_sfrbu_regs, pswbu); |
|
unsigned int val; |
|
|
|
/* Just for safety. */ |
|
if (!soc_pm.data.sfrbu) |
|
return; |
|
|
|
val = readl(soc_pm.data.sfrbu + offset); |
|
|
|
/* Already on VBAT. */ |
|
if (!(val & soc_pm.sfrbu_regs.pswbu.state)) |
|
return; |
|
|
|
val &= ~soc_pm.sfrbu_regs.pswbu.softsw; |
|
val |= soc_pm.sfrbu_regs.pswbu.key | soc_pm.sfrbu_regs.pswbu.ctrl; |
|
writel(val, soc_pm.data.sfrbu + offset); |
|
|
|
/* Wait for update. */ |
|
val = readl(soc_pm.data.sfrbu + offset); |
|
while (val & soc_pm.sfrbu_regs.pswbu.state) |
|
val = readl(soc_pm.data.sfrbu + offset); |
|
} |
|
|
|
static void at91_pm_suspend(suspend_state_t state) |
|
{ |
|
if (soc_pm.data.mode == AT91_PM_BACKUP) { |
|
at91_pm_switch_ba_to_vbat(); |
|
|
|
cpu_suspend(0, at91_suspend_finish); |
|
|
|
/* The SRAM is lost between suspend cycles */ |
|
at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn, |
|
&at91_pm_suspend_in_sram, |
|
at91_pm_suspend_in_sram_sz); |
|
} else { |
|
at91_suspend_finish(0); |
|
} |
|
|
|
outer_resume(); |
|
} |
|
|
|
/* |
|
* STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup' |
|
* event sources; and reduces DRAM power. But otherwise it's identical to |
|
* PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks. |
|
* |
|
* AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must |
|
* suspend more deeply, the master clock switches to the clk32k and turns off |
|
* the main oscillator |
|
* |
|
* AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh |
|
*/ |
|
static int at91_pm_enter(suspend_state_t state) |
|
{ |
|
int ret; |
|
|
|
ret = at91_pm_config_quirks(true); |
|
if (ret) |
|
return ret; |
|
|
|
switch (state) { |
|
case PM_SUSPEND_MEM: |
|
case PM_SUSPEND_STANDBY: |
|
/* |
|
* Ensure that clocks are in a valid state. |
|
*/ |
|
if (soc_pm.data.mode >= AT91_PM_ULP0 && |
|
!at91_pm_verify_clocks()) |
|
goto error; |
|
|
|
at91_pm_suspend(state); |
|
|
|
break; |
|
|
|
case PM_SUSPEND_ON: |
|
cpu_do_idle(); |
|
break; |
|
|
|
default: |
|
pr_debug("AT91: PM - bogus suspend state %d\n", state); |
|
goto error; |
|
} |
|
|
|
error: |
|
at91_pm_config_quirks(false); |
|
return 0; |
|
} |
|
|
|
/* |
|
* Called right prior to thawing processes. |
|
*/ |
|
static void at91_pm_end(void) |
|
{ |
|
at91_pm_config_ws(soc_pm.data.mode, false); |
|
} |
|
|
|
|
|
static const struct platform_suspend_ops at91_pm_ops = { |
|
.valid = at91_pm_valid_state, |
|
.begin = at91_pm_begin, |
|
.enter = at91_pm_enter, |
|
.end = at91_pm_end, |
|
}; |
|
|
|
static struct platform_device at91_cpuidle_device = { |
|
.name = "cpuidle-at91", |
|
}; |
|
|
|
/* |
|
* The AT91RM9200 goes into self-refresh mode with this command, and will |
|
* terminate self-refresh automatically on the next SDRAM access. |
|
* |
|
* Self-refresh mode is exited as soon as a memory access is made, but we don't |
|
* know for sure when that happens. However, we need to restore the low-power |
|
* mode if it was enabled before going idle. Restoring low-power mode while |
|
* still in self-refresh is "not recommended", but seems to work. |
|
*/ |
|
static void at91rm9200_standby(void) |
|
{ |
|
asm volatile( |
|
"b 1f\n\t" |
|
".align 5\n\t" |
|
"1: mcr p15, 0, %0, c7, c10, 4\n\t" |
|
" str %2, [%1, %3]\n\t" |
|
" mcr p15, 0, %0, c7, c0, 4\n\t" |
|
: |
|
: "r" (0), "r" (soc_pm.data.ramc[0]), |
|
"r" (1), "r" (AT91_MC_SDRAMC_SRR)); |
|
} |
|
|
|
/* We manage both DDRAM/SDRAM controllers, we need more than one value to |
|
* remember. |
|
*/ |
|
static void at91_ddr_standby(void) |
|
{ |
|
/* Those two values allow us to delay self-refresh activation |
|
* to the maximum. */ |
|
u32 lpr0, lpr1 = 0; |
|
u32 mdr, saved_mdr0, saved_mdr1 = 0; |
|
u32 saved_lpr0, saved_lpr1 = 0; |
|
|
|
/* LPDDR1 --> force DDR2 mode during self-refresh */ |
|
saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR); |
|
if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) { |
|
mdr = saved_mdr0 & ~AT91_DDRSDRC_MD; |
|
mdr |= AT91_DDRSDRC_MD_DDR2; |
|
at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr); |
|
} |
|
|
|
if (soc_pm.data.ramc[1]) { |
|
saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); |
|
lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB; |
|
lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; |
|
saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR); |
|
if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) { |
|
mdr = saved_mdr1 & ~AT91_DDRSDRC_MD; |
|
mdr |= AT91_DDRSDRC_MD_DDR2; |
|
at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr); |
|
} |
|
} |
|
|
|
saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); |
|
lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; |
|
lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH; |
|
|
|
/* self-refresh mode now */ |
|
at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); |
|
if (soc_pm.data.ramc[1]) |
|
at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); |
|
|
|
cpu_do_idle(); |
|
|
|
at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0); |
|
at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); |
|
if (soc_pm.data.ramc[1]) { |
|
at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1); |
|
at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); |
|
} |
|
} |
|
|
|
static void sama5d3_ddr_standby(void) |
|
{ |
|
u32 lpr0; |
|
u32 saved_lpr0; |
|
|
|
saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); |
|
lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB; |
|
lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN; |
|
|
|
at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); |
|
|
|
cpu_do_idle(); |
|
|
|
at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); |
|
} |
|
|
|
/* We manage both DDRAM/SDRAM controllers, we need more than one value to |
|
* remember. |
|
*/ |
|
static void at91sam9_sdram_standby(void) |
|
{ |
|
u32 lpr0, lpr1 = 0; |
|
u32 saved_lpr0, saved_lpr1 = 0; |
|
|
|
if (soc_pm.data.ramc[1]) { |
|
saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR); |
|
lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB; |
|
lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH; |
|
} |
|
|
|
saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR); |
|
lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB; |
|
lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH; |
|
|
|
/* self-refresh mode now */ |
|
at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0); |
|
if (soc_pm.data.ramc[1]) |
|
at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1); |
|
|
|
cpu_do_idle(); |
|
|
|
at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0); |
|
if (soc_pm.data.ramc[1]) |
|
at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); |
|
} |
|
|
|
static void sama7g5_standby(void) |
|
{ |
|
int pwrtmg, ratio; |
|
|
|
pwrtmg = readl(soc_pm.data.ramc[0] + UDDRC_PWRCTL); |
|
ratio = readl(soc_pm.data.pmc + AT91_PMC_RATIO); |
|
|
|
/* |
|
* Place RAM into self-refresh after a maximum idle clocks. The maximum |
|
* idle clocks is configured by bootloader in |
|
* UDDRC_PWRMGT.SELFREF_TO_X32. |
|
*/ |
|
writel(pwrtmg | UDDRC_PWRCTL_SELFREF_EN, |
|
soc_pm.data.ramc[0] + UDDRC_PWRCTL); |
|
/* Divide CPU clock by 16. */ |
|
writel(ratio & ~AT91_PMC_RATIO_RATIO, soc_pm.data.pmc + AT91_PMC_RATIO); |
|
|
|
cpu_do_idle(); |
|
|
|
/* Restore previous configuration. */ |
|
writel(ratio, soc_pm.data.pmc + AT91_PMC_RATIO); |
|
writel(pwrtmg, soc_pm.data.ramc[0] + UDDRC_PWRCTL); |
|
} |
|
|
|
struct ramc_info { |
|
void (*idle)(void); |
|
unsigned int memctrl; |
|
}; |
|
|
|
static const struct ramc_info ramc_infos[] __initconst = { |
|
{ .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC}, |
|
{ .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC}, |
|
{ .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR}, |
|
{ .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR}, |
|
{ .idle = sama7g5_standby, }, |
|
}; |
|
|
|
static const struct of_device_id ramc_ids[] __initconst = { |
|
{ .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] }, |
|
{ .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] }, |
|
{ .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] }, |
|
{ .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] }, |
|
{ .compatible = "microchip,sama7g5-uddrc", .data = &ramc_infos[4], }, |
|
{ /*sentinel*/ } |
|
}; |
|
|
|
static const struct of_device_id ramc_phy_ids[] __initconst = { |
|
{ .compatible = "microchip,sama7g5-ddr3phy", }, |
|
{ /* Sentinel. */ }, |
|
}; |
|
|
|
static __init int at91_dt_ramc(bool phy_mandatory) |
|
{ |
|
struct device_node *np; |
|
const struct of_device_id *of_id; |
|
int idx = 0; |
|
void *standby = NULL; |
|
const struct ramc_info *ramc; |
|
int ret; |
|
|
|
for_each_matching_node_and_match(np, ramc_ids, &of_id) { |
|
soc_pm.data.ramc[idx] = of_iomap(np, 0); |
|
if (!soc_pm.data.ramc[idx]) { |
|
pr_err("unable to map ramc[%d] cpu registers\n", idx); |
|
ret = -ENOMEM; |
|
of_node_put(np); |
|
goto unmap_ramc; |
|
} |
|
|
|
ramc = of_id->data; |
|
if (ramc) { |
|
if (!standby) |
|
standby = ramc->idle; |
|
soc_pm.data.memctrl = ramc->memctrl; |
|
} |
|
|
|
idx++; |
|
} |
|
|
|
if (!idx) { |
|
pr_err("unable to find compatible ram controller node in dtb\n"); |
|
ret = -ENODEV; |
|
goto unmap_ramc; |
|
} |
|
|
|
/* Lookup for DDR PHY node, if any. */ |
|
for_each_matching_node_and_match(np, ramc_phy_ids, &of_id) { |
|
soc_pm.data.ramc_phy = of_iomap(np, 0); |
|
if (!soc_pm.data.ramc_phy) { |
|
pr_err("unable to map ramc phy cpu registers\n"); |
|
ret = -ENOMEM; |
|
of_node_put(np); |
|
goto unmap_ramc; |
|
} |
|
} |
|
|
|
if (phy_mandatory && !soc_pm.data.ramc_phy) { |
|
pr_err("DDR PHY is mandatory!\n"); |
|
ret = -ENODEV; |
|
goto unmap_ramc; |
|
} |
|
|
|
if (!standby) { |
|
pr_warn("ramc no standby function available\n"); |
|
return 0; |
|
} |
|
|
|
at91_cpuidle_device.dev.platform_data = standby; |
|
|
|
return 0; |
|
|
|
unmap_ramc: |
|
while (idx) |
|
iounmap(soc_pm.data.ramc[--idx]); |
|
|
|
return ret; |
|
} |
|
|
|
static void at91rm9200_idle(void) |
|
{ |
|
/* |
|
* Disable the processor clock. The processor will be automatically |
|
* re-enabled by an interrupt or by a reset. |
|
*/ |
|
writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR); |
|
} |
|
|
|
static void at91sam9_idle(void) |
|
{ |
|
writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR); |
|
cpu_do_idle(); |
|
} |
|
|
|
static void __init at91_pm_sram_init(void) |
|
{ |
|
struct gen_pool *sram_pool; |
|
phys_addr_t sram_pbase; |
|
unsigned long sram_base; |
|
struct device_node *node; |
|
struct platform_device *pdev = NULL; |
|
|
|
for_each_compatible_node(node, NULL, "mmio-sram") { |
|
pdev = of_find_device_by_node(node); |
|
if (pdev) { |
|
of_node_put(node); |
|
break; |
|
} |
|
} |
|
|
|
if (!pdev) { |
|
pr_warn("%s: failed to find sram device!\n", __func__); |
|
return; |
|
} |
|
|
|
sram_pool = gen_pool_get(&pdev->dev, NULL); |
|
if (!sram_pool) { |
|
pr_warn("%s: sram pool unavailable!\n", __func__); |
|
goto out_put_device; |
|
} |
|
|
|
sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz); |
|
if (!sram_base) { |
|
pr_warn("%s: unable to alloc sram!\n", __func__); |
|
goto out_put_device; |
|
} |
|
|
|
sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base); |
|
at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase, |
|
at91_pm_suspend_in_sram_sz, false); |
|
if (!at91_suspend_sram_fn) { |
|
pr_warn("SRAM: Could not map\n"); |
|
goto out_put_device; |
|
} |
|
|
|
/* Copy the pm suspend handler to SRAM */ |
|
at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn, |
|
&at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz); |
|
return; |
|
|
|
out_put_device: |
|
put_device(&pdev->dev); |
|
return; |
|
} |
|
|
|
static bool __init at91_is_pm_mode_active(int pm_mode) |
|
{ |
|
return (soc_pm.data.standby_mode == pm_mode || |
|
soc_pm.data.suspend_mode == pm_mode); |
|
} |
|
|
|
static int __init at91_pm_backup_scan_memcs(unsigned long node, |
|
const char *uname, int depth, |
|
void *data) |
|
{ |
|
const char *type; |
|
const __be32 *reg; |
|
int *located = data; |
|
int size; |
|
|
|
/* Memory node already located. */ |
|
if (*located) |
|
return 0; |
|
|
|
type = of_get_flat_dt_prop(node, "device_type", NULL); |
|
|
|
/* We are scanning "memory" nodes only. */ |
|
if (!type || strcmp(type, "memory")) |
|
return 0; |
|
|
|
reg = of_get_flat_dt_prop(node, "reg", &size); |
|
if (reg) { |
|
soc_pm.memcs = __va((phys_addr_t)be32_to_cpu(*reg)); |
|
*located = 1; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int __init at91_pm_backup_init(void) |
|
{ |
|
struct gen_pool *sram_pool; |
|
struct device_node *np; |
|
struct platform_device *pdev; |
|
int ret = -ENODEV, located = 0; |
|
|
|
if (!IS_ENABLED(CONFIG_SOC_SAMA5D2) && |
|
!IS_ENABLED(CONFIG_SOC_SAMA7G5)) |
|
return -EPERM; |
|
|
|
if (!at91_is_pm_mode_active(AT91_PM_BACKUP)) |
|
return 0; |
|
|
|
np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam"); |
|
if (!np) |
|
return ret; |
|
|
|
pdev = of_find_device_by_node(np); |
|
of_node_put(np); |
|
if (!pdev) { |
|
pr_warn("%s: failed to find securam device!\n", __func__); |
|
return ret; |
|
} |
|
|
|
sram_pool = gen_pool_get(&pdev->dev, NULL); |
|
if (!sram_pool) { |
|
pr_warn("%s: securam pool unavailable!\n", __func__); |
|
goto securam_fail; |
|
} |
|
|
|
soc_pm.bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu)); |
|
if (!soc_pm.bu) { |
|
pr_warn("%s: unable to alloc securam!\n", __func__); |
|
ret = -ENOMEM; |
|
goto securam_fail; |
|
} |
|
|
|
soc_pm.bu->suspended = 0; |
|
soc_pm.bu->canary = __pa_symbol(&canary); |
|
soc_pm.bu->resume = __pa_symbol(cpu_resume); |
|
if (soc_pm.data.ramc_phy) { |
|
of_scan_flat_dt(at91_pm_backup_scan_memcs, &located); |
|
if (!located) |
|
goto securam_fail; |
|
} |
|
|
|
return 0; |
|
|
|
securam_fail: |
|
put_device(&pdev->dev); |
|
return ret; |
|
} |
|
|
|
static void __init at91_pm_secure_init(void) |
|
{ |
|
int suspend_mode; |
|
struct arm_smccc_res res; |
|
|
|
suspend_mode = soc_pm.data.suspend_mode; |
|
|
|
res = sam_smccc_call(SAMA5_SMC_SIP_SET_SUSPEND_MODE, |
|
suspend_mode, 0); |
|
if (res.a0 == 0) { |
|
pr_info("AT91: Secure PM: suspend mode set to %s\n", |
|
pm_modes[suspend_mode].pattern); |
|
return; |
|
} |
|
|
|
pr_warn("AT91: Secure PM: %s mode not supported !\n", |
|
pm_modes[suspend_mode].pattern); |
|
|
|
res = sam_smccc_call(SAMA5_SMC_SIP_GET_SUSPEND_MODE, 0, 0); |
|
if (res.a0 == 0) { |
|
pr_warn("AT91: Secure PM: failed to get default mode\n"); |
|
return; |
|
} |
|
|
|
pr_info("AT91: Secure PM: using default suspend mode %s\n", |
|
pm_modes[suspend_mode].pattern); |
|
|
|
soc_pm.data.suspend_mode = res.a1; |
|
} |
|
static const struct of_device_id atmel_shdwc_ids[] = { |
|
{ .compatible = "atmel,sama5d2-shdwc" }, |
|
{ .compatible = "microchip,sam9x60-shdwc" }, |
|
{ .compatible = "microchip,sama7g5-shdwc" }, |
|
{ /* sentinel. */ } |
|
}; |
|
|
|
static const struct of_device_id gmac_ids[] __initconst = { |
|
{ .compatible = "atmel,sama5d3-gem" }, |
|
{ .compatible = "atmel,sama5d2-gem" }, |
|
{ .compatible = "atmel,sama5d29-gem" }, |
|
{ .compatible = "microchip,sama7g5-gem" }, |
|
{ }, |
|
}; |
|
|
|
static const struct of_device_id emac_ids[] __initconst = { |
|
{ .compatible = "atmel,sama5d3-macb" }, |
|
{ .compatible = "microchip,sama7g5-emac" }, |
|
{ }, |
|
}; |
|
|
|
/* |
|
* Replaces _mode_to_replace with a supported mode that doesn't depend |
|
* on controller pointed by _map_bitmask |
|
* @_maps: u32 array containing AT91_PM_IOMAP() flags and indexed by AT91 |
|
* PM mode |
|
* @_map_bitmask: AT91_PM_IOMAP() bitmask; if _mode_to_replace depends on |
|
* controller represented by _map_bitmask, _mode_to_replace needs to be |
|
* updated |
|
* @_mode_to_replace: standby_mode or suspend_mode that need to be |
|
* updated |
|
* @_mode_to_check: standby_mode or suspend_mode; this is needed here |
|
* to avoid having standby_mode and suspend_mode set with the same AT91 |
|
* PM mode |
|
*/ |
|
#define AT91_PM_REPLACE_MODE(_maps, _map_bitmask, _mode_to_replace, \ |
|
_mode_to_check) \ |
|
do { \ |
|
if (((_maps)[(_mode_to_replace)]) & (_map_bitmask)) { \ |
|
int _mode_to_use, _mode_complementary; \ |
|
/* Use ULP0 if it doesn't need _map_bitmask. */ \ |
|
if (!((_maps)[AT91_PM_ULP0] & (_map_bitmask))) {\ |
|
_mode_to_use = AT91_PM_ULP0; \ |
|
_mode_complementary = AT91_PM_STANDBY; \ |
|
} else { \ |
|
_mode_to_use = AT91_PM_STANDBY; \ |
|
_mode_complementary = AT91_PM_STANDBY; \ |
|
} \ |
|
\ |
|
if ((_mode_to_check) != _mode_to_use) \ |
|
(_mode_to_replace) = _mode_to_use; \ |
|
else \ |
|
(_mode_to_replace) = _mode_complementary;\ |
|
} \ |
|
} while (0) |
|
|
|
/* |
|
* Replaces standby and suspend modes with default supported modes: |
|
* ULP0 and STANDBY. |
|
* @_maps: u32 array indexed by AT91 PM mode containing AT91_PM_IOMAP() |
|
* flags |
|
* @_map: controller specific name; standby and suspend mode need to be |
|
* replaced in order to not depend on this controller |
|
*/ |
|
#define AT91_PM_REPLACE_MODES(_maps, _map) \ |
|
do { \ |
|
AT91_PM_REPLACE_MODE((_maps), BIT(AT91_PM_IOMAP_##_map),\ |
|
(soc_pm.data.standby_mode), \ |
|
(soc_pm.data.suspend_mode)); \ |
|
AT91_PM_REPLACE_MODE((_maps), BIT(AT91_PM_IOMAP_##_map),\ |
|
(soc_pm.data.suspend_mode), \ |
|
(soc_pm.data.standby_mode)); \ |
|
} while (0) |
|
|
|
static int __init at91_pm_get_eth_clks(struct device_node *np, |
|
struct clk_bulk_data *clks) |
|
{ |
|
clks[AT91_PM_ETH_PCLK].clk = of_clk_get_by_name(np, "pclk"); |
|
if (IS_ERR(clks[AT91_PM_ETH_PCLK].clk)) |
|
return PTR_ERR(clks[AT91_PM_ETH_PCLK].clk); |
|
|
|
clks[AT91_PM_ETH_HCLK].clk = of_clk_get_by_name(np, "hclk"); |
|
if (IS_ERR(clks[AT91_PM_ETH_HCLK].clk)) |
|
return PTR_ERR(clks[AT91_PM_ETH_HCLK].clk); |
|
|
|
return 0; |
|
} |
|
|
|
static int __init at91_pm_eth_clks_empty(struct clk_bulk_data *clks) |
|
{ |
|
return IS_ERR(clks[AT91_PM_ETH_PCLK].clk) || |
|
IS_ERR(clks[AT91_PM_ETH_HCLK].clk); |
|
} |
|
|
|
static void __init at91_pm_modes_init(const u32 *maps, int len) |
|
{ |
|
struct at91_pm_quirk_eth *gmac = &soc_pm.quirks.eth[AT91_PM_G_ETH]; |
|
struct at91_pm_quirk_eth *emac = &soc_pm.quirks.eth[AT91_PM_E_ETH]; |
|
struct device_node *np; |
|
int ret; |
|
|
|
ret = at91_pm_backup_init(); |
|
if (ret) { |
|
if (soc_pm.data.standby_mode == AT91_PM_BACKUP) |
|
soc_pm.data.standby_mode = AT91_PM_ULP0; |
|
if (soc_pm.data.suspend_mode == AT91_PM_BACKUP) |
|
soc_pm.data.suspend_mode = AT91_PM_ULP0; |
|
} |
|
|
|
if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) || |
|
maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) { |
|
np = of_find_matching_node(NULL, atmel_shdwc_ids); |
|
if (!np) { |
|
pr_warn("%s: failed to find shdwc!\n", __func__); |
|
AT91_PM_REPLACE_MODES(maps, SHDWC); |
|
} else { |
|
soc_pm.data.shdwc = of_iomap(np, 0); |
|
of_node_put(np); |
|
} |
|
} |
|
|
|
if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) || |
|
maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) { |
|
np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu"); |
|
if (!np) { |
|
pr_warn("%s: failed to find sfrbu!\n", __func__); |
|
AT91_PM_REPLACE_MODES(maps, SFRBU); |
|
} else { |
|
soc_pm.data.sfrbu = of_iomap(np, 0); |
|
of_node_put(np); |
|
} |
|
} |
|
|
|
if ((at91_is_pm_mode_active(AT91_PM_ULP1) || |
|
at91_is_pm_mode_active(AT91_PM_ULP0) || |
|
at91_is_pm_mode_active(AT91_PM_ULP0_FAST)) && |
|
(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(ETHC) || |
|
maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(ETHC))) { |
|
np = of_find_matching_node(NULL, gmac_ids); |
|
if (!np) { |
|
np = of_find_matching_node(NULL, emac_ids); |
|
if (np) |
|
goto get_emac_clks; |
|
AT91_PM_REPLACE_MODES(maps, ETHC); |
|
goto unmap_unused_nodes; |
|
} else { |
|
gmac->np = np; |
|
at91_pm_get_eth_clks(np, gmac->clks); |
|
} |
|
|
|
np = of_find_matching_node(NULL, emac_ids); |
|
if (!np) { |
|
if (at91_pm_eth_clks_empty(gmac->clks)) |
|
AT91_PM_REPLACE_MODES(maps, ETHC); |
|
} else { |
|
get_emac_clks: |
|
emac->np = np; |
|
ret = at91_pm_get_eth_clks(np, emac->clks); |
|
if (ret && at91_pm_eth_clks_empty(gmac->clks)) { |
|
of_node_put(gmac->np); |
|
of_node_put(emac->np); |
|
gmac->np = NULL; |
|
emac->np = NULL; |
|
} |
|
} |
|
} |
|
|
|
unmap_unused_nodes: |
|
/* Unmap all unnecessary. */ |
|
if (soc_pm.data.shdwc && |
|
!(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) || |
|
maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))) { |
|
iounmap(soc_pm.data.shdwc); |
|
soc_pm.data.shdwc = NULL; |
|
} |
|
|
|
if (soc_pm.data.sfrbu && |
|
!(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) || |
|
maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))) { |
|
iounmap(soc_pm.data.sfrbu); |
|
soc_pm.data.sfrbu = NULL; |
|
} |
|
|
|
return; |
|
} |
|
|
|
struct pmc_info { |
|
unsigned long uhp_udp_mask; |
|
unsigned long mckr; |
|
unsigned long version; |
|
}; |
|
|
|
static const struct pmc_info pmc_infos[] __initconst = { |
|
{ |
|
.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP, |
|
.mckr = 0x30, |
|
.version = AT91_PMC_V1, |
|
}, |
|
|
|
{ |
|
.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP, |
|
.mckr = 0x30, |
|
.version = AT91_PMC_V1, |
|
}, |
|
{ |
|
.uhp_udp_mask = AT91SAM926x_PMC_UHP, |
|
.mckr = 0x30, |
|
.version = AT91_PMC_V1, |
|
}, |
|
{ .uhp_udp_mask = 0, |
|
.mckr = 0x30, |
|
.version = AT91_PMC_V1, |
|
}, |
|
{ |
|
.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP, |
|
.mckr = 0x28, |
|
.version = AT91_PMC_V2, |
|
}, |
|
{ |
|
.mckr = 0x28, |
|
.version = AT91_PMC_V2, |
|
}, |
|
|
|
}; |
|
|
|
static const struct of_device_id atmel_pmc_ids[] __initconst = { |
|
{ .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] }, |
|
{ .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] }, |
|
{ .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] }, |
|
{ .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] }, |
|
{ .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] }, |
|
{ .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] }, |
|
{ .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] }, |
|
{ .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] }, |
|
{ .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] }, |
|
{ .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] }, |
|
{ .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] }, |
|
{ .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] }, |
|
{ .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] }, |
|
{ /* sentinel */ }, |
|
}; |
|
|
|
static void __init at91_pm_modes_validate(const int *modes, int len) |
|
{ |
|
u8 i, standby = 0, suspend = 0; |
|
int mode; |
|
|
|
for (i = 0; i < len; i++) { |
|
if (standby && suspend) |
|
break; |
|
|
|
if (modes[i] == soc_pm.data.standby_mode && !standby) { |
|
standby = 1; |
|
continue; |
|
} |
|
|
|
if (modes[i] == soc_pm.data.suspend_mode && !suspend) { |
|
suspend = 1; |
|
continue; |
|
} |
|
} |
|
|
|
if (!standby) { |
|
if (soc_pm.data.suspend_mode == AT91_PM_STANDBY) |
|
mode = AT91_PM_ULP0; |
|
else |
|
mode = AT91_PM_STANDBY; |
|
|
|
pr_warn("AT91: PM: %s mode not supported! Using %s.\n", |
|
pm_modes[soc_pm.data.standby_mode].pattern, |
|
pm_modes[mode].pattern); |
|
soc_pm.data.standby_mode = mode; |
|
} |
|
|
|
if (!suspend) { |
|
if (soc_pm.data.standby_mode == AT91_PM_ULP0) |
|
mode = AT91_PM_STANDBY; |
|
else |
|
mode = AT91_PM_ULP0; |
|
|
|
pr_warn("AT91: PM: %s mode not supported! Using %s.\n", |
|
pm_modes[soc_pm.data.suspend_mode].pattern, |
|
pm_modes[mode].pattern); |
|
soc_pm.data.suspend_mode = mode; |
|
} |
|
} |
|
|
|
static void __init at91_pm_init(void (*pm_idle)(void)) |
|
{ |
|
struct device_node *pmc_np; |
|
const struct of_device_id *of_id; |
|
const struct pmc_info *pmc; |
|
|
|
if (at91_cpuidle_device.dev.platform_data) |
|
platform_device_register(&at91_cpuidle_device); |
|
|
|
pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id); |
|
soc_pm.data.pmc = of_iomap(pmc_np, 0); |
|
of_node_put(pmc_np); |
|
if (!soc_pm.data.pmc) { |
|
pr_err("AT91: PM not supported, PMC not found\n"); |
|
return; |
|
} |
|
|
|
pmc = of_id->data; |
|
soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask; |
|
soc_pm.data.pmc_mckr_offset = pmc->mckr; |
|
soc_pm.data.pmc_version = pmc->version; |
|
|
|
if (pm_idle) |
|
arm_pm_idle = pm_idle; |
|
|
|
at91_pm_sram_init(); |
|
|
|
if (at91_suspend_sram_fn) { |
|
suspend_set_ops(&at91_pm_ops); |
|
pr_info("AT91: PM: standby: %s, suspend: %s\n", |
|
pm_modes[soc_pm.data.standby_mode].pattern, |
|
pm_modes[soc_pm.data.suspend_mode].pattern); |
|
} else { |
|
pr_info("AT91: PM not supported, due to no SRAM allocated\n"); |
|
} |
|
} |
|
|
|
void __init at91rm9200_pm_init(void) |
|
{ |
|
int ret; |
|
|
|
if (!IS_ENABLED(CONFIG_SOC_AT91RM9200)) |
|
return; |
|
|
|
/* |
|
* Force STANDBY and ULP0 mode to avoid calling |
|
* at91_pm_modes_validate() which may increase booting time. |
|
* Platform supports anyway only STANDBY and ULP0 modes. |
|
*/ |
|
soc_pm.data.standby_mode = AT91_PM_STANDBY; |
|
soc_pm.data.suspend_mode = AT91_PM_ULP0; |
|
|
|
ret = at91_dt_ramc(false); |
|
if (ret) |
|
return; |
|
|
|
/* |
|
* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. |
|
*/ |
|
at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0); |
|
|
|
at91_pm_init(at91rm9200_idle); |
|
} |
|
|
|
void __init sam9x60_pm_init(void) |
|
{ |
|
static const int modes[] __initconst = { |
|
AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1, |
|
}; |
|
static const int iomaps[] __initconst = { |
|
[AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC), |
|
}; |
|
int ret; |
|
|
|
if (!IS_ENABLED(CONFIG_SOC_SAM9X60)) |
|
return; |
|
|
|
at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); |
|
at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); |
|
ret = at91_dt_ramc(false); |
|
if (ret) |
|
return; |
|
|
|
at91_pm_init(NULL); |
|
|
|
soc_pm.ws_ids = sam9x60_ws_ids; |
|
soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws; |
|
} |
|
|
|
void __init at91sam9_pm_init(void) |
|
{ |
|
int ret; |
|
|
|
if (!IS_ENABLED(CONFIG_SOC_AT91SAM9)) |
|
return; |
|
|
|
/* |
|
* Force STANDBY and ULP0 mode to avoid calling |
|
* at91_pm_modes_validate() which may increase booting time. |
|
* Platform supports anyway only STANDBY and ULP0 modes. |
|
*/ |
|
soc_pm.data.standby_mode = AT91_PM_STANDBY; |
|
soc_pm.data.suspend_mode = AT91_PM_ULP0; |
|
|
|
ret = at91_dt_ramc(false); |
|
if (ret) |
|
return; |
|
|
|
at91_pm_init(at91sam9_idle); |
|
} |
|
|
|
void __init sama5_pm_init(void) |
|
{ |
|
static const int modes[] __initconst = { |
|
AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, |
|
}; |
|
static const u32 iomaps[] __initconst = { |
|
[AT91_PM_ULP0] = AT91_PM_IOMAP(ETHC), |
|
[AT91_PM_ULP0_FAST] = AT91_PM_IOMAP(ETHC), |
|
}; |
|
int ret; |
|
|
|
if (!IS_ENABLED(CONFIG_SOC_SAMA5)) |
|
return; |
|
|
|
at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); |
|
at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); |
|
ret = at91_dt_ramc(false); |
|
if (ret) |
|
return; |
|
|
|
at91_pm_init(NULL); |
|
|
|
/* Quirks applies to ULP0, ULP0 fast and ULP1 modes. */ |
|
soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP0) | |
|
BIT(AT91_PM_ULP0_FAST) | |
|
BIT(AT91_PM_ULP1); |
|
/* Do not suspend in ULP0, ULP0 fast if GETH is the only wakeup source. */ |
|
soc_pm.quirks.eth[AT91_PM_G_ETH].dns_modes = BIT(AT91_PM_ULP0) | |
|
BIT(AT91_PM_ULP0_FAST); |
|
} |
|
|
|
void __init sama5d2_pm_init(void) |
|
{ |
|
static const int modes[] __initconst = { |
|
AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1, |
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AT91_PM_BACKUP, |
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}; |
|
static const u32 iomaps[] __initconst = { |
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[AT91_PM_ULP0] = AT91_PM_IOMAP(ETHC), |
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[AT91_PM_ULP0_FAST] = AT91_PM_IOMAP(ETHC), |
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[AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC) | |
|
AT91_PM_IOMAP(ETHC), |
|
[AT91_PM_BACKUP] = AT91_PM_IOMAP(SHDWC) | |
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AT91_PM_IOMAP(SFRBU), |
|
}; |
|
int ret; |
|
|
|
if (!IS_ENABLED(CONFIG_SOC_SAMA5D2)) |
|
return; |
|
|
|
if (IS_ENABLED(CONFIG_ATMEL_SECURE_PM)) { |
|
pr_warn("AT91: Secure PM: ignoring standby mode\n"); |
|
at91_pm_secure_init(); |
|
return; |
|
} |
|
|
|
at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); |
|
at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); |
|
ret = at91_dt_ramc(false); |
|
if (ret) |
|
return; |
|
|
|
at91_pm_init(NULL); |
|
|
|
soc_pm.ws_ids = sama5d2_ws_ids; |
|
soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws; |
|
soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws; |
|
|
|
soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8); |
|
soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0); |
|
soc_pm.sfrbu_regs.pswbu.softsw = BIT(1); |
|
soc_pm.sfrbu_regs.pswbu.state = BIT(3); |
|
|
|
/* Quirk applies to ULP0, ULP0 fast and ULP1 modes. */ |
|
soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP0) | |
|
BIT(AT91_PM_ULP0_FAST) | |
|
BIT(AT91_PM_ULP1); |
|
/* |
|
* Do not suspend in ULP0, ULP0 fast if GETH is the only wakeup |
|
* source. |
|
*/ |
|
soc_pm.quirks.eth[AT91_PM_G_ETH].dns_modes = BIT(AT91_PM_ULP0) | |
|
BIT(AT91_PM_ULP0_FAST); |
|
} |
|
|
|
void __init sama7_pm_init(void) |
|
{ |
|
static const int modes[] __initconst = { |
|
AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP, |
|
}; |
|
static const u32 iomaps[] __initconst = { |
|
[AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU), |
|
[AT91_PM_ULP1] = AT91_PM_IOMAP(SFRBU) | |
|
AT91_PM_IOMAP(SHDWC) | |
|
AT91_PM_IOMAP(ETHC), |
|
[AT91_PM_BACKUP] = AT91_PM_IOMAP(SFRBU) | |
|
AT91_PM_IOMAP(SHDWC), |
|
}; |
|
int ret; |
|
|
|
if (!IS_ENABLED(CONFIG_SOC_SAMA7)) |
|
return; |
|
|
|
at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); |
|
|
|
ret = at91_dt_ramc(true); |
|
if (ret) |
|
return; |
|
|
|
at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); |
|
at91_pm_init(NULL); |
|
|
|
soc_pm.ws_ids = sama7g5_ws_ids; |
|
soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws; |
|
|
|
soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8); |
|
soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0); |
|
soc_pm.sfrbu_regs.pswbu.softsw = BIT(1); |
|
soc_pm.sfrbu_regs.pswbu.state = BIT(2); |
|
|
|
/* Quirks applies to ULP1 for both Ethernet interfaces. */ |
|
soc_pm.quirks.eth[AT91_PM_E_ETH].modes = BIT(AT91_PM_ULP1); |
|
soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP1); |
|
} |
|
|
|
static int __init at91_pm_modes_select(char *str) |
|
{ |
|
char *s; |
|
substring_t args[MAX_OPT_ARGS]; |
|
int standby, suspend; |
|
|
|
if (!str) |
|
return 0; |
|
|
|
s = strsep(&str, ","); |
|
standby = match_token(s, pm_modes, args); |
|
if (standby < 0) |
|
return 0; |
|
|
|
suspend = match_token(str, pm_modes, args); |
|
if (suspend < 0) |
|
return 0; |
|
|
|
soc_pm.data.standby_mode = standby; |
|
soc_pm.data.suspend_mode = suspend; |
|
|
|
return 0; |
|
} |
|
early_param("atmel.pm_modes", at91_pm_modes_select);
|
|
|