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42 lines
1.8 KiB
42 lines
1.8 KiB
* Hisilicon Universal Flash Storage (UFS) Host Controller |
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UFS nodes are defined to describe on-chip UFS hardware macro. |
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Each UFS Host Controller should have its own node. |
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Required properties: |
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- compatible : compatible list, contains one of the following - |
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"hisilicon,hi3660-ufs", "jedec,ufs-1.1" for hisi ufs |
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host controller present on Hi3660 chipset. |
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"hisilicon,hi3670-ufs", "jedec,ufs-2.1" for hisi ufs |
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host controller present on Hi3670 chipset. |
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- reg : should contain UFS register address space & UFS SYS CTRL register address, |
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- interrupts : interrupt number |
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- clocks : List of phandle and clock specifier pairs |
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- clock-names : List of clock input name strings sorted in the same |
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order as the clocks property. "ref_clk", "phy_clk" is optional |
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- freq-table-hz : Array of <min max> operating frequencies stored in the same |
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order as the clocks property. If this property is not |
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defined or a value in the array is "0" then it is assumed |
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that the frequency is set by the parent clock or a |
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fixed rate clock source. |
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- resets : describe reset node register |
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- reset-names : reset node register, the "rst" corresponds to reset the whole UFS IP. |
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Example: |
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ufs: ufs@ff3b0000 { |
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compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1"; |
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/* 0: HCI standard */ |
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/* 1: UFS SYS CTRL */ |
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reg = <0x0 0xff3b0000 0x0 0x1000>, |
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<0x0 0xff3b1000 0x0 0x1000>; |
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interrupt-parent = <&gic>; |
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interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, |
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<&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; |
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clock-names = "ref_clk", "phy_clk"; |
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freq-table-hz = <0 0>, <0 0>; |
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/* offset: 0x84; bit: 12 */ |
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resets = <&crg_rst 0x84 12>; |
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reset-names = "rst"; |
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};
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