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143 lines
4.7 KiB
143 lines
4.7 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-pinctrl.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Qualcomm Technologies, Inc. SM8450 TLMM block |
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maintainers: |
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- Vinod Koul <[email protected]> |
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description: | |
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This binding describes the Top Level Mode Multiplexer (TLMM) block found |
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in the SM8450 platform. |
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allOf: |
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# |
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properties: |
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compatible: |
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const: qcom,sm8450-tlmm |
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reg: |
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maxItems: 1 |
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interrupts: true |
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interrupt-controller: true |
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'#interrupt-cells': true |
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gpio-controller: true |
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gpio-reserved-ranges: true |
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'#gpio-cells': true |
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gpio-ranges: true |
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wakeup-parent: true |
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required: |
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- compatible |
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- reg |
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additionalProperties: false |
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patternProperties: |
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'-state$': |
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oneOf: |
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- $ref: "#/$defs/qcom-sm8450-tlmm-state" |
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- patternProperties: |
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".*": |
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$ref: "#/$defs/qcom-sm8450-tlmm-state" |
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$defs: |
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qcom-sm8450-tlmm-state: |
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type: object |
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description: |
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Pinctrl node's client devices use subnodes for desired pin configuration. |
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Client device subnodes use below standard properties. |
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$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" |
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properties: |
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pins: |
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description: |
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List of gpio pins affected by the properties specified in this |
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subnode. |
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items: |
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oneOf: |
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- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$" |
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- enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] |
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minItems: 1 |
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maxItems: 36 |
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function: |
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description: |
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Specify the alternative function to be configured for the specified |
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pins. |
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enum: [ aon_cam, atest_char, atest_usb, audio_ref, cam_mclk, cci_async, |
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cci_i2c, cci_timer, cmu_rng, coex_uart1, coex_uart2, cri_trng, |
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cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, |
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ddr_pxi2, ddr_pxi3, dp_hot, gcc_gp1, gcc_gp2, gcc_gp3, |
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gpio, ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1, |
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mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck, |
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mi2s0_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, |
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mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12, |
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mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, |
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mss_grfc7, mss_grfc8, mss_grfc9, nav, pcie0_clkreqn, |
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pcie1_clkreqn, phase_flag, pll_bist, pll_clk, pri_mi2s, |
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prng_rosc, qdss_cti, qdss_gpio, qlink0_enable, qlink0_request, |
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qlink0_wmss, qlink1_enable, qlink1_request, qlink1_wmss, |
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qlink2_enable, qlink2_request, qlink2_wmss, qspi0, qspi1, |
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qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, |
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qup12, qup13, qup14, qup15, qup16, qup17, qup18, qup19, qup2, |
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qup20, qup21, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, |
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qup_l5, qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk, |
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sdc4_cmd, sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, |
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tgu_ch3, tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3, |
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tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data, uim0_present, |
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uim0_reset, uim1_clk, uim1_data, uim1_present, uim1_reset, |
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usb2phy_ac, usb_phy, vfr_0, vfr_1, vsense_trigger ] |
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bias-disable: true |
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bias-pull-down: true |
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bias-pull-up: true |
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drive-strength: true |
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input-enable: true |
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output-high: true |
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output-low: true |
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required: |
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- pins |
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- function |
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additionalProperties: false |
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examples: |
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- | |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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pinctrl@f100000 { |
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compatible = "qcom,sm8450-tlmm"; |
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reg = <0x0f100000 0x300000>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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gpio-ranges = <&tlmm 0 0 211>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
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gpio-wo-subnode-state { |
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pins = "gpio1"; |
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function = "gpio"; |
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}; |
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uart-w-subnodes-state { |
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rx { |
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pins = "gpio26"; |
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function = "qup7"; |
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bias-pull-up; |
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}; |
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tx { |
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pins = "gpio27"; |
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function = "qup7"; |
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bias-disable; |
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}; |
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}; |
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}; |
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...
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