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181 lines
5.5 KiB
181 lines
5.5 KiB
Qualcomm Technologies, Inc. IPQ8074 TLMM block |
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This binding describes the Top Level Mode Multiplexer block found in the |
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IPQ8074 platform. |
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- compatible: |
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Usage: required |
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Value type: <string> |
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Definition: must be "qcom,ipq8074-pinctrl" |
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- reg: |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: the base address and size of the TLMM register space. |
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- interrupts: |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: should specify the TLMM summary IRQ. |
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- interrupt-controller: |
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Usage: required |
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Value type: <none> |
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Definition: identifies this node as an interrupt controller |
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- #interrupt-cells: |
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Usage: required |
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Value type: <u32> |
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Definition: must be 2. Specifying the pin number and flags, as defined |
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in <dt-bindings/interrupt-controller/irq.h> |
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- gpio-controller: |
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Usage: required |
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Value type: <none> |
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Definition: identifies this node as a gpio controller |
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- #gpio-cells: |
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Usage: required |
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Value type: <u32> |
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Definition: must be 2. Specifying the pin number and flags, as defined |
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in <dt-bindings/gpio/gpio.h> |
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- gpio-ranges: |
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Usage: required |
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Definition: see ../gpio/gpio.txt |
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- gpio-reserved-ranges: |
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Usage: optional |
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Definition: see ../gpio/gpio.txt |
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Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for |
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a general description of GPIO and interrupt bindings. |
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Please refer to pinctrl-bindings.txt in this directory for details of the |
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common pinctrl bindings used by client devices, including the meaning of the |
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phrase "pin configuration node". |
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The pin configuration nodes act as a container for an arbitrary number of |
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subnodes. Each of these subnodes represents some desired configuration for a |
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pin, a group, or a list of pins or groups. This configuration can include the |
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mux function to select on those pin(s)/group(s), and various pin configuration |
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parameters, such as pull-up, drive strength, etc. |
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PIN CONFIGURATION NODES: |
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The name of each subnode is not important; all subnodes should be enumerated |
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and processed purely based on their content. |
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Each subnode only affects those parameters that are explicitly listed. In |
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other words, a subnode that lists a mux function but no pin configuration |
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parameters implies no information about any pin configuration parameters. |
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Similarly, a pin subnode that describes a pullup parameter implies no |
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information about e.g. the mux function. |
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The following generic properties as defined in pinctrl-bindings.txt are valid |
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to specify in a pin configuration subnode: |
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- pins: |
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Usage: required |
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Value type: <string-array> |
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Definition: List of gpio pins affected by the properties specified in |
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this subnode. Valid pins are: |
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gpio0-gpio69 |
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- function: |
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Usage: required |
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Value type: <string> |
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Definition: Specify the alternative function to be configured for the |
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specified pins. Functions are only valid for gpio pins. |
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Valid values are: |
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atest_char, atest_char0, atest_char1, atest_char2, |
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atest_char3, audio_rxbclk, audio_rxd, audio_rxfsync, |
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audio_rxmclk, audio_txbclk, audio_txd, audio_txfsync, |
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audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart, blsp1_i2c, |
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blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi, blsp2_uart, |
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blsp3_i2c, blsp3_spi, blsp3_spi0, blsp3_spi1, blsp3_spi2, |
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blsp3_spi3, blsp3_uart, blsp4_i2c0, blsp4_i2c1, blsp4_spi0, |
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blsp4_spi1, blsp4_uart0, blsp4_uart1, blsp5_i2c, blsp5_spi, |
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blsp5_uart, burn0, burn1, cri_trng, cri_trng0, cri_trng1, |
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cxc0, cxc1, dbg_out, gcc_plltest, gcc_tlmm, gpio, ldo_en, |
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ldo_update, led0, led1, led2, mac0_sa0, mac0_sa1, mac1_sa0, |
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mac1_sa1, mac1_sa2, mac1_sa3, mac2_sa0, mac2_sa1, mdc, |
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mdio, pcie0_clk, pcie0_rst, pcie0_wake, pcie1_clk, |
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pcie1_rst, pcie1_wake, pcm_drx, pcm_dtx, pcm_fsync, |
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pcm_pclk, pcm_zsi0, pcm_zsi1, prng_rosc, pta1_0, pta1_1, |
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pta1_2, pta2_0, pta2_1, pta2_2, pwm0, pwm1, pwm2, pwm3, |
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qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, |
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qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, |
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qdss_cti_trig_out_a0, qdss_cti_trig_out_a1, |
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qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, |
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qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a, |
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qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b, |
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qpic, rx0, rx1, rx2, sd_card, sd_write, tsens_max, wci2a, |
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wci2b, wci2c, wci2d |
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- bias-disable: |
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Usage: optional |
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Value type: <none> |
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Definition: The specified pins should be configured as no pull. |
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- bias-pull-down: |
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Usage: optional |
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Value type: <none> |
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Definition: The specified pins should be configured as pull down. |
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- bias-pull-up: |
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Usage: optional |
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Value type: <none> |
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Definition: The specified pins should be configured as pull up. |
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- output-high: |
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Usage: optional |
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Value type: <none> |
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Definition: The specified pins are configured in output mode, driven |
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high. |
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- output-low: |
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Usage: optional |
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Value type: <none> |
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Definition: The specified pins are configured in output mode, driven |
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low. |
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- drive-strength: |
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Usage: optional |
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Value type: <u32> |
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Definition: Selects the drive strength for the specified pins, in mA. |
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Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 |
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Example: |
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tlmm: pinctrl@1000000 { |
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compatible = "qcom,ipq8074-pinctrl"; |
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reg = <0x1000000 0x300000>; |
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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gpio-ranges = <&tlmm 0 0 70>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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uart2: uart2-default { |
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mux { |
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pins = "gpio23", "gpio24"; |
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function = "blsp4_uart1"; |
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}; |
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rx { |
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pins = "gpio23"; |
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drive-strength = <4>; |
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bias-disable; |
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}; |
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tx { |
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pins = "gpio24"; |
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drive-strength = <2>; |
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bias-pull-up; |
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}; |
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}; |
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};
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