forked from Qortal/Brooklyn
You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
101 lines
3.3 KiB
101 lines
3.3 KiB
Qualcomm IPQ8064 TLMM block |
|
|
|
Required properties: |
|
- compatible: "qcom,ipq8064-pinctrl" |
|
- reg: Should be the base address and length of the TLMM block. |
|
- interrupts: Should be the parent IRQ of the TLMM block. |
|
- interrupt-controller: Marks the device node as an interrupt controller. |
|
- #interrupt-cells: Should be two. |
|
- gpio-controller: Marks the device node as a GPIO controller. |
|
- #gpio-cells : Should be two. |
|
The first cell is the gpio pin number and the |
|
second cell is used for optional parameters. |
|
- gpio-ranges: see ../gpio/gpio.txt |
|
|
|
Optional properties: |
|
|
|
- gpio-reserved-ranges: see ../gpio/gpio.txt |
|
|
|
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for |
|
a general description of GPIO and interrupt bindings. |
|
|
|
Please refer to pinctrl-bindings.txt in this directory for details of the |
|
common pinctrl bindings used by client devices, including the meaning of the |
|
phrase "pin configuration node". |
|
|
|
Qualcomm's pin configuration nodes act as a container for an arbitrary number of |
|
subnodes. Each of these subnodes represents some desired configuration for a |
|
pin, a group, or a list of pins or groups. This configuration can include the |
|
mux function to select on those pin(s)/group(s), and various pin configuration |
|
parameters, such as pull-up, drive strength, etc. |
|
|
|
The name of each subnode is not important; all subnodes should be enumerated |
|
and processed purely based on their content. |
|
|
|
Each subnode only affects those parameters that are explicitly listed. In |
|
other words, a subnode that lists a mux function but no pin configuration |
|
parameters implies no information about any pin configuration parameters. |
|
Similarly, a pin subnode that describes a pullup parameter implies no |
|
information about e.g. the mux function. |
|
|
|
|
|
The following generic properties as defined in pinctrl-bindings.txt are valid |
|
to specify in a pin configuration subnode: |
|
|
|
pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-strength, |
|
output-low, output-high. |
|
|
|
Non-empty subnodes must specify the 'pins' property. |
|
|
|
Valid values for qcom,pins are: |
|
gpio0-gpio68 |
|
Supports mux, bias, and drive-strength |
|
|
|
sdc3_clk, sdc3_cmd, sdc3_data |
|
Supports bias and drive-strength |
|
|
|
|
|
Valid values for function are: |
|
mdio, mi2s, pdm, ssbi, spmi, audio_pcm, gpio, gsbi1, gsbi2, gsbi4, gsbi5, |
|
gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6, gsbi7, nss_spi, sdc1, |
|
spdif, nand, tsif1, tsif2, usb_fs_n, usb_fs, usb2_hsic, rgmii2, sata, |
|
pcie1_rst, pcie1_prsnt, pcie1_pwren_n, pcie1_pwren, pcie1_pwrflt, |
|
pcie1_clk_req, pcie2_rst, pcie2_prsnt, pcie2_pwren_n, pcie2_pwren, |
|
pcie2_pwrflt, pcie2_clk_req, pcie3_rst, pcie3_prsnt, pcie3_pwren_n, |
|
pcie3_pwren, pcie3_pwrflt, pcie3_clk_req, ps_hold |
|
|
|
Example: |
|
|
|
pinmux: pinctrl@800000 { |
|
compatible = "qcom,ipq8064-pinctrl"; |
|
reg = <0x800000 0x4000>; |
|
|
|
gpio-controller; |
|
#gpio-cells = <2>; |
|
gpio-ranges = <&pinmux 0 0 69>; |
|
interrupt-controller; |
|
#interrupt-cells = <2>; |
|
interrupts = <0 32 0x4>; |
|
|
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&gsbi5_uart_default>; |
|
|
|
gsbi5_uart_default: gsbi5_uart_default { |
|
mux { |
|
pins = "gpio18", "gpio19"; |
|
function = "gsbi5"; |
|
}; |
|
|
|
tx { |
|
pins = "gpio18"; |
|
drive-strength = <4>; |
|
bias-disable; |
|
}; |
|
|
|
rx { |
|
pins = "gpio19"; |
|
drive-strength = <2>; |
|
bias-pull-up; |
|
}; |
|
}; |
|
};
|
|
|