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174 lines
5.2 KiB
174 lines
5.2 KiB
*ST pin controller. |
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Each multi-function pin is controlled, driven and routed through the |
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PIO multiplexing block. Each pin supports GPIO functionality (ALT0) |
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and multiple alternate functions(ALT1 - ALTx) that directly connect |
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the pin to different hardware blocks. |
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When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and |
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Pull Up (PU) are driven by the related PIO block. |
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ST pinctrl driver controls PIO multiplexing block and also interacts with |
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gpio driver to configure a pin. |
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GPIO bank can have one of the two possible types of interrupt-wirings. |
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First type is via irqmux, single interrupt is used by multiple gpio banks. This |
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reduces number of overall interrupts numbers required. All these banks belong to |
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a single pincontroller. |
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_________ |
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| |----> [gpio-bank (n) ] |
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| |----> [gpio-bank (n + 1)] |
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[irqN]-- | irq-mux |----> [gpio-bank (n + 2)] |
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| |----> [gpio-bank (... )] |
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|_________|----> [gpio-bank (n + 7)] |
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Second type has a dedicated interrupt per gpio bank. |
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[irqN]----> [gpio-bank (n)] |
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Pin controller node: |
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Required properties: |
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- compatible : should be "st,stih407-<pio-block>-pinctrl" |
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- st,syscfg : Should be a phandle of the syscfg node. |
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- st,retime-pin-mask : Should be mask to specify which pins can be retimed. |
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If the property is not present, it is assumed that all the pins in the |
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bank are capable of retiming. Retiming is mainly used to improve the |
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IO timing margins of external synchronous interfaces. |
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- ranges : defines mapping between pin controller node (parent) to gpio-bank |
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node (children). |
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Optional properties: |
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- interrupts : Interrupt number of the irqmux. If the interrupt is shared |
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with other gpio banks via irqmux. |
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a irqline and gpio banks. |
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- reg : irqmux memory resource. If irqmux is present. |
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- reg-names : irqmux resource should be named as "irqmux". |
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GPIO controller/bank node. |
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Required properties: |
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- gpio-controller : Indicates this device is a GPIO controller |
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- #gpio-cells : Must be two. |
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- First cell: specifies the pin number inside the controller |
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- Second cell: specifies whether the pin is logically inverted. |
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- 0 = active high |
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- 1 = active low |
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- st,bank-name : Should be a name string for this bank as specified in |
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datasheet. |
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Optional properties: |
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- interrupts : Interrupt number for this gpio bank. If there is a dedicated |
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interrupt wired up for this gpio bank. |
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- interrupt-controller : Indicates this device is a interrupt controller. GPIO |
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bank can be an interrupt controller iff one of the interrupt type either via |
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irqmux or a dedicated interrupt per bank is specified. |
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- #interrupt-cells: the value of this property should be 2. |
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- First Cell: represents the external gpio interrupt number local to the |
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gpio interrupt space of the controller. |
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- Second Cell: flags to identify the type of the interrupt |
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- 1 = rising edge triggered |
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- 2 = falling edge triggered |
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- 3 = rising and falling edge triggered |
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- 4 = high level triggered |
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- 8 = low level triggered |
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for related macros look in: |
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include/dt-bindings/interrupt-controller/irq.h |
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Example: |
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pin-controller-sbc { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "st,stih407-sbc-pinctrl"; |
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st,syscfg = <&syscfg_sbc>; |
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reg = <0x0961f080 0x4>; |
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reg-names = "irqmux"; |
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interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>; |
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interrupt-names = "irqmux"; |
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ranges = <0 0x09610000 0x6000>; |
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pio0: gpio@9610000 { |
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gpio-controller; |
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#gpio-cells = <2>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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reg = <0x0 0x100>; |
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st,bank-name = "PIO0"; |
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}; |
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... |
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pin-functions nodes follow... |
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}; |
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Contents of function subnode node: |
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---------------------- |
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Required properties for pin configuration node: |
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- st,pins : Child node with list of pins with configuration. |
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Below is the format of how each pin conf should look like. |
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<bank offset mux mode rt_type rt_delay rt_clk> |
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Every PIO is represented with 4-7 parameters depending on retime configuration. |
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Each parameter is explained as below. |
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-bank : Should be bank phandle to which this PIO belongs. |
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-offset : Offset in the PIO bank. |
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-mux : Should be alternate function number associated this pin. |
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Use same numbers from datasheet. |
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-mode :pin configuration is selected from one of the below values. |
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IN |
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IN_PU |
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OUT |
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BIDIR |
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BIDIR_PU |
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-rt_type Retiming Configuration for the pin. |
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Possible retime configuration are: |
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------- ------------- |
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value args |
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------- ------------- |
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NICLK <delay> <clk> |
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ICLK_IO <delay> <clk> |
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BYPASS <delay> |
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DE_IO <delay> <clk> |
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SE_ICLK_IO <delay> <clk> |
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SE_NICLK_IO <delay> <clk> |
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- delay is retime delay in pico seconds as mentioned in data sheet. |
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- rt_clk :clk to be use for retime. |
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Possible values are: |
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CLK_A |
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CLK_B |
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CLK_C |
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CLK_D |
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Example of mmcclk pin which is a bi-direction pull pu with retime config |
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as non inverted clock retimed with CLK_B and delay of 0 pico seconds: |
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pin-controller { |
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... |
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mmc0 { |
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pinctrl_mmc: mmc { |
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st,pins { |
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mmcclk = <&PIO13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>; |
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... |
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}; |
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}; |
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... |
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}; |
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}; |
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sdhci0:sdhci@fe810000{ |
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... |
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interrupt-parent = <&pio3>; |
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#interrupt-cells = <2>; |
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interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; /* Interrupt line via PIO3-3 */ |
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interrupt-names = "card-detect"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_mmc>; |
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};
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