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210 lines
7.3 KiB
210 lines
7.3 KiB
Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY |
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------------------------------------------------- |
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Required properties: |
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- compatible : should be one of the listed compatibles: |
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- "samsung,s5pv210-mipi-video-phy" |
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- "samsung,exynos5420-mipi-video-phy" |
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- "samsung,exynos5433-mipi-video-phy" |
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- #phy-cells : from the generic phy bindings, must be 1; |
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In case of s5pv210 and exynos5420 compatible PHYs: |
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- syscon - phandle to the PMU system controller |
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In case of exynos5433 compatible PHY: |
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- samsung,pmu-syscon - phandle to the PMU system controller |
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- samsung,disp-sysreg - phandle to the DISP system registers controller |
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- samsung,cam0-sysreg - phandle to the CAM0 system registers controller |
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- samsung,cam1-sysreg - phandle to the CAM1 system registers controller |
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For "samsung,s5pv210-mipi-video-phy" compatible PHYs the second cell in |
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the PHY specifier identifies the PHY and its meaning is as follows: |
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0 - MIPI CSIS 0, |
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1 - MIPI DSIM 0, |
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2 - MIPI CSIS 1, |
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3 - MIPI DSIM 1. |
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"samsung,exynos5420-mipi-video-phy" and "samsung,exynos5433-mipi-video-phy" |
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supports additional fifth PHY: |
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4 - MIPI CSIS 2. |
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Samsung Exynos SoC series Display Port PHY |
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------------------------------------------------- |
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Required properties: |
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- compatible : should be one of the following supported values: |
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- "samsung,exynos5250-dp-video-phy" |
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- "samsung,exynos5420-dp-video-phy" |
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- samsung,pmu-syscon: phandle for PMU system controller interface, used to |
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control pmu registers for power isolation. |
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- #phy-cells : from the generic PHY bindings, must be 0; |
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Samsung S5P/Exynos SoC series USB PHY |
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------------------------------------------------- |
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Required properties: |
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- compatible : should be one of the listed compatibles: |
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- "samsung,exynos3250-usb2-phy" |
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- "samsung,exynos4210-usb2-phy" |
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- "samsung,exynos4x12-usb2-phy" |
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- "samsung,exynos5250-usb2-phy" |
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- "samsung,exynos5420-usb2-phy" |
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- "samsung,s5pv210-usb2-phy" |
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- reg : a list of registers used by phy driver |
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- first and obligatory is the location of phy modules registers |
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- samsung,sysreg-phandle - handle to syscon used to control the system registers |
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- samsung,pmureg-phandle - handle to syscon used to control PMU registers |
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- #phy-cells : from the generic phy bindings, must be 1; |
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- clocks and clock-names: |
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- the "phy" clock is required by the phy module, used as a gate |
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- the "ref" clock is used to get the rate of the clock provided to the |
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PHY module |
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Optional properties: |
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- vbus-supply: power-supply phandle for vbus power source |
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The first phandle argument in the PHY specifier identifies the PHY, its |
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meaning is compatible dependent. For the currently supported SoCs (Exynos 4210 |
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and Exynos 4212) it is as follows: |
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0 - USB device ("device"), |
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1 - USB host ("host"), |
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2 - HSIC0 ("hsic0"), |
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3 - HSIC1 ("hsic1"), |
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Exynos3250 has only USB device phy available as phy 0. |
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Exynos 4210 and Exynos 4212 use mode switching and require that mode switch |
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register is supplied. |
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Example: |
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For Exynos 4412 (compatible with Exynos 4212): |
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usbphy: phy@125b0000 { |
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compatible = "samsung,exynos4x12-usb2-phy"; |
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reg = <0x125b0000 0x100>; |
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clocks = <&clock 305>, <&clock 2>; |
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clock-names = "phy", "ref"; |
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#phy-cells = <1>; |
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samsung,sysreg-phandle = <&sys_reg>; |
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samsung,pmureg-phandle = <&pmu_reg>; |
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}; |
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Then the PHY can be used in other nodes such as: |
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phy-consumer@12340000 { |
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phys = <&usbphy 2>; |
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phy-names = "phy"; |
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}; |
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Refer to DT bindings documentation of particular PHY consumer devices for more |
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information about required PHYs and the way of specification. |
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Samsung SATA PHY Controller |
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--------------------------- |
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SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers. |
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Each SATA PHY controller should have its own node. |
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Required properties: |
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- compatible : compatible list, contains "samsung,exynos5250-sata-phy" |
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- reg : offset and length of the SATA PHY register set; |
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- #phy-cells : must be zero |
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- clocks : must be exactly one entry |
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- clock-names : must be "sata_phyctrl" |
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- samsung,exynos-sataphy-i2c-phandle : a phandle to the I2C device, no arguments |
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- samsung,syscon-phandle : a phandle to the PMU system controller, no arguments |
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Example: |
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sata_phy: sata-phy@12170000 { |
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compatible = "samsung,exynos5250-sata-phy"; |
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reg = <0x12170000 0x1ff>; |
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clocks = <&clock 287>; |
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clock-names = "sata_phyctrl"; |
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#phy-cells = <0>; |
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samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; |
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samsung,syscon-phandle = <&pmu_syscon>; |
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}; |
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Device-Tree bindings for sataphy i2c client driver |
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-------------------------------------------------- |
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Required properties: |
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compatible: Should be "samsung,exynos-sataphy-i2c" |
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- reg: I2C address of the sataphy i2c device. |
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Example: |
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sata_phy_i2c:sata-phy@38 { |
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compatible = "samsung,exynos-sataphy-i2c"; |
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reg = <0x38>; |
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}; |
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Samsung Exynos5 SoC series USB DRD PHY controller |
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-------------------------------------------------- |
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Required properties: |
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- compatible : Should be set to one of the following supported values: |
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- "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC, |
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- "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC. |
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- "samsung,exynos5433-usbdrd-phy" - for exynos5433 SoC. |
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- "samsung,exynos7-usbdrd-phy" - for exynos7 SoC. |
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- reg : Register offset and length of USB DRD PHY register set; |
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- clocks: Clock IDs array as required by the controller |
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- clock-names: names of clocks correseponding to IDs in the clock property; |
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Required clocks: |
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- phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), |
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used for register access. |
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- ref: PHY's reference clock (usually crystal clock), used for |
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PHY operations, associated by phy name. It is used to |
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determine bit values for clock settings register. |
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For Exynos5420 this is given as 'sclk_usbphy30' in CMU. |
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- optional clocks: Exynos5433 & Exynos7 SoC has now following additional |
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gate clocks available: |
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- phy_pipe: for PIPE3 phy |
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- phy_utmi: for UTMI+ phy |
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- itp: for ITP generation |
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- samsung,pmu-syscon: phandle for PMU system controller interface, used to |
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control pmu registers for power isolation. |
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- #phy-cells : from the generic PHY bindings, must be 1; |
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For "samsung,exynos5250-usbdrd-phy" and "samsung,exynos5420-usbdrd-phy" |
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compatible PHYs, the second cell in the PHY specifier identifies the |
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PHY id, which is interpreted as follows: |
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0 - UTMI+ type phy, |
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1 - PIPE3 type phy, |
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Example: |
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usbdrd_phy: usbphy@12100000 { |
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compatible = "samsung,exynos5250-usbdrd-phy"; |
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reg = <0x12100000 0x100>; |
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clocks = <&clock 286>, <&clock 1>; |
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clock-names = "phy", "ref"; |
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samsung,pmu-syscon = <&pmu_system_controller>; |
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#phy-cells = <1>; |
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}; |
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- aliases: For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers, |
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'usbdrd_phy' nodes should have numbered alias in the aliases node, |
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in the form of usbdrdphyN, N = 0, 1... (depending on number of |
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controllers). |
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Example: |
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aliases { |
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usbdrdphy0 = &usb3_phy0; |
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usbdrdphy1 = &usb3_phy1; |
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}; |
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Samsung Exynos SoC series PCIe PHY controller |
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-------------------------------------------------- |
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Required properties: |
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- compatible : Should be set to "samsung,exynos5440-pcie-phy" |
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- #phy-cells : Must be zero |
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- reg : a register used by phy driver. |
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- First is for phy register, second is for block register. |
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- reg-names : Must be set to "phy" and "block". |
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Example: |
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pcie_phy0: pcie-phy@270000 { |
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#phy-cells = <0>; |
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compatible = "samsung,exynos5440-pcie-phy"; |
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reg = <0x270000 0x1000>, <0x271000 0x40>; |
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reg-names = "phy", "block"; |
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};
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