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502 lines
13 KiB
502 lines
13 KiB
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#" |
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$schema: "http://devicetree.org/meta-schemas/core.yaml#" |
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title: Qualcomm QMP PHY controller |
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maintainers: |
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- Vinod Koul <[email protected]> |
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description: |
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QMP phy controller supports physical layer functionality for a number of |
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controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. |
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properties: |
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compatible: |
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enum: |
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- qcom,ipq6018-qmp-pcie-phy |
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- qcom,ipq6018-qmp-usb3-phy |
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- qcom,ipq8074-qmp-gen3-pcie-phy |
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- qcom,ipq8074-qmp-pcie-phy |
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- qcom,ipq8074-qmp-usb3-phy |
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- qcom,msm8996-qmp-pcie-phy |
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- qcom,msm8996-qmp-ufs-phy |
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- qcom,msm8996-qmp-usb3-phy |
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- qcom,msm8998-qmp-pcie-phy |
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- qcom,msm8998-qmp-ufs-phy |
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- qcom,msm8998-qmp-usb3-phy |
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- qcom,qcm2290-qmp-usb3-phy |
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- qcom,sc7180-qmp-usb3-phy |
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- qcom,sc8180x-qmp-pcie-phy |
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- qcom,sc8180x-qmp-ufs-phy |
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- qcom,sc8180x-qmp-usb3-phy |
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- qcom,sc8280xp-qmp-ufs-phy |
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- qcom,sdm845-qhp-pcie-phy |
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- qcom,sdm845-qmp-pcie-phy |
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- qcom,sdm845-qmp-ufs-phy |
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- qcom,sdm845-qmp-usb3-phy |
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- qcom,sdm845-qmp-usb3-uni-phy |
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- qcom,sm6115-qmp-ufs-phy |
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- qcom,sm6350-qmp-ufs-phy |
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- qcom,sm8150-qmp-ufs-phy |
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- qcom,sm8150-qmp-usb3-phy |
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- qcom,sm8150-qmp-usb3-uni-phy |
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- qcom,sm8250-qmp-ufs-phy |
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- qcom,sm8250-qmp-gen3x1-pcie-phy |
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- qcom,sm8250-qmp-gen3x2-pcie-phy |
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- qcom,sm8250-qmp-modem-pcie-phy |
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- qcom,sm8250-qmp-usb3-phy |
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- qcom,sm8250-qmp-usb3-uni-phy |
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- qcom,sm8350-qmp-ufs-phy |
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- qcom,sm8350-qmp-usb3-phy |
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- qcom,sm8350-qmp-usb3-uni-phy |
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- qcom,sm8450-qmp-gen3x1-pcie-phy |
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- qcom,sm8450-qmp-gen4x2-pcie-phy |
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- qcom,sm8450-qmp-ufs-phy |
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- qcom,sm8450-qmp-usb3-phy |
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- qcom,sdx55-qmp-pcie-phy |
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- qcom,sdx55-qmp-usb3-uni-phy |
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- qcom,sdx65-qmp-usb3-uni-phy |
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reg: |
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minItems: 1 |
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items: |
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- description: Address and length of PHY's common serdes block. |
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- description: Address and length of PHY's DP_COM control block. |
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"#clock-cells": |
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enum: [ 1, 2 ] |
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"#address-cells": |
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enum: [ 1, 2 ] |
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"#size-cells": |
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enum: [ 1, 2 ] |
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ranges: true |
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clocks: |
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minItems: 1 |
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maxItems: 4 |
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clock-names: |
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minItems: 1 |
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maxItems: 4 |
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resets: |
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minItems: 1 |
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maxItems: 3 |
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reset-names: |
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minItems: 1 |
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maxItems: 3 |
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vdda-phy-supply: |
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description: |
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Phandle to a regulator supply to PHY core block. |
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vdda-pll-supply: |
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description: |
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Phandle to 1.8V regulator supply to PHY refclk pll block. |
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vddp-ref-clk-supply: |
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description: |
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Phandle to a regulator supply to any specific refclk pll block. |
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#Required nodes: |
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patternProperties: |
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"^phy@[0-9a-f]+$": |
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type: object |
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description: |
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Each device node of QMP phy is required to have as many child nodes as |
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the number of lanes the PHY has. |
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required: |
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- compatible |
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- reg |
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- "#clock-cells" |
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- "#address-cells" |
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- "#size-cells" |
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- ranges |
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- clocks |
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- clock-names |
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- resets |
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- reset-names |
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additionalProperties: false |
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allOf: |
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- if: |
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properties: |
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compatible: |
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contains: |
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enum: |
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- qcom,sdm845-qmp-usb3-uni-phy |
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then: |
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properties: |
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clocks: |
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items: |
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- description: Phy aux clock. |
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- description: Phy config clock. |
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- description: 19.2 MHz ref clk. |
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- description: Phy common block aux clock. |
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clock-names: |
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items: |
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- const: aux |
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- const: cfg_ahb |
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- const: ref |
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- const: com_aux |
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resets: |
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items: |
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- description: reset of phy block. |
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- description: phy common block reset. |
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reset-names: |
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items: |
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- const: phy |
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- const: common |
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required: |
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- vdda-phy-supply |
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- vdda-pll-supply |
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- if: |
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properties: |
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compatible: |
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contains: |
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enum: |
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- qcom,sdx55-qmp-usb3-uni-phy |
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- qcom,sdx65-qmp-usb3-uni-phy |
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then: |
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properties: |
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clocks: |
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items: |
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- description: Phy aux clock. |
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- description: Phy config clock. |
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- description: 19.2 MHz ref clk. |
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clock-names: |
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items: |
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- const: aux |
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- const: cfg_ahb |
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- const: ref |
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resets: |
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items: |
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- description: reset of phy block. |
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- description: phy common block reset. |
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reset-names: |
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items: |
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- const: phy |
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- const: common |
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required: |
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- vdda-phy-supply |
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- vdda-pll-supply |
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- if: |
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properties: |
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compatible: |
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contains: |
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enum: |
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- qcom,msm8996-qmp-pcie-phy |
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then: |
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properties: |
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clocks: |
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items: |
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- description: Phy aux clock. |
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- description: Phy config clock. |
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- description: 19.2 MHz ref clk. |
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clock-names: |
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items: |
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- const: aux |
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- const: cfg_ahb |
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- const: ref |
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resets: |
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items: |
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- description: reset of phy block. |
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- description: phy common block reset. |
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- description: phy's ahb cfg block reset. |
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reset-names: |
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items: |
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- const: phy |
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- const: common |
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- const: cfg |
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required: |
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- vdda-phy-supply |
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- vdda-pll-supply |
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- if: |
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properties: |
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compatible: |
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contains: |
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enum: |
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- qcom,ipq8074-qmp-usb3-phy |
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- qcom,msm8996-qmp-usb3-phy |
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- qcom,msm8998-qmp-pcie-phy |
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- qcom,msm8998-qmp-usb3-phy |
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then: |
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properties: |
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clocks: |
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items: |
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- description: Phy aux clock. |
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- description: Phy config clock. |
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- description: 19.2 MHz ref clk. |
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clock-names: |
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items: |
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- const: aux |
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- const: cfg_ahb |
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- const: ref |
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resets: |
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items: |
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- description: reset of phy block. |
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- description: phy common block reset. |
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reset-names: |
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items: |
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- const: phy |
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- const: common |
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required: |
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- vdda-phy-supply |
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- vdda-pll-supply |
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- if: |
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properties: |
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compatible: |
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contains: |
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enum: |
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- qcom,msm8996-qmp-ufs-phy |
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then: |
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properties: |
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clocks: |
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items: |
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- description: 19.2 MHz ref clk. |
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clock-names: |
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items: |
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- const: ref |
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resets: |
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items: |
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- description: PHY reset in the UFS controller. |
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reset-names: |
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items: |
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- const: ufsphy |
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required: |
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- vdda-phy-supply |
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- vdda-pll-supply |
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- if: |
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properties: |
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compatible: |
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contains: |
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enum: |
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- qcom,msm8998-qmp-ufs-phy |
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- qcom,sdm845-qmp-ufs-phy |
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- qcom,sm6350-qmp-ufs-phy |
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- qcom,sm8150-qmp-ufs-phy |
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- qcom,sm8250-qmp-ufs-phy |
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- qcom,sc8180x-qmp-ufs-phy |
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- qcom,sc8280xp-qmp-ufs-phy |
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then: |
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properties: |
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clocks: |
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items: |
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- description: 19.2 MHz ref clk. |
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- description: Phy reference aux clock. |
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clock-names: |
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items: |
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- const: ref |
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- const: ref_aux |
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resets: |
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items: |
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- description: PHY reset in the UFS controller. |
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reset-names: |
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items: |
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- const: ufsphy |
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required: |
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- vdda-phy-supply |
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- vdda-pll-supply |
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- if: |
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properties: |
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compatible: |
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contains: |
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enum: |
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- qcom,ipq6018-qmp-pcie-phy |
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- qcom,ipq8074-qmp-gen3-pcie-phy |
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- qcom,ipq8074-qmp-pcie-phy |
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then: |
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properties: |
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clocks: |
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items: |
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- description: Phy aux clock. |
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- description: Phy config clock. |
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clock-names: |
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items: |
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- const: aux |
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- const: cfg_ahb |
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resets: |
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items: |
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- description: reset of phy block. |
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- description: phy common block reset. |
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reset-names: |
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items: |
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- const: phy |
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- const: common |
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- if: |
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properties: |
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compatible: |
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contains: |
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enum: |
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- qcom,sc8180x-qmp-pcie-phy |
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- qcom,sdm845-qhp-pcie-phy |
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- qcom,sdm845-qmp-pcie-phy |
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- qcom,sdx55-qmp-pcie-phy |
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- qcom,sm8250-qmp-gen3x1-pcie-phy |
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- qcom,sm8250-qmp-gen3x2-pcie-phy |
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- qcom,sm8250-qmp-modem-pcie-phy |
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- qcom,sm8450-qmp-gen3x1-pcie-phy |
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- qcom,sm8450-qmp-gen4x2-pcie-phy |
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then: |
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properties: |
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clocks: |
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items: |
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- description: Phy aux clock. |
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- description: Phy config clock. |
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- description: 19.2 MHz ref clk. |
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- description: Phy refgen clk. |
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clock-names: |
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items: |
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- const: aux |
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- const: cfg_ahb |
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- const: ref |
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- const: refgen |
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resets: |
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items: |
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- description: reset of phy block. |
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reset-names: |
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items: |
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- const: phy |
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required: |
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- vdda-phy-supply |
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- vdda-pll-supply |
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- if: |
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properties: |
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compatible: |
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contains: |
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enum: |
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- qcom,sm8150-qmp-usb3-phy |
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- qcom,sm8150-qmp-usb3-uni-phy |
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- qcom,sm8250-qmp-usb3-uni-phy |
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- qcom,sm8350-qmp-usb3-uni-phy |
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then: |
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properties: |
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clocks: |
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items: |
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- description: Phy aux clock. |
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- description: 19.2 MHz ref clk source. |
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- description: 19.2 MHz ref clk. |
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- description: Phy common block aux clock. |
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clock-names: |
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items: |
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- const: aux |
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- const: ref_clk_src |
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- const: ref |
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- const: com_aux |
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resets: |
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items: |
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- description: reset of phy block. |
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- description: phy common block reset. |
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reset-names: |
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items: |
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- const: phy |
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- const: common |
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required: |
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- vdda-phy-supply |
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- vdda-pll-supply |
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- if: |
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properties: |
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compatible: |
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contains: |
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enum: |
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- qcom,sm8250-qmp-usb3-phy |
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- qcom,sm8350-qmp-usb3-phy |
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then: |
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properties: |
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clocks: |
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items: |
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- description: Phy aux clock. |
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- description: 19.2 MHz ref clk. |
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- description: Phy common block aux clock. |
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clock-names: |
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items: |
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- const: aux |
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- const: ref_clk_src |
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- const: com_aux |
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resets: |
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items: |
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- description: reset of phy block. |
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- description: phy common block reset. |
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reset-names: |
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items: |
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- const: phy |
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- const: common |
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required: |
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- vdda-phy-supply |
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- vdda-pll-supply |
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- if: |
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properties: |
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compatible: |
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contains: |
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enum: |
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- qcom,qcm2290-qmp-usb3-phy |
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then: |
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properties: |
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clocks: |
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items: |
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- description: Phy config clock. |
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- description: 19.2 MHz ref clk. |
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- description: Phy common block aux clock. |
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clock-names: |
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items: |
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- const: cfg_ahb |
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- const: ref |
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- const: com_aux |
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resets: |
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items: |
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- description: phy_phy reset. |
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- description: reset of phy block. |
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reset-names: |
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items: |
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- const: phy_phy |
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- const: phy |
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required: |
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- vdda-phy-supply |
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- vdda-pll-supply |
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examples: |
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- | |
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#include <dt-bindings/clock/qcom,gcc-sdm845.h> |
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usb_2_qmpphy: phy-wrapper@88eb000 { |
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compatible = "qcom,sdm845-qmp-usb3-uni-phy"; |
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reg = <0x088eb000 0x18c>; |
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#clock-cells = <1>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0x0 0x088eb000 0x2000>; |
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clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >, |
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<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, |
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<&gcc GCC_USB3_SEC_CLKREF_CLK>, |
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<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; |
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clock-names = "aux", "cfg_ahb", "ref", "com_aux"; |
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resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, |
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<&gcc GCC_USB3_PHY_SEC_BCR>; |
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reset-names = "phy", "common"; |
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vdda-phy-supply = <&vdda_usb2_ss_1p2>; |
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vdda-pll-supply = <&vdda_usb2_ss_core>; |
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usb_2_ssphy: phy@200 { |
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reg = <0x200 0x128>, |
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<0x400 0x1fc>, |
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<0x800 0x218>, |
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<0x600 0x70>; |
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#clock-cells = <0>; |
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#phy-cells = <0>; |
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clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; |
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clock-names = "pipe0"; |
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clock-output-names = "usb3_uni_phy_pipe_clk_src"; |
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}; |
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};
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