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173 lines
5.6 KiB
173 lines
5.6 KiB
Marvell Xenon SDHCI Controller device tree bindings |
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This file documents differences between the core mmc properties |
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described by mmc.txt and the properties used by the Xenon implementation. |
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Multiple SDHCs might be put into a single Xenon IP, to save size and cost. |
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Each SDHC is independent and owns independent resources, such as register sets, |
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clock and PHY. |
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Each SDHC should have an independent device tree node. |
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Required Properties: |
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- compatible: should be one of the following |
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- "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC. |
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Must provide a second register area and marvell,pad-type. |
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- "marvell,armada-ap806-sdhci": For controllers on Armada AP806. |
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- "marvell,armada-ap807-sdhci": For controllers on Armada AP807. |
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- "marvell,armada-cp110-sdhci": For controllers on Armada CP110. |
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- clocks: |
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Array of clocks required for SDHC. |
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Require at least input clock for Xenon IP core. For Armada AP806 and |
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CP110, the AXI clock is also mandatory. |
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- clock-names: |
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Array of names corresponding to clocks property. |
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The input clock for Xenon IP core should be named as "core". |
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The input clock for the AXI bus must be named as "axi". |
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- reg: |
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* For "marvell,armada-3700-sdhci", two register areas. |
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The first one for Xenon IP register. The second one for the Armada 3700 SoC |
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PHY PAD Voltage Control register. |
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Please follow the examples with compatible "marvell,armada-3700-sdhci" |
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in below. |
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Please also check property marvell,pad-type in below. |
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* For other compatible strings, one register area for Xenon IP. |
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Optional Properties: |
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- marvell,xenon-sdhc-id: |
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Indicate the corresponding bit index of current SDHC in |
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SDHC System Operation Control Register Bit[7:0]. |
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Set/clear the corresponding bit to enable/disable current SDHC. |
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If Xenon IP contains only one SDHC, this property is optional. |
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- marvell,xenon-phy-type: |
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Xenon support multiple types of PHYs. |
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To select eMMC 5.1 PHY, set: |
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marvell,xenon-phy-type = "emmc 5.1 phy" |
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eMMC 5.1 PHY is the default choice if this property is not provided. |
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To select eMMC 5.0 PHY, set: |
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marvell,xenon-phy-type = "emmc 5.0 phy" |
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All those types of PHYs can support eMMC, SD and SDIO. |
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Please note that this property only presents the type of PHY. |
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It doesn't stand for the entire SDHC type or property. |
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For example, "emmc 5.1 phy" doesn't mean that this Xenon SDHC only |
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supports eMMC 5.1. |
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- marvell,xenon-phy-znr: |
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Set PHY ZNR value. |
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Only available for eMMC PHY. |
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Valid range = [0:0x1F]. |
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ZNR is set as 0xF by default if this property is not provided. |
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- marvell,xenon-phy-zpr: |
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Set PHY ZPR value. |
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Only available for eMMC PHY. |
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Valid range = [0:0x1F]. |
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ZPR is set as 0xF by default if this property is not provided. |
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- marvell,xenon-phy-nr-success-tun: |
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Set the number of required consecutive successful sampling points |
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used to identify a valid sampling window, in tuning process. |
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Valid range = [1:7]. |
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Set as 0x4 by default if this property is not provided. |
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- marvell,xenon-phy-tun-step-divider: |
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Set the divider for calculating TUN_STEP. |
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Set as 64 by default if this property is not provided. |
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- marvell,xenon-phy-slow-mode: |
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If this property is selected, transfers will bypass PHY. |
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Only available when bus frequency lower than 55MHz in SDR mode. |
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Disabled by default. Please only try this property if timing issues |
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always occur with PHY enabled in eMMC HS SDR, SD SDR12, SD SDR25, |
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SD Default Speed and HS mode and eMMC legacy speed mode. |
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- marvell,xenon-tun-count: |
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Xenon SDHC SoC usually doesn't provide re-tuning counter in |
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Capabilities Register 3 Bit[11:8]. |
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This property provides the re-tuning counter. |
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If this property is not set, default re-tuning counter will |
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be set as 0x9 in driver. |
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- marvell,pad-type: |
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Type of Armada 3700 SoC PHY PAD Voltage Controller register. |
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Only valid when "marvell,armada-3700-sdhci" is selected. |
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Two types: "sd" and "fixed-1-8v". |
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If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning and is |
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switched to 1.8V when later in higher speed mode. |
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If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for eMMC. |
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Please follow the examples with compatible "marvell,armada-3700-sdhci" |
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in below. |
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Example: |
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- For eMMC: |
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sdhci@aa0000 { |
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compatible = "marvell,armada-ap806-sdhci"; |
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reg = <0xaa0000 0x1000>; |
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH> |
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clocks = <&emmc_clk>,<&axi_clk>; |
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clock-names = "core", "axi"; |
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bus-width = <4>; |
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marvell,xenon-phy-slow-mode; |
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marvell,xenon-tun-count = <11>; |
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non-removable; |
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no-sd; |
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no-sdio; |
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/* Vmmc and Vqmmc are both fixed */ |
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}; |
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- For SD/SDIO: |
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sdhci@ab0000 { |
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compatible = "marvell,armada-cp110-sdhci"; |
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reg = <0xab0000 0x1000>; |
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH> |
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vqmmc-supply = <&sd_vqmmc_regulator>; |
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vmmc-supply = <&sd_vmmc_regulator>; |
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clocks = <&sdclk>, <&axi_clk>; |
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clock-names = "core", "axi"; |
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bus-width = <4>; |
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marvell,xenon-tun-count = <9>; |
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}; |
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- For eMMC with compatible "marvell,armada-3700-sdhci": |
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sdhci@aa0000 { |
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compatible = "marvell,armada-3700-sdhci"; |
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reg = <0xaa0000 0x1000>, |
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<phy_addr 0x4>; |
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH> |
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clocks = <&emmcclk>; |
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clock-names = "core"; |
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bus-width = <8>; |
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mmc-ddr-1_8v; |
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mmc-hs400-1_8v; |
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non-removable; |
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no-sd; |
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no-sdio; |
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/* Vmmc and Vqmmc are both fixed */ |
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marvell,pad-type = "fixed-1-8v"; |
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}; |
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- For SD/SDIO with compatible "marvell,armada-3700-sdhci": |
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sdhci@ab0000 { |
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compatible = "marvell,armada-3700-sdhci"; |
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reg = <0xab0000 0x1000>, |
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<phy_addr 0x4>; |
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH> |
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vqmmc-supply = <&sd_regulator>; |
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/* Vmmc is fixed */ |
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clocks = <&sdclk>; |
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clock-names = "core"; |
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bus-width = <4>; |
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marvell,pad-type = "sd"; |
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};
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