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172 lines
5.3 KiB
172 lines
5.3 KiB
# SPDX-License-Identifier: (GPL-2.0) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: NVIDIA Tegra30 SoC Memory Controller |
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maintainers: |
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- Dmitry Osipenko <[email protected]> |
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- Jon Hunter <[email protected]> |
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- Thierry Reding <[email protected]> |
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description: | |
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Tegra30 Memory Controller architecturally consists of the following parts: |
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Arbitration Domains, which can handle a single request or response per |
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clock from a group of clients. Typically, a system has a single Arbitration |
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Domain, but an implementation may divide the client space into multiple |
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Arbitration Domains to increase the effective system bandwidth. |
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Protocol Arbiter, which manage a related pool of memory devices. A system |
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may have a single Protocol Arbiter or multiple Protocol Arbiters. |
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Memory Crossbar, which routes request and responses between Arbitration |
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Domains and Protocol Arbiters. In the simplest version of the system, the |
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Memory Crossbar is just a pass through between a single Arbitration Domain |
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and a single Protocol Arbiter. |
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Global Resources, which include things like configuration registers which |
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are shared across the Memory Subsystem. |
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The Tegra30 Memory Controller handles memory requests from internal clients |
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and arbitrates among them to allocate memory bandwidth for DDR3L and LPDDR2 |
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SDRAMs. |
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properties: |
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compatible: |
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const: nvidia,tegra30-mc |
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reg: |
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maxItems: 1 |
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clocks: |
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maxItems: 1 |
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clock-names: |
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items: |
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- const: mc |
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interrupts: |
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maxItems: 1 |
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"#reset-cells": |
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const: 1 |
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"#iommu-cells": |
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const: 1 |
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"#interconnect-cells": |
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const: 1 |
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patternProperties: |
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"^emc-timings-[0-9]+$": |
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type: object |
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properties: |
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nvidia,ram-code: |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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description: |
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Value of RAM_CODE this timing set is used for. |
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patternProperties: |
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"^timing-[0-9]+$": |
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type: object |
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properties: |
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clock-frequency: |
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description: |
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Memory clock rate in Hz. |
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minimum: 1000000 |
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maximum: 900000000 |
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nvidia,emem-configuration: |
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$ref: /schemas/types.yaml#/definitions/uint32-array |
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description: | |
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Values to be written to the EMEM register block. See section |
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"18.13.1 MC Registers" in the TRM. |
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items: |
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- description: MC_EMEM_ARB_CFG |
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- description: MC_EMEM_ARB_OUTSTANDING_REQ |
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- description: MC_EMEM_ARB_TIMING_RCD |
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- description: MC_EMEM_ARB_TIMING_RP |
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- description: MC_EMEM_ARB_TIMING_RC |
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- description: MC_EMEM_ARB_TIMING_RAS |
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- description: MC_EMEM_ARB_TIMING_FAW |
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- description: MC_EMEM_ARB_TIMING_RRD |
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- description: MC_EMEM_ARB_TIMING_RAP2PRE |
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- description: MC_EMEM_ARB_TIMING_WAP2PRE |
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- description: MC_EMEM_ARB_TIMING_R2R |
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- description: MC_EMEM_ARB_TIMING_W2W |
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- description: MC_EMEM_ARB_TIMING_R2W |
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- description: MC_EMEM_ARB_TIMING_W2R |
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- description: MC_EMEM_ARB_DA_TURNS |
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- description: MC_EMEM_ARB_DA_COVERS |
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- description: MC_EMEM_ARB_MISC0 |
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- description: MC_EMEM_ARB_RING1_THROTTLE |
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required: |
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- clock-frequency |
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- nvidia,emem-configuration |
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additionalProperties: false |
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required: |
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- nvidia,ram-code |
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additionalProperties: false |
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required: |
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- compatible |
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- reg |
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- interrupts |
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- clocks |
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- clock-names |
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- "#reset-cells" |
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- "#iommu-cells" |
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- "#interconnect-cells" |
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additionalProperties: false |
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examples: |
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- | |
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memory-controller@7000f000 { |
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compatible = "nvidia,tegra30-mc"; |
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reg = <0x7000f000 0x400>; |
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clocks = <&tegra_car 32>; |
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clock-names = "mc"; |
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interrupts = <0 77 4>; |
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#iommu-cells = <1>; |
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#reset-cells = <1>; |
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#interconnect-cells = <1>; |
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emc-timings-1 { |
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nvidia,ram-code = <1>; |
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timing-667000000 { |
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clock-frequency = <667000000>; |
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nvidia,emem-configuration = < |
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0x0000000a /* MC_EMEM_ARB_CFG */ |
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0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */ |
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0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ |
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0x00000004 /* MC_EMEM_ARB_TIMING_RP */ |
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0x00000010 /* MC_EMEM_ARB_TIMING_RC */ |
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0x0000000b /* MC_EMEM_ARB_TIMING_RAS */ |
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0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ |
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0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ |
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0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ |
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0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ |
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0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ |
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0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ |
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0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ |
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0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ |
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0x08040202 /* MC_EMEM_ARB_DA_TURNS */ |
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0x00130b10 /* MC_EMEM_ARB_DA_COVERS */ |
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0x70ea1f11 /* MC_EMEM_ARB_MISC0 */ |
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0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ |
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>; |
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}; |
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}; |
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};
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