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355 lines
13 KiB
355 lines
13 KiB
# SPDX-License-Identifier: (GPL-2.0) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: NVIDIA Tegra30 SoC External Memory Controller |
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maintainers: |
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- Dmitry Osipenko <[email protected]> |
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- Jon Hunter <[email protected]> |
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- Thierry Reding <[email protected]> |
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description: | |
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The EMC interfaces with the off-chip SDRAM to service the request stream |
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sent from Memory Controller. The EMC also has various performance-affecting |
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settings beyond the obvious SDRAM configuration parameters and initialization |
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settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2, |
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LPDDR3, and DDR3. |
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properties: |
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compatible: |
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const: nvidia,tegra30-emc |
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reg: |
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maxItems: 1 |
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clocks: |
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maxItems: 1 |
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interrupts: |
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maxItems: 1 |
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"#interconnect-cells": |
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const: 0 |
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nvidia,memory-controller: |
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$ref: /schemas/types.yaml#/definitions/phandle |
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description: |
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Phandle of the Memory Controller node. |
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power-domains: |
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maxItems: 1 |
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description: |
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Phandle of the SoC "core" power domain. |
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operating-points-v2: |
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description: |
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Should contain freqs and voltages and opp-supported-hw property, which |
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is a bitfield indicating SoC speedo ID mask. |
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patternProperties: |
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"^emc-timings-[0-9]+$": |
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type: object |
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properties: |
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nvidia,ram-code: |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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description: |
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Value of RAM_CODE this timing set is used for. |
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patternProperties: |
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"^timing-[0-9]+$": |
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type: object |
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properties: |
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clock-frequency: |
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description: |
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Memory clock rate in Hz. |
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minimum: 1000000 |
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maximum: 900000000 |
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nvidia,emc-auto-cal-interval: |
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description: |
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Pad calibration interval in microseconds. |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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minimum: 0 |
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maximum: 2097151 |
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nvidia,emc-mode-1: |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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description: |
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Mode Register 1. |
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nvidia,emc-mode-2: |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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description: |
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Mode Register 2. |
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nvidia,emc-mode-reset: |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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description: |
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Mode Register 0. |
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nvidia,emc-zcal-cnt-long: |
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description: |
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Number of EMC clocks to wait before issuing any commands after |
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sending ZCAL_MRW_CMD. |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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minimum: 0 |
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maximum: 1023 |
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nvidia,emc-cfg-dyn-self-ref: |
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type: boolean |
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description: |
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Dynamic self-refresh enabled. |
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nvidia,emc-cfg-periodic-qrst: |
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type: boolean |
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description: |
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FBIO "read" FIFO periodic resetting enabled. |
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nvidia,emc-configuration: |
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description: |
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EMC timing characterization data. These are the registers |
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(see section "18.13.2 EMC Registers" in the TRM) whose values |
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need to be specified, according to the board documentation. |
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$ref: /schemas/types.yaml#/definitions/uint32-array |
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items: |
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- description: EMC_RC |
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- description: EMC_RFC |
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- description: EMC_RAS |
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- description: EMC_RP |
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- description: EMC_R2W |
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- description: EMC_W2R |
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- description: EMC_R2P |
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- description: EMC_W2P |
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- description: EMC_RD_RCD |
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- description: EMC_WR_RCD |
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- description: EMC_RRD |
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- description: EMC_REXT |
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- description: EMC_WEXT |
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- description: EMC_WDV |
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- description: EMC_QUSE |
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- description: EMC_QRST |
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- description: EMC_QSAFE |
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- description: EMC_RDV |
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- description: EMC_REFRESH |
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- description: EMC_BURST_REFRESH_NUM |
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- description: EMC_PRE_REFRESH_REQ_CNT |
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- description: EMC_PDEX2WR |
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- description: EMC_PDEX2RD |
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- description: EMC_PCHG2PDEN |
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- description: EMC_ACT2PDEN |
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- description: EMC_AR2PDEN |
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- description: EMC_RW2PDEN |
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- description: EMC_TXSR |
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- description: EMC_TXSRDLL |
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- description: EMC_TCKE |
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- description: EMC_TFAW |
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- description: EMC_TRPAB |
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- description: EMC_TCLKSTABLE |
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- description: EMC_TCLKSTOP |
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- description: EMC_TREFBW |
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- description: EMC_QUSE_EXTRA |
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- description: EMC_FBIO_CFG6 |
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- description: EMC_ODT_WRITE |
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- description: EMC_ODT_READ |
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- description: EMC_FBIO_CFG5 |
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- description: EMC_CFG_DIG_DLL |
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- description: EMC_CFG_DIG_DLL_PERIOD |
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- description: EMC_DLL_XFORM_DQS0 |
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- description: EMC_DLL_XFORM_DQS1 |
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- description: EMC_DLL_XFORM_DQS2 |
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- description: EMC_DLL_XFORM_DQS3 |
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- description: EMC_DLL_XFORM_DQS4 |
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- description: EMC_DLL_XFORM_DQS5 |
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- description: EMC_DLL_XFORM_DQS6 |
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- description: EMC_DLL_XFORM_DQS7 |
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- description: EMC_DLL_XFORM_QUSE0 |
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- description: EMC_DLL_XFORM_QUSE1 |
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- description: EMC_DLL_XFORM_QUSE2 |
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- description: EMC_DLL_XFORM_QUSE3 |
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- description: EMC_DLL_XFORM_QUSE4 |
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- description: EMC_DLL_XFORM_QUSE5 |
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- description: EMC_DLL_XFORM_QUSE6 |
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- description: EMC_DLL_XFORM_QUSE7 |
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- description: EMC_DLI_TRIM_TXDQS0 |
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- description: EMC_DLI_TRIM_TXDQS1 |
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- description: EMC_DLI_TRIM_TXDQS2 |
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- description: EMC_DLI_TRIM_TXDQS3 |
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- description: EMC_DLI_TRIM_TXDQS4 |
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- description: EMC_DLI_TRIM_TXDQS5 |
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- description: EMC_DLI_TRIM_TXDQS6 |
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- description: EMC_DLI_TRIM_TXDQS7 |
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- description: EMC_DLL_XFORM_DQ0 |
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- description: EMC_DLL_XFORM_DQ1 |
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- description: EMC_DLL_XFORM_DQ2 |
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- description: EMC_DLL_XFORM_DQ3 |
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- description: EMC_XM2CMDPADCTRL |
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- description: EMC_XM2DQSPADCTRL2 |
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- description: EMC_XM2DQPADCTRL2 |
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- description: EMC_XM2CLKPADCTRL |
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- description: EMC_XM2COMPPADCTRL |
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- description: EMC_XM2VTTGENPADCTRL |
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- description: EMC_XM2VTTGENPADCTRL2 |
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- description: EMC_XM2QUSEPADCTRL |
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- description: EMC_XM2DQSPADCTRL3 |
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- description: EMC_CTT_TERM_CTRL |
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- description: EMC_ZCAL_INTERVAL |
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- description: EMC_ZCAL_WAIT_CNT |
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- description: EMC_MRS_WAIT_CNT |
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- description: EMC_AUTO_CAL_CONFIG |
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- description: EMC_CTT |
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- description: EMC_CTT_DURATION |
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- description: EMC_DYN_SELF_REF_CONTROL |
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- description: EMC_FBIO_SPARE |
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- description: EMC_CFG_RSV |
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required: |
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- clock-frequency |
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- nvidia,emc-auto-cal-interval |
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- nvidia,emc-mode-1 |
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- nvidia,emc-mode-2 |
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- nvidia,emc-mode-reset |
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- nvidia,emc-zcal-cnt-long |
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- nvidia,emc-configuration |
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additionalProperties: false |
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required: |
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- nvidia,ram-code |
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additionalProperties: false |
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required: |
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- compatible |
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- reg |
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- interrupts |
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- clocks |
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- nvidia,memory-controller |
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- "#interconnect-cells" |
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- operating-points-v2 |
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additionalProperties: false |
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examples: |
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- | |
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external-memory-controller@7000f400 { |
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compatible = "nvidia,tegra30-emc"; |
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reg = <0x7000f400 0x400>; |
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interrupts = <0 78 4>; |
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clocks = <&tegra_car 57>; |
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nvidia,memory-controller = <&mc>; |
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operating-points-v2 = <&dvfs_opp_table>; |
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power-domains = <&domain>; |
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#interconnect-cells = <0>; |
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emc-timings-1 { |
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nvidia,ram-code = <1>; |
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timing-667000000 { |
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clock-frequency = <667000000>; |
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nvidia,emc-auto-cal-interval = <0x001fffff>; |
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nvidia,emc-mode-1 = <0x80100002>; |
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nvidia,emc-mode-2 = <0x80200018>; |
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nvidia,emc-mode-reset = <0x80000b71>; |
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nvidia,emc-zcal-cnt-long = <0x00000040>; |
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nvidia,emc-cfg-periodic-qrst; |
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nvidia,emc-configuration = < |
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0x00000020 /* EMC_RC */ |
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0x0000006a /* EMC_RFC */ |
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0x00000017 /* EMC_RAS */ |
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0x00000007 /* EMC_RP */ |
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0x00000005 /* EMC_R2W */ |
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0x0000000c /* EMC_W2R */ |
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0x00000003 /* EMC_R2P */ |
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0x00000011 /* EMC_W2P */ |
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0x00000007 /* EMC_RD_RCD */ |
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0x00000007 /* EMC_WR_RCD */ |
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0x00000002 /* EMC_RRD */ |
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0x00000001 /* EMC_REXT */ |
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0x00000000 /* EMC_WEXT */ |
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0x00000007 /* EMC_WDV */ |
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0x0000000a /* EMC_QUSE */ |
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0x00000009 /* EMC_QRST */ |
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0x0000000b /* EMC_QSAFE */ |
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0x00000011 /* EMC_RDV */ |
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0x00001412 /* EMC_REFRESH */ |
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0x00000000 /* EMC_BURST_REFRESH_NUM */ |
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0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */ |
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0x00000002 /* EMC_PDEX2WR */ |
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0x0000000e /* EMC_PDEX2RD */ |
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0x00000001 /* EMC_PCHG2PDEN */ |
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0x00000000 /* EMC_ACT2PDEN */ |
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0x0000000c /* EMC_AR2PDEN */ |
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0x00000016 /* EMC_RW2PDEN */ |
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0x00000072 /* EMC_TXSR */ |
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0x00000200 /* EMC_TXSRDLL */ |
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0x00000005 /* EMC_TCKE */ |
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0x00000015 /* EMC_TFAW */ |
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0x00000000 /* EMC_TRPAB */ |
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0x00000006 /* EMC_TCLKSTABLE */ |
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0x00000007 /* EMC_TCLKSTOP */ |
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0x00001453 /* EMC_TREFBW */ |
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0x0000000b /* EMC_QUSE_EXTRA */ |
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0x00000006 /* EMC_FBIO_CFG6 */ |
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0x00000000 /* EMC_ODT_WRITE */ |
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0x00000000 /* EMC_ODT_READ */ |
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0x00005088 /* EMC_FBIO_CFG5 */ |
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0xf00b0191 /* EMC_CFG_DIG_DLL */ |
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0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ |
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0x00000008 /* EMC_DLL_XFORM_DQS0 */ |
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0x00000008 /* EMC_DLL_XFORM_DQS1 */ |
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0x00000008 /* EMC_DLL_XFORM_DQS2 */ |
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0x00000008 /* EMC_DLL_XFORM_DQS3 */ |
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0x0000000a /* EMC_DLL_XFORM_DQS4 */ |
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0x0000000a /* EMC_DLL_XFORM_DQS5 */ |
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0x0000000a /* EMC_DLL_XFORM_DQS6 */ |
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0x0000000a /* EMC_DLL_XFORM_DQS7 */ |
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0x00018000 /* EMC_DLL_XFORM_QUSE0 */ |
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0x00018000 /* EMC_DLL_XFORM_QUSE1 */ |
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0x00018000 /* EMC_DLL_XFORM_QUSE2 */ |
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0x00018000 /* EMC_DLL_XFORM_QUSE3 */ |
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0x00000000 /* EMC_DLL_XFORM_QUSE4 */ |
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0x00000000 /* EMC_DLL_XFORM_QUSE5 */ |
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0x00000000 /* EMC_DLL_XFORM_QUSE6 */ |
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0x00000000 /* EMC_DLL_XFORM_QUSE7 */ |
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0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ |
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0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ |
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0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ |
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0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ |
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0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ |
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0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ |
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0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ |
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0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ |
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0x0000000a /* EMC_DLL_XFORM_DQ0 */ |
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0x0000000a /* EMC_DLL_XFORM_DQ1 */ |
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0x0000000a /* EMC_DLL_XFORM_DQ2 */ |
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0x0000000a /* EMC_DLL_XFORM_DQ3 */ |
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0x000002a0 /* EMC_XM2CMDPADCTRL */ |
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0x0800013d /* EMC_XM2DQSPADCTRL2 */ |
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0x22220000 /* EMC_XM2DQPADCTRL2 */ |
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0x77fff884 /* EMC_XM2CLKPADCTRL */ |
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0x01f1f501 /* EMC_XM2COMPPADCTRL */ |
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0x07077404 /* EMC_XM2VTTGENPADCTRL */ |
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0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ |
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0x080001e8 /* EMC_XM2QUSEPADCTRL */ |
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0x0c000021 /* EMC_XM2DQSPADCTRL3 */ |
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0x00000802 /* EMC_CTT_TERM_CTRL */ |
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0x00020000 /* EMC_ZCAL_INTERVAL */ |
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0x00000100 /* EMC_ZCAL_WAIT_CNT */ |
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0x0155000c /* EMC_MRS_WAIT_CNT */ |
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0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ |
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0x00000000 /* EMC_CTT */ |
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0x00000000 /* EMC_CTT_DURATION */ |
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0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */ |
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0xe8000000 /* EMC_FBIO_SPARE */ |
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0xff00ff49 /* EMC_CFG_RSV */ |
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>; |
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}; |
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}; |
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};
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