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35 lines
1.1 KiB
35 lines
1.1 KiB
Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller |
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The DDR controller of the AR7xxx and AR9xxx families provides an interface |
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to flush the FIFO between various devices and the DDR. This is mainly used |
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by the IRQ controller to flush the FIFO before running the interrupt handler |
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of such devices. |
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Required properties: |
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- compatible: has to be "qca,<soc-type>-ddr-controller", |
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"qca,[ar7100|ar7240]-ddr-controller" as fallback. |
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On SoC with PCI support "qca,ar7100-ddr-controller" should be used as |
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fallback, otherwise "qca,ar7240-ddr-controller" should be used. |
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- reg: Base address and size of the controller's memory area |
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- #qca,ddr-wb-channel-cells: Specifies the number of cells needed to encode |
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the write buffer channel index, should be 1. |
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Example: |
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ddr_ctrl: memory-controller@18000000 { |
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compatible = "qca,ar9132-ddr-controller", |
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"qca,ar7240-ddr-controller"; |
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reg = <0x18000000 0x100>; |
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#qca,ddr-wb-channel-cells = <1>; |
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}; |
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... |
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interrupt-controller { |
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... |
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qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>; |
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qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>, |
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<&ddr_ctrl 0>, <&ddr_ctrl 1>; |
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};
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