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40 lines
1.1 KiB
40 lines
1.1 KiB
Tegra124 CPU frequency scaling driver bindings |
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Both required and optional properties listed below must be defined |
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under node /cpus/cpu@0. |
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Required properties: |
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- clocks: Must contain an entry for each entry in clock-names. |
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See ../clocks/clock-bindings.txt for details. |
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- clock-names: Must include the following entries: |
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- cpu_g: Clock mux for the fast CPU cluster. |
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- pll_x: Fast PLL clocksource. |
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- pll_p: Auxiliary PLL used during fast PLL rate changes. |
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- dfll: Fast DFLL clocksource that also automatically scales CPU voltage. |
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Optional properties: |
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- clock-latency: Specify the possible maximum transition latency for clock, |
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in unit of nanoseconds. |
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Example: |
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-------- |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu@0 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a15"; |
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reg = <0>; |
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clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, |
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<&tegra_car TEGRA124_CLK_PLL_X>, |
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<&tegra_car TEGRA124_CLK_PLL_P>, |
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<&dfll>; |
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clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; |
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clock-latency = <300000>; |
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}; |
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<...> |
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};
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