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215 lines
6.1 KiB
215 lines
6.1 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/bus/ti-sysc.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Texas Instruments interconnect target module binding |
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maintainers: |
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- Tony Lindgren <[email protected]> |
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description: |
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Texas Instruments SoCs can have a generic interconnect target module |
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for devices connected to various interconnects such as L3 interconnect |
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using Arteris NoC, and L4 interconnect using Sonics s3220. This module |
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is mostly used for interaction between module and Power, Reset and Clock |
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Manager PRCM. It participates in the OCP Disconnect Protocol, but other |
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than that it is mostly independent of the interconnect. |
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Each interconnect target module can have one or more devices connected to |
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it. There is a set of control registers for managing the interconnect target |
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module clocks, idle modes and interconnect level resets. |
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The interconnect target module control registers are sprinkled into the |
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unused register address space of the first child device IP block managed by |
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the interconnect target module. Typically the register names are REVISION, |
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SYSCONFIG and SYSSTATUS. |
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properties: |
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$nodename: |
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pattern: "^target-module(@[0-9a-f]+)?$" |
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compatible: |
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oneOf: |
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- items: |
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- enum: |
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- ti,sysc-omap2 |
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- ti,sysc-omap4 |
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- ti,sysc-omap4-simple |
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- ti,sysc-omap2-timer |
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- ti,sysc-omap4-timer |
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- ti,sysc-omap3430-sr |
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- ti,sysc-omap3630-sr |
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- ti,sysc-omap4-sr |
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- ti,sysc-omap3-sham |
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- ti,sysc-omap-aes |
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- ti,sysc-mcasp |
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- ti,sysc-dra7-mcasp |
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- ti,sysc-usb-host-fs |
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- ti,sysc-dra7-mcan |
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- ti,sysc-pruss |
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- const: ti,sysc |
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- items: |
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- const: ti,sysc |
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reg: |
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description: |
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Interconnect target module control registers consisting of |
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REVISION, SYSCONFIG and SYSSTATUS registers as defined in the |
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Technical Reference Manual for the SoC. |
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minItems: 1 |
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maxItems: 3 |
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reg-names: |
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description: |
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Interconnect target module control register names consisting |
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of "rev", "sysc" and "syss". |
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oneOf: |
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- minItems: 1 |
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items: |
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- const: rev |
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- const: sysc |
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- const: syss |
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- items: |
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- const: rev |
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- const: syss |
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- enum: [ sysc, syss ] |
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power-domains: |
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description: Target module power domain if available. |
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maxItems: 1 |
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clocks: |
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description: |
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Target module clocks consisting of one functional clock, one |
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interface clock, and up to 8 module specific optional clocks. |
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Some modules may have only the functional clock, and some have |
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no configurable clocks. |
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minItems: 1 |
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maxItems: 4 |
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clock-names: |
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description: |
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Target module clock names like "fck", "ick", "optck1", "optck2" |
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if the clocks are configurable. |
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oneOf: |
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- enum: [ ick, fck, sys_clk ] |
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- items: |
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- const: fck |
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- enum: [ ick. dbclk, osc, sys_clk, dss_clk, ahclkx ] |
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- items: |
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- const: fck |
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- const: phy-clk |
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- const: phy-clk-div |
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- items: |
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- const: fck |
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- const: hdmi_clk |
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- const: sys_clk |
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- const: tv_clk |
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- items: |
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- const: fck |
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- const: ahclkx |
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- const: ahclkr |
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resets: |
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description: |
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Target module reset bit in the RSTCTRL register if wired for the module. |
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Note that the other reset bits should be mapped for the child device |
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driver to use. |
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maxItems: 1 |
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reset-names: |
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description: |
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Target module reset names in the RSTCTRL register, typically named |
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"rstctrl" if only one reset bit is wired for the module. |
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items: |
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- const: rstctrl |
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'#address-cells': |
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enum: [ 1, 2 ] |
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'#size-cells': |
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enum: [ 1, 2 ] |
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ranges: true |
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dma-ranges: true |
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ti,sysc-mask: |
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description: Mask of supported register bits for the SYSCONFIG register |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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ti,sysc-midle: |
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description: List of hardware supported idle modes |
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$ref: /schemas/types.yaml#/definitions/uint32-array |
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ti,sysc-sidle: |
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description: List of hardware supported idle modes |
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$ref: /schemas/types.yaml#/definitions/uint32-array |
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ti,syss-mask: |
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description: Mask of supported register bits for the SYSSTATUS register |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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ti,sysc-delay-us: |
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description: Delay needed after OCP softreset before accessing SYCONFIG |
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default: 0 |
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minimum: 0 |
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maximum: 2 |
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ti,no-reset-on-init: |
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description: Interconnect target module shall not be reset at init |
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type: boolean |
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ti,no-idle-on-init: |
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description: Interconnect target module shall not be idled at init |
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type: boolean |
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ti,no-idle: |
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description: Interconnect target module shall not be idled |
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type: boolean |
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ti,hwmods: |
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description: Interconnect module name to use with legacy hwmod data |
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$ref: /schemas/types.yaml#/definitions/string |
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deprecated: true |
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required: |
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- compatible |
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- '#address-cells' |
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- '#size-cells' |
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- ranges |
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additionalProperties: |
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type: object |
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examples: |
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- | |
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#include <dt-bindings/bus/ti-sysc.h> |
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#include <dt-bindings/clock/omap4.h> |
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target-module@2b000 { |
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compatible = "ti,sysc-omap2", "ti,sysc"; |
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ti,hwmods = "usb_otg_hs"; |
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reg = <0x2b400 0x4>, |
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<0x2b404 0x4>, |
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<0x2b408 0x4>; |
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reg-names = "rev", "sysc", "syss"; |
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clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; |
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clock-names = "fck"; |
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ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | |
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SYSC_OMAP2_SOFTRESET | |
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SYSC_OMAP2_AUTOIDLE)>; |
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ti,sysc-midle = <SYSC_IDLE_FORCE>, |
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<SYSC_IDLE_NO>, |
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<SYSC_IDLE_SMART>; |
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ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
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<SYSC_IDLE_NO>, |
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<SYSC_IDLE_SMART>, |
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<SYSC_IDLE_SMART_WKUP>; |
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ti,syss-mask = <1>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0 0x2b000 0x1000>; |
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};
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