"PublicDescription":"Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
"PublicDescription":"Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.",
"PublicDescription":"Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.",
"PublicDescription":"Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.",
"PublicDescription":"Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.",
"PublicDescription":"Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.",
"PublicDescription":"Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.",
"PublicDescription":"Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue":"2003",
"TakenAlone":"1",
"UMask":"0x1"
},
{
"BriefDescription":"Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
"PublicDescription":"Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue":"50021",
"TakenAlone":"1",
"UMask":"0x1"
},
{
"BriefDescription":"Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.",
"Counter":"0,1,2,3",
"EventCode":"0xB7, 0xBB",
"EventName":"OCR.DEMAND_CODE_RD.L3_MISS",
"MSRIndex":"0x1a6,0x1a7",
"MSRValue":"0x3FBFC00004",
"Offcore":"1",
"PublicDescription":"Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"BriefDescription":"Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
"Counter":"0,1,2,3",
"EventCode":"0xB7, 0xBB",
"EventName":"OCR.DEMAND_CODE_RD.L3_MISS_LOCAL",
"MSRIndex":"0x1a6,0x1a7",
"MSRValue":"0x3F84400004",
"Offcore":"1",
"PublicDescription":"Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.",
"Counter":"0,1,2,3",
"EventCode":"0xB7, 0xBB",
"EventName":"OCR.DEMAND_DATA_RD.L3_MISS",
"MSRIndex":"0x1a6,0x1a7",
"MSRValue":"0x3FBFC00001",
"Offcore":"1",
"PublicDescription":"Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
"Counter":"0,1,2,3",
"EventCode":"0xB7, 0xBB",
"EventName":"OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",
"MSRIndex":"0x1a6,0x1a7",
"MSRValue":"0x3F84400001",
"Offcore":"1",
"PublicDescription":"Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.",
"Counter":"0,1,2,3",
"EventCode":"0xB7, 0xBB",
"EventName":"OCR.DEMAND_RFO.L3_MISS",
"MSRIndex":"0x1a6,0x1a7",
"MSRValue":"0x3F3FC00002",
"Offcore":"1",
"PublicDescription":"Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket.",
"Counter":"0,1,2,3",
"EventCode":"0xB7, 0xBB",
"EventName":"OCR.DEMAND_RFO.L3_MISS_LOCAL",
"MSRIndex":"0x1a6,0x1a7",
"MSRValue":"0x3F04400002",
"Offcore":"1",
"PublicDescription":"Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.",
"Counter":"0,1,2,3",
"EventCode":"0xB7, 0xBB",
"EventName":"OCR.HWPF_L1D_AND_SWPF.L3_MISS",
"MSRIndex":"0x1a6,0x1a7",
"MSRValue":"0x3FBFC00400",
"Offcore":"1",
"PublicDescription":"Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
"PublicDescription":"Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.",
"Counter":"0,1,2,3",
"EventCode":"0xB7, 0xBB",
"EventName":"OCR.HWPF_L3.L3_MISS",
"MSRIndex":"0x1a6,0x1a7",
"MSRValue":"0x94002380",
"Offcore":"1",
"PublicDescription":"Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
"Counter":"0,1,2,3",
"EventCode":"0xB7, 0xBB",
"EventName":"OCR.HWPF_L3.L3_MISS_LOCAL",
"MSRIndex":"0x1a6,0x1a7",
"MSRValue":"0x84002380",
"Offcore":"1",
"PublicDescription":"Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
"Counter":"0,1,2,3",
"EventCode":"0xB7, 0xBB",
"EventName":"OCR.ITOM.L3_MISS_LOCAL",
"MSRIndex":"0x1a6,0x1a7",
"MSRValue":"0x84000002",
"Offcore":"1",
"PublicDescription":"Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches.",
"Counter":"0,1,2,3",
"EventCode":"0xB7, 0xBB",
"EventName":"OCR.OTHER.L3_MISS",
"MSRIndex":"0x1a6,0x1a7",
"MSRValue":"0x3FBFC08000",
"Offcore":"1",
"PublicDescription":"Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
"Counter":"0,1,2,3",
"EventCode":"0xB7, 0xBB",
"EventName":"OCR.OTHER.L3_MISS_LOCAL",
"MSRIndex":"0x1a6,0x1a7",
"MSRValue":"0x3F84408000",
"Offcore":"1",
"PublicDescription":"Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"Counts hardware and software prefetches to all cache levels that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
"Counter":"0,1,2,3",
"EventCode":"0xB7, 0xBB",
"EventName":"OCR.PREFETCHES.L3_MISS_LOCAL",
"MSRIndex":"0x1a6,0x1a7",
"MSRValue":"0x3F844027F0",
"Offcore":"1",
"PublicDescription":"Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches.",
"Counter":"0,1,2,3",
"EventCode":"0xB7, 0xBB",
"EventName":"OCR.READS_TO_CORE.L3_MISS",
"MSRIndex":"0x1a6,0x1a7",
"MSRValue":"0x3F3FC00477",
"Offcore":"1",
"PublicDescription":"Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket.",
"Counter":"0,1,2,3",
"EventCode":"0xB7, 0xBB",
"EventName":"OCR.READS_TO_CORE.L3_MISS_LOCAL",
"MSRIndex":"0x1a6,0x1a7",
"MSRValue":"0x3F04400477",
"Offcore":"1",
"PublicDescription":"Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster.",
"PublicDescription":"Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"Counts streaming stores that missed the local socket's L1, L2, and L3 caches.",
"Counter":"0,1,2,3",
"EventCode":"0xB7, 0xBB",
"EventName":"OCR.STREAMING_WR.L3_MISS",
"MSRIndex":"0x1a6,0x1a7",
"MSRValue":"0x94000800",
"Offcore":"1",
"PublicDescription":"Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
"Counter":"0,1,2,3",
"EventCode":"0xB7, 0xBB",
"EventName":"OCR.STREAMING_WR.L3_MISS_LOCAL",
"MSRIndex":"0x1a6,0x1a7",
"MSRValue":"0x84000800",
"Offcore":"1",
"PublicDescription":"Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"Counts demand data read requests that miss the L3 cache.",
"PublicDescription":"Cycles where at least one demand data read request known to have missed the L3 cache is pending. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.",
"SampleAfterValue":"1000003",
"Speculative":"1",
"UMask":"0x10"
},
{
"BriefDescription":"For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.",
"PublicDescription":"For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.",
"SampleAfterValue":"2000003",
"Speculative":"1",
"UMask":"0x10"
},
{
"BriefDescription":"Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache.",
"PublicDescription":"Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache. Note that this event does not capture all elapsed cycles while the requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.",
"BriefDescription":"Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region",
"PublicDescription":"Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads",
"PublicDescription":"Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.",
