"BriefDescription":"Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
"CollectPEBSRecord":"2",
"Counter":"0,1,2,3",
"EventCode":"0x28",
"EventName":"CORE_POWER.LVL0_TURBO_LICENSE",
"PEBScounters":"0,1,2,3",
"PublicDescription":"Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
"SampleAfterValue":"200003",
"UMask":"0x7"
},
{
"BriefDescription":"Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
"CollectPEBSRecord":"2",
"Counter":"0,1,2,3",
"EventCode":"0x28",
"EventName":"CORE_POWER.LVL1_TURBO_LICENSE",
"PEBScounters":"0,1,2,3",
"PublicDescription":"Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
"SampleAfterValue":"200003",
"UMask":"0x18"
},
{
"BriefDescription":"Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
"CollectPEBSRecord":"2",
"Counter":"0,1,2,3",
"EventCode":"0x28",
"EventName":"CORE_POWER.LVL2_TURBO_LICENSE",
"PEBScounters":"0,1,2,3",
"PublicDescription":"Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions.",
"SampleAfterValue":"200003",
"UMask":"0x20"
},
{
"BriefDescription":"Counts streaming stores that have any type of response.",