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284 lines
6.9 KiB
284 lines
6.9 KiB
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause |
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/* Copyright (c) 2015, The Linux Foundation. All rights reserved. */ |
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/* Copyright (c) 2020 Sartura Ltd. */ |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/iopoll.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of_address.h> |
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#include <linux/of_mdio.h> |
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#include <linux/phy.h> |
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#include <linux/platform_device.h> |
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#include <linux/clk.h> |
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#define MDIO_MODE_REG 0x40 |
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#define MDIO_ADDR_REG 0x44 |
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#define MDIO_DATA_WRITE_REG 0x48 |
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#define MDIO_DATA_READ_REG 0x4c |
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#define MDIO_CMD_REG 0x50 |
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#define MDIO_CMD_ACCESS_BUSY BIT(16) |
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#define MDIO_CMD_ACCESS_START BIT(8) |
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#define MDIO_CMD_ACCESS_CODE_READ 0 |
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#define MDIO_CMD_ACCESS_CODE_WRITE 1 |
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#define MDIO_CMD_ACCESS_CODE_C45_ADDR 0 |
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#define MDIO_CMD_ACCESS_CODE_C45_WRITE 1 |
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#define MDIO_CMD_ACCESS_CODE_C45_READ 2 |
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/* 0 = Clause 22, 1 = Clause 45 */ |
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#define MDIO_MODE_C45 BIT(8) |
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#define IPQ4019_MDIO_TIMEOUT 10000 |
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#define IPQ4019_MDIO_SLEEP 10 |
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/* MDIO clock source frequency is fixed to 100M */ |
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#define IPQ_MDIO_CLK_RATE 100000000 |
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#define IPQ_PHY_SET_DELAY_US 100000 |
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struct ipq4019_mdio_data { |
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void __iomem *membase; |
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void __iomem *eth_ldo_rdy; |
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struct clk *mdio_clk; |
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}; |
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static int ipq4019_mdio_wait_busy(struct mii_bus *bus) |
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{ |
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struct ipq4019_mdio_data *priv = bus->priv; |
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unsigned int busy; |
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return readl_poll_timeout(priv->membase + MDIO_CMD_REG, busy, |
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(busy & MDIO_CMD_ACCESS_BUSY) == 0, |
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IPQ4019_MDIO_SLEEP, IPQ4019_MDIO_TIMEOUT); |
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} |
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static int ipq4019_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
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{ |
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struct ipq4019_mdio_data *priv = bus->priv; |
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unsigned int data; |
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unsigned int cmd; |
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if (ipq4019_mdio_wait_busy(bus)) |
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return -ETIMEDOUT; |
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/* Clause 45 support */ |
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if (regnum & MII_ADDR_C45) { |
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unsigned int mmd = (regnum >> 16) & 0x1F; |
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unsigned int reg = regnum & 0xFFFF; |
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/* Enter Clause 45 mode */ |
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data = readl(priv->membase + MDIO_MODE_REG); |
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data |= MDIO_MODE_C45; |
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writel(data, priv->membase + MDIO_MODE_REG); |
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/* issue the phy address and mmd */ |
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writel((mii_id << 8) | mmd, priv->membase + MDIO_ADDR_REG); |
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/* issue reg */ |
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writel(reg, priv->membase + MDIO_DATA_WRITE_REG); |
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cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_ADDR; |
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} else { |
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/* Enter Clause 22 mode */ |
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data = readl(priv->membase + MDIO_MODE_REG); |
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data &= ~MDIO_MODE_C45; |
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writel(data, priv->membase + MDIO_MODE_REG); |
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/* issue the phy address and reg */ |
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writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG); |
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cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_READ; |
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} |
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/* issue read command */ |
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writel(cmd, priv->membase + MDIO_CMD_REG); |
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/* Wait read complete */ |
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if (ipq4019_mdio_wait_busy(bus)) |
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return -ETIMEDOUT; |
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if (regnum & MII_ADDR_C45) { |
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cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_READ; |
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writel(cmd, priv->membase + MDIO_CMD_REG); |
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if (ipq4019_mdio_wait_busy(bus)) |
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return -ETIMEDOUT; |
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} |
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/* Read and return data */ |
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return readl(priv->membase + MDIO_DATA_READ_REG); |
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} |
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static int ipq4019_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
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u16 value) |
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{ |
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struct ipq4019_mdio_data *priv = bus->priv; |
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unsigned int data; |
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unsigned int cmd; |
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if (ipq4019_mdio_wait_busy(bus)) |
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return -ETIMEDOUT; |
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/* Clause 45 support */ |
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if (regnum & MII_ADDR_C45) { |
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unsigned int mmd = (regnum >> 16) & 0x1F; |
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unsigned int reg = regnum & 0xFFFF; |
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/* Enter Clause 45 mode */ |
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data = readl(priv->membase + MDIO_MODE_REG); |
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data |= MDIO_MODE_C45; |
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writel(data, priv->membase + MDIO_MODE_REG); |
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/* issue the phy address and mmd */ |
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writel((mii_id << 8) | mmd, priv->membase + MDIO_ADDR_REG); |
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/* issue reg */ |
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writel(reg, priv->membase + MDIO_DATA_WRITE_REG); |
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cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_ADDR; |
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writel(cmd, priv->membase + MDIO_CMD_REG); |
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if (ipq4019_mdio_wait_busy(bus)) |
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return -ETIMEDOUT; |
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} else { |
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/* Enter Clause 22 mode */ |
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data = readl(priv->membase + MDIO_MODE_REG); |
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data &= ~MDIO_MODE_C45; |
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writel(data, priv->membase + MDIO_MODE_REG); |
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/* issue the phy address and reg */ |
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writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG); |
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} |
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/* issue write data */ |
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writel(value, priv->membase + MDIO_DATA_WRITE_REG); |
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/* issue write command */ |
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if (regnum & MII_ADDR_C45) |
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cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_WRITE; |
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else |
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cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_WRITE; |
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writel(cmd, priv->membase + MDIO_CMD_REG); |
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/* Wait write complete */ |
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if (ipq4019_mdio_wait_busy(bus)) |
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return -ETIMEDOUT; |
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return 0; |
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} |
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static int ipq_mdio_reset(struct mii_bus *bus) |
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{ |
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struct ipq4019_mdio_data *priv = bus->priv; |
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u32 val; |
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int ret; |
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/* To indicate CMN_PLL that ethernet_ldo has been ready if platform resource 1 |
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* is specified in the device tree. |
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*/ |
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if (priv->eth_ldo_rdy) { |
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val = readl(priv->eth_ldo_rdy); |
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val |= BIT(0); |
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writel(val, priv->eth_ldo_rdy); |
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fsleep(IPQ_PHY_SET_DELAY_US); |
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} |
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/* Configure MDIO clock source frequency if clock is specified in the device tree */ |
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ret = clk_set_rate(priv->mdio_clk, IPQ_MDIO_CLK_RATE); |
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if (ret) |
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return ret; |
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ret = clk_prepare_enable(priv->mdio_clk); |
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if (ret == 0) |
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mdelay(10); |
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return ret; |
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} |
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static int ipq4019_mdio_probe(struct platform_device *pdev) |
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{ |
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struct ipq4019_mdio_data *priv; |
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struct mii_bus *bus; |
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struct resource *res; |
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int ret; |
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bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*priv)); |
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if (!bus) |
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return -ENOMEM; |
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priv = bus->priv; |
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priv->membase = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(priv->membase)) |
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return PTR_ERR(priv->membase); |
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priv->mdio_clk = devm_clk_get_optional(&pdev->dev, "gcc_mdio_ahb_clk"); |
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if (IS_ERR(priv->mdio_clk)) |
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return PTR_ERR(priv->mdio_clk); |
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/* The platform resource is provided on the chipset IPQ5018 */ |
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/* This resource is optional */ |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
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if (res) |
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priv->eth_ldo_rdy = devm_ioremap_resource(&pdev->dev, res); |
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bus->name = "ipq4019_mdio"; |
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bus->read = ipq4019_mdio_read; |
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bus->write = ipq4019_mdio_write; |
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bus->reset = ipq_mdio_reset; |
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bus->parent = &pdev->dev; |
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snprintf(bus->id, MII_BUS_ID_SIZE, "%s%d", pdev->name, pdev->id); |
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ret = of_mdiobus_register(bus, pdev->dev.of_node); |
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if (ret) { |
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dev_err(&pdev->dev, "Cannot register MDIO bus!\n"); |
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return ret; |
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} |
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platform_set_drvdata(pdev, bus); |
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return 0; |
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} |
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static int ipq4019_mdio_remove(struct platform_device *pdev) |
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{ |
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struct mii_bus *bus = platform_get_drvdata(pdev); |
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mdiobus_unregister(bus); |
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return 0; |
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} |
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static const struct of_device_id ipq4019_mdio_dt_ids[] = { |
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{ .compatible = "qcom,ipq4019-mdio" }, |
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{ .compatible = "qcom,ipq5018-mdio" }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, ipq4019_mdio_dt_ids); |
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static struct platform_driver ipq4019_mdio_driver = { |
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.probe = ipq4019_mdio_probe, |
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.remove = ipq4019_mdio_remove, |
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.driver = { |
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.name = "ipq4019-mdio", |
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.of_match_table = ipq4019_mdio_dt_ids, |
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}, |
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}; |
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module_platform_driver(ipq4019_mdio_driver); |
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MODULE_DESCRIPTION("ipq4019 MDIO interface driver"); |
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MODULE_AUTHOR("Qualcomm Atheros"); |
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MODULE_LICENSE("Dual BSD/GPL");
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