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646 lines
17 KiB
646 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* Copyright(c) 2020 Intel Corporation. All rights reserved. */ |
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#include <linux/io-64-nonatomic-lo-hi.h> |
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#include <linux/moduleparam.h> |
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#include <linux/module.h> |
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#include <linux/delay.h> |
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#include <linux/sizes.h> |
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#include <linux/mutex.h> |
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#include <linux/list.h> |
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#include <linux/pci.h> |
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#include <linux/io.h> |
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#include "cxlmem.h" |
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#include "cxlpci.h" |
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#include "cxl.h" |
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|
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/** |
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* DOC: cxl pci |
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* |
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* This implements the PCI exclusive functionality for a CXL device as it is |
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* defined by the Compute Express Link specification. CXL devices may surface |
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* certain functionality even if it isn't CXL enabled. While this driver is |
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* focused around the PCI specific aspects of a CXL device, it binds to the |
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* specific CXL memory device class code, and therefore the implementation of |
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* cxl_pci is focused around CXL memory devices. |
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* |
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* The driver has several responsibilities, mainly: |
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* - Create the memX device and register on the CXL bus. |
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* - Enumerate device's register interface and map them. |
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* - Registers nvdimm bridge device with cxl_core. |
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* - Registers a CXL mailbox with cxl_core. |
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*/ |
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|
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#define cxl_doorbell_busy(cxlds) \ |
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(readl((cxlds)->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET) & \ |
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CXLDEV_MBOX_CTRL_DOORBELL) |
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|
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/* CXL 2.0 - 8.2.8.4 */ |
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#define CXL_MAILBOX_TIMEOUT_MS (2 * HZ) |
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|
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/* |
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* CXL 2.0 ECN "Add Mailbox Ready Time" defines a capability field to |
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* dictate how long to wait for the mailbox to become ready. The new |
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* field allows the device to tell software the amount of time to wait |
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* before mailbox ready. This field per the spec theoretically allows |
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* for up to 255 seconds. 255 seconds is unreasonably long, its longer |
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* than the maximum SATA port link recovery wait. Default to 60 seconds |
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* until someone builds a CXL device that needs more time in practice. |
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*/ |
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static unsigned short mbox_ready_timeout = 60; |
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module_param(mbox_ready_timeout, ushort, 0644); |
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MODULE_PARM_DESC(mbox_ready_timeout, |
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"seconds to wait for mailbox ready / memory active status"); |
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|
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static int cxl_pci_mbox_wait_for_doorbell(struct cxl_dev_state *cxlds) |
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{ |
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const unsigned long start = jiffies; |
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unsigned long end = start; |
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|
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while (cxl_doorbell_busy(cxlds)) { |
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end = jiffies; |
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|
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if (time_after(end, start + CXL_MAILBOX_TIMEOUT_MS)) { |
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/* Check again in case preempted before timeout test */ |
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if (!cxl_doorbell_busy(cxlds)) |
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break; |
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return -ETIMEDOUT; |
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} |
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cpu_relax(); |
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} |
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dev_dbg(cxlds->dev, "Doorbell wait took %dms", |
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jiffies_to_msecs(end) - jiffies_to_msecs(start)); |
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return 0; |
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} |
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|
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#define cxl_err(dev, status, msg) \ |
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dev_err_ratelimited(dev, msg ", device state %s%s\n", \ |
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status & CXLMDEV_DEV_FATAL ? " fatal" : "", \ |
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status & CXLMDEV_FW_HALT ? " firmware-halt" : "") |
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|
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#define cxl_cmd_err(dev, cmd, status, msg) \ |
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dev_err_ratelimited(dev, msg " (opcode: %#x), device state %s%s\n", \ |
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(cmd)->opcode, \ |
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status & CXLMDEV_DEV_FATAL ? " fatal" : "", \ |
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status & CXLMDEV_FW_HALT ? " firmware-halt" : "") |
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|
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/** |
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* __cxl_pci_mbox_send_cmd() - Execute a mailbox command |
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* @cxlds: The device state to communicate with. |
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* @mbox_cmd: Command to send to the memory device. |
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* |
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* Context: Any context. Expects mbox_mutex to be held. |
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* Return: -ETIMEDOUT if timeout occurred waiting for completion. 0 on success. |
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* Caller should check the return code in @mbox_cmd to make sure it |
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* succeeded. |
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* |
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* This is a generic form of the CXL mailbox send command thus only using the |
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* registers defined by the mailbox capability ID - CXL 2.0 8.2.8.4. Memory |
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* devices, and perhaps other types of CXL devices may have further information |
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* available upon error conditions. Driver facilities wishing to send mailbox |
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* commands should use the wrapper command. |
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* |
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* The CXL spec allows for up to two mailboxes. The intention is for the primary |
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* mailbox to be OS controlled and the secondary mailbox to be used by system |
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* firmware. This allows the OS and firmware to communicate with the device and |
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* not need to coordinate with each other. The driver only uses the primary |
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* mailbox. |
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*/ |
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static int __cxl_pci_mbox_send_cmd(struct cxl_dev_state *cxlds, |
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struct cxl_mbox_cmd *mbox_cmd) |
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{ |
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void __iomem *payload = cxlds->regs.mbox + CXLDEV_MBOX_PAYLOAD_OFFSET; |
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struct device *dev = cxlds->dev; |
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u64 cmd_reg, status_reg; |
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size_t out_len; |
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int rc; |
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lockdep_assert_held(&cxlds->mbox_mutex); |
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|
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/* |
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* Here are the steps from 8.2.8.4 of the CXL 2.0 spec. |
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* 1. Caller reads MB Control Register to verify doorbell is clear |
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* 2. Caller writes Command Register |
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* 3. Caller writes Command Payload Registers if input payload is non-empty |
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* 4. Caller writes MB Control Register to set doorbell |
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* 5. Caller either polls for doorbell to be clear or waits for interrupt if configured |
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* 6. Caller reads MB Status Register to fetch Return code |
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* 7. If command successful, Caller reads Command Register to get Payload Length |
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* 8. If output payload is non-empty, host reads Command Payload Registers |
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* |
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* Hardware is free to do whatever it wants before the doorbell is rung, |
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* and isn't allowed to change anything after it clears the doorbell. As |
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* such, steps 2 and 3 can happen in any order, and steps 6, 7, 8 can |
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* also happen in any order (though some orders might not make sense). |
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*/ |
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|
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/* #1 */ |
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if (cxl_doorbell_busy(cxlds)) { |
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u64 md_status = |
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readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); |
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cxl_cmd_err(cxlds->dev, mbox_cmd, md_status, |
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"mailbox queue busy"); |
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return -EBUSY; |
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} |
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cmd_reg = FIELD_PREP(CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK, |
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mbox_cmd->opcode); |
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if (mbox_cmd->size_in) { |
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if (WARN_ON(!mbox_cmd->payload_in)) |
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return -EINVAL; |
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cmd_reg |= FIELD_PREP(CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK, |
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mbox_cmd->size_in); |
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memcpy_toio(payload, mbox_cmd->payload_in, mbox_cmd->size_in); |
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} |
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|
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/* #2, #3 */ |
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writeq(cmd_reg, cxlds->regs.mbox + CXLDEV_MBOX_CMD_OFFSET); |
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/* #4 */ |
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dev_dbg(dev, "Sending command\n"); |
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writel(CXLDEV_MBOX_CTRL_DOORBELL, |
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cxlds->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET); |
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/* #5 */ |
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rc = cxl_pci_mbox_wait_for_doorbell(cxlds); |
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if (rc == -ETIMEDOUT) { |
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u64 md_status = readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); |
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cxl_cmd_err(cxlds->dev, mbox_cmd, md_status, "mailbox timeout"); |
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return rc; |
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} |
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/* #6 */ |
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status_reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_STATUS_OFFSET); |
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mbox_cmd->return_code = |
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FIELD_GET(CXLDEV_MBOX_STATUS_RET_CODE_MASK, status_reg); |
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if (mbox_cmd->return_code != 0) { |
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dev_dbg(dev, "Mailbox operation had an error\n"); |
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return 0; |
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} |
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/* #7 */ |
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cmd_reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_CMD_OFFSET); |
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out_len = FIELD_GET(CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK, cmd_reg); |
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/* #8 */ |
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if (out_len && mbox_cmd->payload_out) { |
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/* |
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* Sanitize the copy. If hardware misbehaves, out_len per the |
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* spec can actually be greater than the max allowed size (21 |
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* bits available but spec defined 1M max). The caller also may |
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* have requested less data than the hardware supplied even |
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* within spec. |
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*/ |
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size_t n = min3(mbox_cmd->size_out, cxlds->payload_size, out_len); |
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memcpy_fromio(mbox_cmd->payload_out, payload, n); |
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mbox_cmd->size_out = n; |
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} else { |
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mbox_cmd->size_out = 0; |
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} |
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return 0; |
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} |
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static int cxl_pci_mbox_send(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd) |
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{ |
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int rc; |
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mutex_lock_io(&cxlds->mbox_mutex); |
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rc = __cxl_pci_mbox_send_cmd(cxlds, cmd); |
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mutex_unlock(&cxlds->mbox_mutex); |
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return rc; |
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} |
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static int cxl_pci_setup_mailbox(struct cxl_dev_state *cxlds) |
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{ |
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const int cap = readl(cxlds->regs.mbox + CXLDEV_MBOX_CAPS_OFFSET); |
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unsigned long timeout; |
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u64 md_status; |
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timeout = jiffies + mbox_ready_timeout * HZ; |
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do { |
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md_status = readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); |
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if (md_status & CXLMDEV_MBOX_IF_READY) |
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break; |
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if (msleep_interruptible(100)) |
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break; |
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} while (!time_after(jiffies, timeout)); |
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if (!(md_status & CXLMDEV_MBOX_IF_READY)) { |
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cxl_err(cxlds->dev, md_status, |
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"timeout awaiting mailbox ready"); |
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return -ETIMEDOUT; |
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} |
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/* |
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* A command may be in flight from a previous driver instance, |
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* think kexec, do one doorbell wait so that |
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* __cxl_pci_mbox_send_cmd() can assume that it is the only |
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* source for future doorbell busy events. |
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*/ |
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if (cxl_pci_mbox_wait_for_doorbell(cxlds) != 0) { |
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cxl_err(cxlds->dev, md_status, "timeout awaiting mailbox idle"); |
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return -ETIMEDOUT; |
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} |
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cxlds->mbox_send = cxl_pci_mbox_send; |
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cxlds->payload_size = |
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1 << FIELD_GET(CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK, cap); |
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/* |
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* CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register |
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* |
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* If the size is too small, mandatory commands will not work and so |
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* there's no point in going forward. If the size is too large, there's |
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* no harm is soft limiting it. |
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*/ |
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cxlds->payload_size = min_t(size_t, cxlds->payload_size, SZ_1M); |
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if (cxlds->payload_size < 256) { |
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dev_err(cxlds->dev, "Mailbox is too small (%zub)", |
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cxlds->payload_size); |
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return -ENXIO; |
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} |
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dev_dbg(cxlds->dev, "Mailbox payload sized %zu", |
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cxlds->payload_size); |
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return 0; |
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} |
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static int cxl_map_regblock(struct pci_dev *pdev, struct cxl_register_map *map) |
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{ |
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void __iomem *addr; |
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int bar = map->barno; |
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struct device *dev = &pdev->dev; |
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resource_size_t offset = map->block_offset; |
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/* Basic sanity check that BAR is big enough */ |
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if (pci_resource_len(pdev, bar) < offset) { |
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dev_err(dev, "BAR%d: %pr: too small (offset: %pa)\n", bar, |
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&pdev->resource[bar], &offset); |
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return -ENXIO; |
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} |
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addr = pci_iomap(pdev, bar, 0); |
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if (!addr) { |
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dev_err(dev, "failed to map registers\n"); |
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return -ENOMEM; |
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} |
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dev_dbg(dev, "Mapped CXL Memory Device resource bar %u @ %pa\n", |
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bar, &offset); |
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map->base = addr + map->block_offset; |
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return 0; |
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} |
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static void cxl_unmap_regblock(struct pci_dev *pdev, |
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struct cxl_register_map *map) |
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{ |
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pci_iounmap(pdev, map->base - map->block_offset); |
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map->base = NULL; |
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} |
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static int cxl_probe_regs(struct pci_dev *pdev, struct cxl_register_map *map) |
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{ |
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struct cxl_component_reg_map *comp_map; |
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struct cxl_device_reg_map *dev_map; |
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struct device *dev = &pdev->dev; |
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void __iomem *base = map->base; |
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switch (map->reg_type) { |
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case CXL_REGLOC_RBI_COMPONENT: |
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comp_map = &map->component_map; |
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cxl_probe_component_regs(dev, base, comp_map); |
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if (!comp_map->hdm_decoder.valid) { |
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dev_err(dev, "HDM decoder registers not found\n"); |
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return -ENXIO; |
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} |
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dev_dbg(dev, "Set up component registers\n"); |
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break; |
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case CXL_REGLOC_RBI_MEMDEV: |
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dev_map = &map->device_map; |
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cxl_probe_device_regs(dev, base, dev_map); |
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if (!dev_map->status.valid || !dev_map->mbox.valid || |
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!dev_map->memdev.valid) { |
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dev_err(dev, "registers not found: %s%s%s\n", |
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!dev_map->status.valid ? "status " : "", |
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!dev_map->mbox.valid ? "mbox " : "", |
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!dev_map->memdev.valid ? "memdev " : ""); |
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return -ENXIO; |
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} |
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dev_dbg(dev, "Probing device registers...\n"); |
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break; |
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default: |
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break; |
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} |
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return 0; |
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} |
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static int cxl_map_regs(struct cxl_dev_state *cxlds, struct cxl_register_map *map) |
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{ |
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struct device *dev = cxlds->dev; |
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struct pci_dev *pdev = to_pci_dev(dev); |
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switch (map->reg_type) { |
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case CXL_REGLOC_RBI_COMPONENT: |
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cxl_map_component_regs(pdev, &cxlds->regs.component, map); |
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dev_dbg(dev, "Mapping component registers...\n"); |
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break; |
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case CXL_REGLOC_RBI_MEMDEV: |
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cxl_map_device_regs(pdev, &cxlds->regs.device_regs, map); |
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dev_dbg(dev, "Probing device registers...\n"); |
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break; |
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default: |
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break; |
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} |
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return 0; |
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} |
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static int cxl_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, |
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struct cxl_register_map *map) |
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{ |
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int rc; |
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rc = cxl_find_regblock(pdev, type, map); |
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if (rc) |
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return rc; |
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rc = cxl_map_regblock(pdev, map); |
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if (rc) |
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return rc; |
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rc = cxl_probe_regs(pdev, map); |
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cxl_unmap_regblock(pdev, map); |
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return rc; |
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} |
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static int wait_for_valid(struct cxl_dev_state *cxlds) |
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{ |
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struct pci_dev *pdev = to_pci_dev(cxlds->dev); |
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int d = cxlds->cxl_dvsec, rc; |
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u32 val; |
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/* |
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* Memory_Info_Valid: When set, indicates that the CXL Range 1 Size high |
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* and Size Low registers are valid. Must be set within 1 second of |
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* deassertion of reset to CXL device. Likely it is already set by the |
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* time this runs, but otherwise give a 1.5 second timeout in case of |
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* clock skew. |
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*/ |
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rc = pci_read_config_dword(pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(0), &val); |
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if (rc) |
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return rc; |
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if (val & CXL_DVSEC_MEM_INFO_VALID) |
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return 0; |
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msleep(1500); |
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rc = pci_read_config_dword(pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(0), &val); |
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if (rc) |
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return rc; |
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if (val & CXL_DVSEC_MEM_INFO_VALID) |
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return 0; |
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return -ETIMEDOUT; |
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} |
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|
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/* |
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* Wait up to @mbox_ready_timeout for the device to report memory |
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* active. |
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*/ |
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static int wait_for_media_ready(struct cxl_dev_state *cxlds) |
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{ |
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struct pci_dev *pdev = to_pci_dev(cxlds->dev); |
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int d = cxlds->cxl_dvsec; |
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bool active = false; |
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u64 md_status; |
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int rc, i; |
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rc = wait_for_valid(cxlds); |
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if (rc) |
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return rc; |
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for (i = mbox_ready_timeout; i; i--) { |
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u32 temp; |
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rc = pci_read_config_dword( |
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pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(0), &temp); |
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if (rc) |
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return rc; |
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active = FIELD_GET(CXL_DVSEC_MEM_ACTIVE, temp); |
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if (active) |
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break; |
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msleep(1000); |
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} |
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|
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if (!active) { |
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dev_err(&pdev->dev, |
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"timeout awaiting memory active after %d seconds\n", |
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mbox_ready_timeout); |
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return -ETIMEDOUT; |
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} |
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md_status = readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); |
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if (!CXLMDEV_READY(md_status)) |
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return -EIO; |
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|
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return 0; |
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} |
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static int cxl_dvsec_ranges(struct cxl_dev_state *cxlds) |
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{ |
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struct cxl_endpoint_dvsec_info *info = &cxlds->info; |
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struct pci_dev *pdev = to_pci_dev(cxlds->dev); |
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int d = cxlds->cxl_dvsec; |
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int hdm_count, rc, i; |
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u16 cap, ctrl; |
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|
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if (!d) |
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return -ENXIO; |
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|
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rc = pci_read_config_word(pdev, d + CXL_DVSEC_CAP_OFFSET, &cap); |
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if (rc) |
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return rc; |
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|
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rc = pci_read_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, &ctrl); |
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if (rc) |
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return rc; |
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|
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if (!(cap & CXL_DVSEC_MEM_CAPABLE)) |
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return -ENXIO; |
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|
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/* |
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* It is not allowed by spec for MEM.capable to be set and have 0 legacy |
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* HDM decoders (values > 2 are also undefined as of CXL 2.0). As this |
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* driver is for a spec defined class code which must be CXL.mem |
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* capable, there is no point in continuing to enable CXL.mem. |
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*/ |
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hdm_count = FIELD_GET(CXL_DVSEC_HDM_COUNT_MASK, cap); |
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if (!hdm_count || hdm_count > 2) |
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return -EINVAL; |
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rc = wait_for_valid(cxlds); |
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if (rc) |
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return rc; |
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info->mem_enabled = FIELD_GET(CXL_DVSEC_MEM_ENABLE, ctrl); |
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|
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for (i = 0; i < hdm_count; i++) { |
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u64 base, size; |
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u32 temp; |
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|
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rc = pci_read_config_dword( |
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pdev, d + CXL_DVSEC_RANGE_SIZE_HIGH(i), &temp); |
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if (rc) |
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return rc; |
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|
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size = (u64)temp << 32; |
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|
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rc = pci_read_config_dword( |
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pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(i), &temp); |
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if (rc) |
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return rc; |
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|
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size |= temp & CXL_DVSEC_MEM_SIZE_LOW_MASK; |
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|
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rc = pci_read_config_dword( |
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pdev, d + CXL_DVSEC_RANGE_BASE_HIGH(i), &temp); |
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if (rc) |
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return rc; |
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|
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base = (u64)temp << 32; |
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|
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rc = pci_read_config_dword( |
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pdev, d + CXL_DVSEC_RANGE_BASE_LOW(i), &temp); |
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if (rc) |
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return rc; |
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|
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base |= temp & CXL_DVSEC_MEM_BASE_LOW_MASK; |
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|
|
info->dvsec_range[i] = (struct range) { |
|
.start = base, |
|
.end = base + size - 1 |
|
}; |
|
|
|
if (size) |
|
info->ranges++; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
|
{ |
|
struct cxl_register_map map; |
|
struct cxl_memdev *cxlmd; |
|
struct cxl_dev_state *cxlds; |
|
int rc; |
|
|
|
/* |
|
* Double check the anonymous union trickery in struct cxl_regs |
|
* FIXME switch to struct_group() |
|
*/ |
|
BUILD_BUG_ON(offsetof(struct cxl_regs, memdev) != |
|
offsetof(struct cxl_regs, device_regs.memdev)); |
|
|
|
rc = pcim_enable_device(pdev); |
|
if (rc) |
|
return rc; |
|
|
|
cxlds = cxl_dev_state_create(&pdev->dev); |
|
if (IS_ERR(cxlds)) |
|
return PTR_ERR(cxlds); |
|
|
|
cxlds->serial = pci_get_dsn(pdev); |
|
cxlds->cxl_dvsec = pci_find_dvsec_capability( |
|
pdev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE); |
|
if (!cxlds->cxl_dvsec) |
|
dev_warn(&pdev->dev, |
|
"Device DVSEC not present, skip CXL.mem init\n"); |
|
|
|
cxlds->wait_media_ready = wait_for_media_ready; |
|
|
|
rc = cxl_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map); |
|
if (rc) |
|
return rc; |
|
|
|
rc = cxl_map_regs(cxlds, &map); |
|
if (rc) |
|
return rc; |
|
|
|
/* |
|
* If the component registers can't be found, the cxl_pci driver may |
|
* still be useful for management functions so don't return an error. |
|
*/ |
|
cxlds->component_reg_phys = CXL_RESOURCE_NONE; |
|
rc = cxl_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &map); |
|
if (rc) |
|
dev_warn(&pdev->dev, "No component registers (%d)\n", rc); |
|
|
|
cxlds->component_reg_phys = cxl_regmap_to_base(pdev, &map); |
|
|
|
rc = cxl_pci_setup_mailbox(cxlds); |
|
if (rc) |
|
return rc; |
|
|
|
rc = cxl_enumerate_cmds(cxlds); |
|
if (rc) |
|
return rc; |
|
|
|
rc = cxl_dev_state_identify(cxlds); |
|
if (rc) |
|
return rc; |
|
|
|
rc = cxl_mem_create_range_info(cxlds); |
|
if (rc) |
|
return rc; |
|
|
|
rc = cxl_dvsec_ranges(cxlds); |
|
if (rc) |
|
dev_warn(&pdev->dev, |
|
"Failed to get DVSEC range information (%d)\n", rc); |
|
|
|
cxlmd = devm_cxl_add_memdev(cxlds); |
|
if (IS_ERR(cxlmd)) |
|
return PTR_ERR(cxlmd); |
|
|
|
if (range_len(&cxlds->pmem_range) && IS_ENABLED(CONFIG_CXL_PMEM)) |
|
rc = devm_cxl_add_nvdimm(&pdev->dev, cxlmd); |
|
|
|
return rc; |
|
} |
|
|
|
static const struct pci_device_id cxl_mem_pci_tbl[] = { |
|
/* PCI class code for CXL.mem Type-3 Devices */ |
|
{ PCI_DEVICE_CLASS((PCI_CLASS_MEMORY_CXL << 8 | CXL_MEMORY_PROGIF), ~0)}, |
|
{ /* terminate list */ }, |
|
}; |
|
MODULE_DEVICE_TABLE(pci, cxl_mem_pci_tbl); |
|
|
|
static struct pci_driver cxl_pci_driver = { |
|
.name = KBUILD_MODNAME, |
|
.id_table = cxl_mem_pci_tbl, |
|
.probe = cxl_pci_probe, |
|
.driver = { |
|
.probe_type = PROBE_PREFER_ASYNCHRONOUS, |
|
}, |
|
}; |
|
|
|
MODULE_LICENSE("GPL v2"); |
|
module_pci_driver(cxl_pci_driver); |
|
MODULE_IMPORT_NS(CXL);
|
|
|